CN111083547A - Method, apparatus, and medium for balancing video frame rate error based on trigger mode - Google Patents
Method, apparatus, and medium for balancing video frame rate error based on trigger mode Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 230000015654 memory Effects 0.000 claims description 15
- 238000004590 computer program Methods 0.000 claims description 11
- 239000000872 buffer Substances 0.000 claims description 8
- 230000005540 biological transmission Effects 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 10
- 230000001960 triggered effect Effects 0.000 description 4
- 230000009365 direct transmission Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
- H04N21/440281—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by altering the temporal resolution, e.g. by frame skipping
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Abstract
The invention discloses a method, equipment and a medium for balancing video frame rate errors based on a trigger mode, wherein the method comprises the steps of setting clock frequencies of a video acquisition end and a video display end so as to meet the requirements of video frame rate consistency and display resolution; setting a time sequence parameter of a video display end to be n lines of blanking areas less than a standard time sequence parameter; n is a positive integer; generating a frame trigger control signal according to the frame rate of the video acquisition end so as to start the video display end to display each frame of video in real time; the missing n line blanking regions of the video display terminal compensate for the deviation by waiting for the time interval for the next frame to trigger the control signal. The method successfully solves the problem that the frame rates of the video acquisition end and the video display end are inconsistent through a mode of waiting for compensation based on frame rate triggering of the video acquisition end and frame rate triggering of the video display end, ensures that the display frame rate is consistent with the video source frame rate, simultaneously realizes display delay of the most line levels, and meets the requirement of low-delay application of the video.
Description
Technical Field
The present invention relates to video processing technologies, and in particular, to a method, an apparatus, and a medium for balancing video frame rate errors based on a trigger mode.
Background
The real-time nature of video display is increasingly important. For example, the camera is used for replacing an external rearview mirror to observe the scene of the road condition outside the automobile, so that a high requirement is put forward on the real-time performance of video display. According to the method, the problem of frame rate error is solved by a frame loss or frame folding mode, on one hand, a large buffer space is needed, on the other hand, display is delayed greatly, and the requirement of low-delay application cannot be met. Obviously, the video is directly transmitted from the video acquisition terminal to the video display terminal, so that the display delay can be reduced, however, in the process of acquiring and displaying the video, because the clock source frequencies of the video acquisition terminal and the video display terminal have errors, the video frame rates at the two terminals have errors, if the frame rate errors are not eliminated, the video acquisition and display cannot be balanced due to the cumulative effect, and therefore a new mode must be found to solve the problem of the video frame rate errors at the two terminals.
Disclosure of Invention
In order to solve the problem of frame rate errors of videos at two ends, embodiments of the present invention provide a method, an apparatus, and a medium for balancing a video frame rate error based on a trigger mode, so as to implement low-latency video transmission and ensure that a display frame rate is consistent with a video source frame rate.
In order to achieve the purpose, the technical scheme of the invention is as follows:
in a first aspect, an embodiment of the present invention provides a method for balancing a video frame rate error based on a trigger mode, where the method includes:
setting clock frequencies of a video acquisition end and a video display end to meet the requirements of video frame rate consistency and display resolution;
setting a time sequence parameter of a video display end to be n lines of blanking areas less than a standard time sequence parameter; n is a positive integer;
generating a frame trigger control signal according to the frame rate of the video acquisition end so as to start the video display end to display each frame of video in real time;
the missing n line blanking regions of the video display terminal compensate for the deviation by waiting for the time interval for the next frame to trigger the control signal.
Furthermore, the timing parameter of the video display end is less than the standard timing parameter by one line of blanking area in the VFP interval.
Further, the blanking area of the line which is lacked at the video display end compensates the deviation by waiting for the time interval triggered by the next frame:
when the frame rate of the video acquisition end is slightly larger than that of the video display end, the length of the missing blanking area of the line is slightly smaller than the length of the standard time sequence;
when the frame rate of the video acquisition end is slightly less than that of the video display end, the length of the missing line blanking area is slightly greater than the standard time sequence length.
Further, the line blanking region waiting for compensation retains the line synchronization signal and is adjusted only by the blanking region space following the line synchronization signal.
Further, the n line blanking areas missing from the video display end compensate the deviation by waiting for the time interval of the next frame trigger control signal:
when the frame rate of the video acquisition end is slightly larger than that of the video display end, the length of the missing n-line blanking area is slightly smaller than the length of the standard time sequence;
when the frame rate of the video acquisition end is slightly less than that of the video display end, the length of the missing n-line blanking area is slightly greater than the length of the standard time sequence.
Further, the method for balancing the video frame rate error based on the trigger mode further includes:
according to the delay condition of the video transmission path, a buffer unit with a proper space is arranged to adjust the trigger point position of the balance frame, so that the display delay of the maximum line level is realized.
In a second aspect, an embodiment of the present invention provides an apparatus for balancing video frame rate errors based on a trigger mode, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the above-mentioned method steps when executing the computer program.
In a third aspect, the present invention provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the computer program implements the method steps as described above
Compared with the prior art, the invention has the beneficial effects that:
the method successfully solves the problem that the frame rates of the video acquisition end and the video display end are inconsistent through a mode of waiting for compensation based on frame rate triggering of the video acquisition end and frame rate triggering of the video display end, ensures that the display frame rate is consistent with the video source frame rate, simultaneously realizes display delay of the most line levels, and meets the requirement of low-delay application of the video.
Drawings
FIG. 1 is a schematic diagram of a video stream direct transmission structure;
fig. 2 is a flowchart of a method for balancing video frame rate errors based on a trigger mode according to embodiment 1 of the present invention;
FIG. 3 is a diagram of a standard timing format;
fig. 4 is a practical timing chart of the method provided by embodiment 1 of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and detailed description.
The timing format of video includes an Active area (Active area) for transmitting Active video data and a Blanking area (Blanking area) for transmitting a synchronization signal, and video timing content contains the synchronization signal and the video signal.
Example 1:
as shown in fig. 1, the schematic diagram of the entire video direct transmission path includes video acquisition, video pre-processing, video caching, video post-processing, time sequence establishment, and video display; the invention mainly aims at the frame rate deviation, and utilizes the tiny deviation to compensate the frame rate deviation in the virtual frame time sequence establishing part.
The method for balancing video frame rate errors based on the trigger mode provided by the embodiment can be applicable to an end-to-end direct transmission scene from Camera to display equipment of all videos.
Specifically, as shown in fig. 2, the method for balancing video frame rate errors based on a trigger manner provided in this embodiment includes the following steps:
21. setting the clock frequencies of a video acquisition end and a video display end according to the video frame rate consistency and the display resolution requirement; if the frequency of two ends is 148.5MHz when the frequency is transmitted from 1080p/60Hz to 1080p/60Hz, and if the frequency is from 1080p/60Hz to 720p/60Hz, the clock frequency of a video acquisition end is 148.5MHz, and the clock frequency of a video display end is 74.5 MHz.
22. Based on the video frame rate consistency and the display resolution, a plurality of line blanking areas with the time sequence parameter less than the standard time sequence parameter of the video display end are set, so that the video display end finishes the transmission of the previous frame data at the time point triggered by each frame, and meanwhile, the length of the line can be adjusted according to the frame rate of the video acquisition end to compensate the frame rate deviation.
23. Designing a frame trigger control signal based on a video acquisition end frame rate; specifically, the frame trigger control signal is a fixed point selected from the video capture end for triggering, and may be selected at any position of the video format, such as a vsync trigger edge of each frame, for example, a position of the first valid data, for example, a position of the nth valid data, and so on. I.e., the displayed frame rate is ultimately equivalent to the acquired frame rate, thus eliminating the offset.
24. Starting a video display end to display each frame of video in real time based on the frame trigger control signal;
25. based on the consistent video frame rate, the video display terminal compensates the deviation by waiting for the time interval triggered by the next frame.
Therefore, the method successfully solves the problem that the frame rates of the video acquisition end and the video display end are inconsistent through a mode of waiting for compensation based on frame rate triggering of the video acquisition end and frame-to-frame triggering of the video display end, ensures that the display frame rate is consistent with the video source frame rate, simultaneously realizes the display delay of the maximum row level and meets the requirement of low-delay application of the video.
Preferably, for the convenience of implementation, the timing parameter at the video display end is one line less than the standard timing parameter in the VFP interval, certainly not necessarily one line less in the VFP interval, and may be several lines less in other blanking areas (such as vbp/vsync), and it is easier to implement only one line less in the VFP interval.
Specifically, the line of blanking areas missing from the video display end is compensated by means of waiting for video interframe trigger, and the length of the line of blanking areas waiting may not be consistent with the standard timing length based on the frame rate errors of the video acquisition end and the video display end. When the frame rate of the video acquisition end is slightly larger than that of the video display end, the length of the blanking area of the line is slightly smaller than the length of the standard time sequence; when the frame rate of the video acquisition end is slightly less than that of the video display end, the length of the line blanking area is slightly greater than the length of the standard time sequence. Based on the length balance of the blanking area of the line, the video display end can maintain the frame rate to be consistent with that of the video acquisition end, and normal real-time display is ensured.
When the timing parameter of the video display end lacks n (a positive integer with n being greater than 1) line blanking areas compared with the standard timing parameter, because the trigger signal is provided by the video acquisition end, the timing of the video acquisition end is complete, the timing of each frame is consistent, for example, the first point trigger is set, each frame initiates one trigger at the position of the point, the lack of the n line blanking areas is specific to the video display end, the lack of the n line blanking areas is utilized, each trigger of the video acquisition end can be ensured, the display end finishes sending the previous frame, the state of the triggered next frame is waited, a new trigger cannot occur temporarily, the display of the previous frame is not finished, and the length of the lack of the n line can be slightly longer or slightly shorter than the actual length in consideration of the deviation of the two, so that the deviation of the two is counteracted.
In addition, in order to further ensure the consistency of the timing format, a line blanking area waiting for the line synchronization signal can be reserved, and only the blanking area space behind the line synchronization signal is used for adjustment, namely, the offset is balanced by setting the length of the line, but the hsync area of the line is reserved, and only the length of a part of hblanking area behind the hsync area of the line is adjusted for balance, so that the whole timing is basically consistent, and the condition that one hsync is less can not occur.
In addition, based on the delay condition of the video transmission path, a buffer unit with a proper space is arranged, the trigger point position of the balance frame is adjusted, and the display delay of the maximum line level is realized. Specifically, the buffer unit may be a simple FIFO, data provided by the video capture end is buffered in advance, a frame trigger signal is generated after a certain amount of data is buffered, the frame trigger signal may select a fixed point of each frame of video at the video capture end to perform frame triggering, and in practice, the fixed point may be found by the buffer unit, for example, in practical application, the first data may be selected as a trigger point, and the trigger point may be started by buffering the first data of one frame of video at each time in the buffer unit, and so on, but this is only an implementation scheme of triggering, and the setting of the trigger point and the setting of the buffer unit may be adjusted according to specific application.
FIG. 3 is a schematic diagram of a standard timing format, the first is a row timing diagram including hfp/hsync/hbp/active region, the second is a column timing diagram including vfp/vsync/vbp/active region;
FIG. 4 is a diagram of an actual timing diagram after the method of the present embodiment is applied, comparing to see that the row timing diagram is consistent, except for the last row, which may be slightly larger or smaller than the standard row timing, and this comparison is not shown; the column timing diagram is just one row less at vfp, compensated by waiting;
comparing fig. 3 and 4, it can be seen that the timing formats actually displayed are substantially consistent.
In summary, the method for balancing the video frame rate error based on the trigger method provided by the embodiment has the following technical advantages compared with the prior art:
1. in the prior art, a frame loss or frame overlapping method is adopted to eliminate frame rate errors, so that the actual video display frame rate is inconsistent with the video source frame rate.
2. The traditional technology frame dropping or frame overlapping mode needs a frame buffer storage unit when realizing low-delay video transmission, the cost is too high, when DDR storage is adopted, due to the problems of bandwidth, delay, response speed and the like, the real-time performance of video transmission can be reduced, and the application requirement can not be met for scenes with high real-time performance requirement. The method only needs a proper line cache storage unit, greatly reduces the cache cost, can display the video from the acquisition, only has line-level delay, and really achieves low delay.
Example 2:
the present embodiment provides an apparatus for balancing video frame rate errors based on a trigger mode, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the method steps described in embodiment 1 when executing the computer program.
Example 3:
the present embodiment provides a computer-readable storage medium, which stores a computer program that, when executed by a processor, implements the method steps described in embodiment 1.
The above-described embodiments of the system and apparatus are only schematic, wherein the modules described as separate parts may or may not be physically separate, and the parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above detailed description of the embodiments, those skilled in the art will clearly understand that the embodiments may be implemented by software plus a necessary general hardware platform, and may also be implemented by hardware. Based on such understanding, the above technical solutions may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, wherein the storage medium includes a Read-Only Memory (ROM), a Random Access Memory (RAM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), a One-time Programmable Read-Only Memory (OTPROM), an Electrically Erasable rewritable Read-Only Memory (EEPROM), a compact disc-Read-Only Memory (CD-ROM) or other magnetic disk memories, a magnetic tape Memory, a magnetic disk, a magnetic tape Memory, a magnetic tape, and a magnetic tape, Or any other medium which can be used to carry or store data and which can be read by a computer.
The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention accordingly, and not to limit the protection scope of the present invention accordingly. All equivalent changes or modifications made in accordance with the spirit of the present disclosure are intended to be covered by the scope of the present disclosure.
Claims (8)
1. A method for balancing video frame rate error based on a trigger mode is characterized by comprising the following steps:
setting clock frequencies of a video acquisition end and a video display end to meet the requirements of video frame rate consistency and display resolution;
setting a time sequence parameter of a video display end to be n lines of blanking areas less than a standard time sequence parameter; n is a positive integer;
generating a frame trigger control signal according to the frame rate of the video acquisition end so as to start the video display end to display each frame of video in real time;
the missing n line blanking regions of the video display terminal compensate for the deviation by waiting for the time interval for the next frame to trigger the control signal.
2. The method as claimed in claim 1, wherein the timing parameter of the video display end is one line less blanking area than the standard timing parameter in the VFP interval.
3. The method as claimed in claim 2, wherein the blanking region of the line missing from the video display end is compensated for the deviation by waiting for the time interval of the next frame trigger:
when the frame rate of the video acquisition end is slightly larger than that of the video display end, the length of the missing blanking area of the line is slightly smaller than the length of the standard time sequence;
when the frame rate of the video acquisition end is slightly less than that of the video display end, the length of the missing line blanking area is slightly greater than the standard time sequence length.
4. The method of claim 3, wherein the line blanking interval waiting for compensation retains the line sync signal and only uses the blanking interval space following the line sync signal to adjust.
5. The method for balancing video frame rate error based on trigger mode as claimed in claim 1, wherein the n line blanking areas missing from the video display end compensate for the deviation by waiting for the time interval of the next frame trigger control signal:
when the frame rate of the video acquisition end is slightly larger than that of the video display end, the length of the missing n-line blanking area is slightly smaller than the length of the standard time sequence;
when the frame rate of the video acquisition end is slightly less than that of the video display end, the length of the missing n-line blanking area is slightly greater than the length of the standard time sequence.
6. The method for balancing video frame rate error based on trigger mode as claimed in claim 1, further comprising:
according to the delay condition of the video transmission path, a buffer unit with a proper space is arranged to adjust the trigger point position of the balance frame, so that the display delay of the maximum line level is realized.
7. An apparatus for trigger-based video frame rate error balancing, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method steps of any of claims 1-6 when executing the computer program.
8. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method steps of any one of claims 1 to 6.
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| CN111083547B (en) | 2022-07-29 |
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