Description of drawings
Fig. 1 is with the block diagram form explanation employed primary clustering relevant with embodiments of the invention;
Fig. 2 illustrates the form of frame according to an embodiment of the invention;
Fig. 3 A and Fig. 3 B illustrate the form of first packet and packet subsequently respectively;
Fig. 4 A and Fig. 4 B illustrate the tissue of the video data in the packet according to an embodiment of the invention;
Fig. 5 A and Fig. 5 B illustrate the tissue of the voice data in the packet according to an embodiment of the invention;
Fig. 6 and Fig. 7 illustrate the element of header included in the frame according to an embodiment of the invention;
Fig. 8 explanation is gathered so that form the bag of a frame according to an embodiment of the invention through combination;
Fig. 9 A-9D illustrates an alternate embodiment of the present invention, wherein uses the variant of SDTI frame according to embodiments of the invention;
Fig. 9 E illustrates an alternate embodiment, and wherein transmitter separates SDTI stream and makes it spread all over a plurality of passages;
Figure 10 is performed with the flow chart formal specification according to an embodiment of the invention so that the action of the external definition between a computer and the hardware interface is provided;
Figure 11 illustrates the register memory mapping of interface device according to an embodiment of the invention;
Figure 12 illustrates the tissue of the A/V global register that interface of the present invention contains;
Figure 13 illustrates the tissue of the global state register that interface device of the present invention contains;
Control register when Figure 14 illustrates waiting of containing in the interface device of the present invention;
Figure 15 illustrates the tissue of the flow control register that contains in the interface device of the present invention;
The tissue of channel register when Figure 16 illustrates waiting of containing in the interface device of the present invention.
Embodiment
Note Fig. 1, with block diagram form showed through connecting in case between a computer 100 and client 102 assembly of transmission of audio and video data, described computer and client are connected to interface 106 by bus 104.Computer 100 in the preferred embodiment is one can be handled video and voice data and can discern form with one and show described data computing device to a user.These devices comprise desktop, on knee and palmtop computer.As the related client 102 of this paper are a video consumer or video production persons, and comprise as digital camera with such as this class device of the video storage device of linear and random access device.Comprise as the related bus 104 of this paper and physical connection between computer 100 and the interface 106 also to comprise the serial protocol that device met that communicates by by bus 104.In a preferred embodiment, bus 104 is utilized I EEE 1394 serial bus protocols that are called as live wire (Firewire).Interface 106 is accepted analog-and digital-input from client 102, and described input is converted to the spendable scan line of carrying out of audio/video player on computer 100.In an alternate embodiment, interface 106 is accepted the compressed signal of a digital compression/not and is transmitted the subclass of described whole signal or described signal from client 102.In one embodiment, interface 106 will be imported branch framing 108, pass to computer 100 by bus 104.
The form of explanation frame 108 among Fig. 2.Frame 108 comprises a video header 110, video blocks 112, audio block 114, and optionally comprises an audio header 116.With respect to the voice data in the sampling of the video data in the video blocks 112 audio block 114.The audio samples counting of every frame changes according to defined number in the ANSI/SMPTE272M specification, and this specification is incorporated herein by reference in full.Audio samples counting beat is upward to divide necessary at NTSC frame frequency (29.97fps) an integer sample of per second.Similarly, the variable sizeization of frame 108 is so that be fit to various video formats, such as PAL or NTSC and 8 or 10 digital video data, and such as audio format of 16 and 24 of 48Khz and 96Khz or the like.Similarly, the frame sign of packed data can change so that be fit to compressed format.In one embodiment, video blocks 112 and audio block or compression blocks have a pre-sizing so that make analysis frame 108 simple also feasible application programs such as the direct memory access (DMA) program need processing expenditure seldom.In a part of video blocks 112 or audio block 114 is not to be full of fully under the data conditions, the remainder of usable zero filling block 112,114.In one embodiment, the data that contained in video blocks 112 and the audio block 114 are not compressed, and have further reduced the processing expenditure on the interface 106, and have reduced the needed processing expenditure of gunzip of operation on computer 100.
In case the input that is received from client 102 is changed and is converted into scan line and it is organized the incoming frame 108, interface 106 send a frame with regard to each vertical blanking interval in case provide with computer 100 synchronously.Computer 100 can draw described vertical blanking interval from the frequency of the frame that received and make himself and the Voice ﹠ Video data sync of importing frame 108 into that is received from interface 106.Preserved the processing resource by this way, this is owing to need not carry out synchronously it when receiving each frame, therefore provides the Voice ﹠ Video of the better quality performance on the computer 100 to show.
Fig. 3 A and 3B illustrate the form of first packet and packet subsequently respectively.
The tissue of the video data in Fig. 4 A and the 4B explanation packet.
The tissue of the voice data in Fig. 5 A and the 5B explanation packet.
Fig. 6 illustrates the content of video header 110.Comprising each sample of indication have how many positions form mark 130, smpte time code 132, increase progressively frame counter 134, audio frequency cycle count 136, audio samples counting 138, channel counts 140, block size byte count 142, audio format mark 144 and video format mark 146.Audio samples counting 138 indication numbers of samples, it is consistent with a beat.Value in the audio frequency cycle count 136 is indicated the position in the described beat.In an alternate embodiment, some content of video header 110 can be moved or copies in the optional audio header 116.Show an alternative view of video header 110 among Fig. 7, it shows byte count, data length and a framing bit.
As illustrated in fig. 8, frame 108 is formed by a plurality of bags 150 structures of pre-sizing.Be associated with each bag be one 1394 grades the time packet head.Transfer of data according to the present invention utilizes a sync bit to find the beginning of a frame.First bag in the frame 108 indicates described sync bit.This allows computer 100 recognition data stream when receiving data flow, thereby further by allowing computer 100 to make the frame stream that is received from interface 106 reduce processing expenditure synchronously.
In an alternate embodiment of the present invention, illustrated in 9E as Fig. 9 A, can utilize the frame that meets serial digital interface (SDI) standard.In these embodiments, bus 104 meets IEEE 1394B serial bus protocol so that adapt to the data rate restriction that described SDI standard is stated.As described above, interface 106 forms frame by the SDTI frame of the Voice ﹠ Video data of establishment scan line, execution deinterleave, branch packetize and establishment fixed size from the input that is received.Depend on processing resource available on computer 100, interface 106, client 102 or other device, can make various modifications the SDTI frame.As described above, make the vertical blanking interval of the transmission of the SDTI frame that is sent by bus 104 and institute's acknowledge(ment) signal synchronous.
As shown in Fig. 9 A, SDTI frame 160 has two parts usually: vertical blanking part 162 and horizontal flyback sweep 164.Perhaps, in another embodiment (Fig. 9 B), for further synchronously and the purpose of fault detect (such as data of recovering to be lost in the transmission or generation bus reset), SDTI frame header 166 is added in the SDTI frame 160, described frame header 166 is one to have the header of a sync bit and a frame count.In this embodiment, comprise a frame count sync bit in the SDTI frame header 166, and SDTI frame header 166 is synchronous with vertical blanking part 162.For instance, can not read packed data or require at interface 106 and SDTI frame 160 can be transferred to computer 100 in the application of excessive upgrading of interface 106, wherein carry out processing in a non real-time mode SDTI stream by software.Perhaps, as shown in Fig. 9 C, can construct does not have the SDTI of horizontal flyback sweep 164 frame 160 so that further reduce processing expenditure.As shown in Fig. 9 D, also can utilize in one embodiment to be configured to not have horizontal flyback sweep but to have the SDTI frame of header 166.In yet another embodiment, as shown in Fig. 9 E, can between a plurality of passages, cut apart described SDTI frame, and described frame also comprises SDTI frame header 166.In this embodiment, transmitter is slit into two halves with described SDTI flow point, and a half line is by passage A transmission, and second half transmits by channel B.An additional header of each partial frame can be used for helping the reassembled frame data.
In the another aspect of the present invention, can utilize external definition to make the transfer of data between computer 100, interface 106 and the client 102 synchronous.In one embodiment, client 102 comprises a high-quality reference clock 180 (Fig. 1), its can be used for making on the interface 106 clock 182 synchronously and prevent that the buffer 184 on the interface 106 from overflowing.In this embodiment, on the interface 106 according to 106 transmission data frequency draws the value of the reference clock 180 on the client 102 from computer 102 to interface.For carrying out flow control, between the frame transmission, skip circulation.The circulation of skipping increases the time quantum between the frame transmission so that the data rate of frame transmission is slack-off.Note Figure 10, at reference number 200 places, computer polling interface 106 is come the size of read buffers 184.Although be the described buffer of term appellation of serve exemplary purposes such as " bigger " and " less ", should be appreciated that, under the situation of the buffer of fixed size, big and than the degree of filling of this buffer of little finger of toe.At reference number 202 places, computer 100 sends a plurality of frames to interface 106 then.At reference number 204 places, computer 100 polling interface 106 is once more judged the size of buffer 184.If buffer 184 had had growth (judging reference number 206 places) in size since last time since the poll big or small to it, control proceeds to reference number 208 places so, the delay that increases between the frame that sends to interface 106 of computer 100 herein.In one embodiment, the delay between institute's transmit frame is 125 milliseconds.In another embodiment, by some frame modulation are postponed to obtain fractional delay.For instance, be 2.5 to take advantage of 1.25 microseconds if require delay between the frame, the alternate frame of (intersperse) several 2 and 3 circulations (125 microsecond) that intersperse so postpones.Reference number 202 places are returned in control then, frame is sent to interface 106 herein, and extra delay is arranged between the frame.Yet, return and judge reference number 206 places, if buffer 184 did not increase since the poll big or small to it in size since last time, control is converted to and judges reference number 210 places so.Judging reference number 210 places, if buffer 206 reduces in size, control is converted to reference number 212 places so, reduces to send to delay between the frame of interface 106 from computer 100 herein.In one embodiment, this amount that reduces also is 125Ms.Control is converted to reference number 202 places then, frame is sent to interface 106 from computer 100 herein, and the delay that reduces is arranged between the frame.Return and judge reference number 210 places,, do not need to adjust the delay between the frame so, and control is converted to reference number 202 places if the size of buffer 184 did not also reduce since the poll to the size of buffer 184 since last time.
Interface 106 comprises a serial unit 300, and it is used to make it possible to communicate by bus 104.Serial unit 300 comprises a unit catalogue 302 as shown in table 1.
Title | Keyword | Value |
Unit_Spec_ID |
| 0×12 | 0×000a27 |
Unit_SW_Version | 0×13 | 0×000022 |
Unit_Register_Location | 0×54 | The Csr_offset of register |
Unit_Signals_Supported |
| 0×55 | The RS232 signal of being supported |
Table 1
The Unit_Spec_ID value is specified the mechanism of the architecture definition of being responsible for serial unit 300.The Unit_SW_Version value is in conjunction with the common software interface of specifying described unit of Unit_Spec_ID value.The side-play amount of the home address space of the target devices of the described serial unit register of Unit_Register_Location value appointment.The Unit_Signals_Supported value is specified and is supported which RS-232 signal (as shown in table 2).If from described serial unit catalogue 302, omit this, do not support these signals so.
The hurdle | The position | Describe |
Be ready for sending (RTS) | 0 | If support RTS/RFR with regard to set |
Zero clearing sends (CTS) | 1 | If support CTS with regard to set |
DSR (DSR) | 2 | If support DSR with regard to set |
Transfer of data ready (DTR) | 3 | If support DTR with regard to set |
Jingle bell indication (RI) | 4 | If support RI with regard to set |
Carrier wave (CAR) | 5 | If support CAR/DCD with regard to set |
Keep | [31..6] | Keep |
Table 2
Also comprise serial location register mapping 304 in the serial unit 300, it relates to the register that contains in the serial unit 300.The tissue of showing serial unit register mappings 304 in the table 3.
The hexadecimal skew | Title | Access | Size (quad) | Value |
0×0 | Land | W | | 2 | The address of the serial register of starter |
0×8 | Withdraw from | W | 1 | Any value |
0×c | Reconnect | W | | 1 | The node ID of starter |
0×10 | T * FIFO is big | R | | 1 | The byte-sized of T * FIFO |
0×14 | R * FIFO is big | R | | 1 | The byte-sized of R * FIFO |
0×18 | State | R | | 1 | CTS/DSR/RI/CAR |
0×1c | Control | W | | 1 | DTR/RTS |
0×20 | Refresh | W | | 1 | Any value |
0×24 | Refresh | W | | 1 | Any value |
0×28 | Send and interrupt | W | 1 | Any value |
0×2c | Baud is set | W | 1 | Baud rate 300-〉230400 |
0×30 | Character is set | W | 1 | 7 or 8 characters |
0×34 | Setting stops | W | 1 | 1,1.5 or 2 |
0×38 | Odd even is set | W | 1 | Nothing, strange or even parity check |
0×3c | Flow control is set | W | 1 | Nothing, RTS/CTS or Xon/Xoff (continuing/stop) |
0×40 | Keep | - | 4 | Keep |
0×50 | Send data | W | T * FIFO size | Byte waiting for transmission |
Table 3
Serial unit register mappings 304 relates to lands register.One device of attempting to communicate with serial unit 300 is called as a starter in this article.For instance, starter can be computer 100 or other node of being connected on the network and communicating with interface 106 by a high-speed serial bus.Described starter is write 64 bit address of the plot of its serial register mapping and is describedly landed register so that log in the serial unit 300.If another starter lands, serial unit 300 is returned a conflict response message of makeing mistakes so.High 32 of described address are written to and land the address, and low 32 are written to and land+4 places.Described serial unit register mappings also relates to and withdraws from register.Starter is write this register so that withdraw from this serial unit with any value.After each bus reset, starter must be written to its (may change) node ID and reconnect register.If fail to do like this within one second at starter behind the bus reset, it will withdraw from automatically so.16 node ID are written to 16 of the bottoms of this register, 16 on top should be written as zero.Read T * FIFO sized registers and return the byte-sized of the transmission FIFO of serial unit.Read R * FIFO sized registers and return the byte-sized of the reception FIFO of serial unit 300.Read status register returns the state (if support) of current C TS/DSR/RI/CAR.Ground as shown in table 4 structural state register.
The hurdle | The position | Describe |
CTS | 0 | If CTS is the higher position is 1, otherwise be 0 |
DSR | 1 | If DSR is the higher position is 1, otherwise be 0 |
RI | 2 | If RI is the higher position is 1, otherwise be 0 |
CAR | 3 | If CAR is the higher position is 1, otherwise be 0 |
Keep | [31..4] | Always be 0 |
Table 4
The state that the writing of control register is provided with DTR and RTS (if support).The tissue of showing described control register in the table 5.
The hurdle | The position | Describe |
RTS | 0 | If be 1 just RTS to be made as height, otherwise RTS be made as low |
DTR |
| 1 | If be 1 just DTR to be made as height, otherwise DTR be made as low |
Keep | [31..2] | Always be 0 |
Table 5
With any value write refresh T * fifo register make serial unit 300 refresh its transmission FIFO, abandon current any byte wherein.Any value write refresh R * fifo register and make serial unit refresh it to receive FIFO, abandon current any byte wherein.Any value is write the transmission interrupt register makes serial unit 300 after the current content of transmission T * FIFO an interrupt status is set on its serial port.The baud rate that writing of baud rate register is provided with the serial port of serial unit 300 is set.As shown in table 6 organize the described baud rate register that is provided with.
The value of writing |
Baud rate |
0 |
300 |
1 |
600 |
2 |
1200 |
3 |
2400 |
4 |
4800 |
5 |
9600 |
6 |
19200 |
7 |
38400 |
8 |
57600 |
9 |
115200 |
10 |
230400 |
Table 6
The position size that the character boundary register is provided with send and the character that is received is set.Show the described tissue that the character boundary register is set in the table 7.Is 8 as highest significant position with 7 Character Filling by adding a filler.
The value of writing | The character bit size |
0 | 7 |
1 | 8 |
Table 7
Setting stops the number that sized registers indicates position of rest.Organize described setting to stop sized registers as shown in table 8ly.
The value of writing | Position of rest |
0 | 1 |
1 | 1.5 position |
2 | 2 |
Table 8
The parity check that the parity check register is provided with serial port is set.Show the described tissue that the parity check register is set in the table 9.
The value of writing | Parity check |
0 | The no parity position |
1 | Even parity check |
2 | Odd |
Table 9
The flow control register is set the employed flow control type of serial port is set.Show the described tissue that the flow register is set in the table 10.
The value of writing | Flow control | |
0 | Do not have |
1 | CTS/RTS |
2 | XOn/Xoff |
Table 10
Write and use this transmitting data register when asking transmitting data register that character is write transmission FIFO when starter sends piece.Piece writes and must be not more than by the specified transmission FIFO size of T * FIFO sized registers.Do not write if there are enough spaces to be used for whole among T * FIFO, return make mistakes response message and do not have character to be copied among this FIFO of a conflict so.
Comprise also in the series unit 300 that one has the starter register mappings of a plurality of registers, organize this mapping as shown in table 11ly.
The hexadecimal side-play amount | Title | Access | Size (quad) | Value |
0×0 | Interrupt | W | 1 | Any value |
0×4 | Framing is made mistakes | W | | 1 | The character that is received |
0×8 | Parity check makes mistakes | W | | 1 | The character that is received |
0×c | R * FIFO overflows | W | 1 | Any value |
0×10 | State variation | W | | 1 | CTS/DSR/RI/CAR |
0×14 | Keep | - | 3 | Keep |
0×20 | The data that received | W | R * FIFO size | The byte that is received |
Table 11
When serial unit 300 detected an interrupt status on its serial port, it was written to this register with an arbitrary value.When serial unit 300 detected a framing and makes mistakes on its serial port, it was written to the framing register with the character that is received.When serial unit 300 detected a parity check and makes mistakes on its serial port, it was written to the parity check register of makeing mistakes with the character that is received.When the reception FIFO of serial unit 300 overflowed, serial unit 300 was written to R * FIFO overflow register with an arbitrary value.When serial unit 300 detected the variation of arbitrary state of CTS/DSR/RI/CAR, its state that is written to the new serial port signal state of indication changed register.The tissue of showing described status register in the table 12.
The hurdle | The position | Describe |
CTS | 0 | If CTS is the higher position is 1, otherwise be 0 |
DSR | 1 | If DSR is the higher position is 1, otherwise be 0 |
RI | 2 | If RI is the higher position is 1, otherwise be 0 |
CAR | 3 | If CAR is the higher position is 1, otherwise be 0 |
Keep | [31..4] | Always be 0 |
Table 12
When serial unit 300 when its serial port receives character, it writes affairs with piece the character that is received is written to the received data register.It never writes the byte of Duoing than by the specified reception FIFO size of R * FIFO sized registers.If starter can not receive all characters that sent, it responds and does not receive the character that is sent with the conflict response message of makeing mistakes so.
Figure 11 illustrates the register memory mapping of interface device according to an embodiment of the invention.Figure 12 illustrates the tissue of the A/V global register that interface of the present invention contains.Figure 13 illustrates the tissue of the global state register that interface device of the present invention contains.Control register when Figure 14 illustrates waiting of containing in the interface device of the present invention.Figure 15 illustrates the tissue of the flow control register that contains in the interface device of the present invention.The tissue of channel register when Figure 16 illustrates waiting of containing in the interface device of the present invention.
In another embodiment of the present invention, draw a synthetic vertical blanking signal by the vertical blanking register on poll or the other fetch interface 106.This vertical blanking signal invocation code is to the program of operation on computer 100.In one embodiment, also the program to operation on computer 100 provides clocking information, itself and yard sign indicating number that combines or replace being called that is called.In one embodiment of the invention, interface 106 contains a register, and it has the counter of current process in the indication frame, thus deducibility or draw next vertical flyback in addition.By drawing the border of frame transmission, can locate with the access frame in and other data synchronous with the generation of a vertical blanking interval, such as for sampling operation.In addition, one embodiment of the present of invention draw and are used to locate consistent with vertical blanking interval but do not comprise frame boundaries about the data of the information of described vertical blanking.In one embodiment, the present invention is used for obtaining after a video blanking interval takes place active data in one period, such as the timing code that can read and can be used for being contained in the frame in the various processing application.In one embodiment, computer 100 scheduling one are interrupted therefore sending out a frame so that send in this deduction time then.