CN2221798Y - Numeric picture transmission and conversion arrangement - Google Patents

Abstract

The utility model relates to a numeric image transmission and conversion device, which is based on an SCSI and can output video signals of different systems. The utility model is composed of an SCSI controller and an image cache processor. The input terminal of the device is connected with the SCSI; the SCSI controller charges the completion of an SCSI protocol to guarantee that the image data is conveyed from a chief computer to the image cache processor through the SCSI; the image cache processor converts the image data to the needed system video signal. The utility model has the advantages that the interface adopts the SCSI, so the commonality is reinforced; a programmable device is adopted to enhance the density of integration; the volume is small; the installation and the maintenance are easy.

Description

A kind of Digital Image Transmission and conversion equipment

The utility model relates to a kind of Digital Image Transmission and conversion equipment, and the digital picture with calculator memory converts the device that video signal transmission is given peripheral hardware to specifically.

In the prior art, had view data conversion equipment based on VAX machine, PC bus and other bus, this conversion equipment becomes vision signal by controller and video memory with image transitions, but its versatility is relatively poor, and its interface, integrated level all can not meet the demands, the chip that is adopted in the converter is also out-of-date, and volume is bigger, is not suitable for the little occasion of volume requirement.

The purpose of this utility model provides a kind of based on scsi interface, the image transmission and the conversion equipment of exportable different systems vision signal.

Technical solution of the present utility model is achieved in that a kind of image transmission and conversion equipment of being made up of controller 1 (scsi controller) and image buffer storage processor 2 (Image BufferProcessor) IBP, the input end of this device is connected with the scsi interface of image documentation equipment computer system, the SCSI control circuit is responsible for finishing the SCSI agreement, the assurance view data is given image buffer storage processor IBP by the SCSI oral instructions from principal computer, view data is sent to video memory by graphic process unit, video dac converts view data to external unit receivable video standard signal.

Advantage of the present utility model is: the interface of this device adopts the SCSI mouth, can be connected in the computing machine of any configuration scsi interface, and versatility strengthens, number biography rate is accelerated, and adopts programming device, and integrated level improves, reliability improves, and volume is little, is easy to install and safeguard.

Below in conjunction with drawings and Examples the utility model is described in further detail.

Accompanying drawing 1 is the structured flowchart of this device

Accompanying drawing 2 is schematic diagrams of scsi controller.

Accompanying drawing 3 is schematic diagrams of image buffer storage processor.

Accompanying drawing 4 is theory diagrams of image buffer storage processor.

Accompanying drawing 5 is FPGA internal electrical schematic diagrams of image buffer storage processor.

In Fig. 1, image transmission and conversion equipment have been formed by scsi controller 1 and image buffer storage processor 2, on scsi controller 1, there is a SCSI socket 3 (25 * 2) to link to each other with the SCSI of principal computer, there is an IBP socket 4 (10 * 2) to dock with image buffer storage processor 2, the function of SCSI control unit circuit is to send the digital picture on the principal computer workstation to the IBP plate, after the storage conversion of viewdata signal by the IBP plate image transitions is become the receivable video standard signal of peripheral hardware, and be connected with peripheral hardware by a video socket 5 (75 Europe concentric cable).

In Fig. 2, by SCSI special chip NCR53C94 (1.1), the scsi controller 1 that high speed single chip microcomputer DS80C320 (1.2) and corresponding interface circuits are formed, total system is integrated on the PCB2 plate.Its principle is: as scsi device, must follow ANSI X3.131 agreement, it has formulated the stage of SCSI bus, stipulations such as condition and message system, all there be generation condition and sequential requirement separately in each stage, we select for use special-purpose SCSI IC to guarantee that their sequential is correct, carry out it and order the generation of controlling each stage, SCSI transmission order is carried out with the form of CDB (COMMAND DESCRIPTION BLOCK), after the SCSI control unit circuit has received CDB, promptly carry out translator command by command format, carried out then, behind the Data Transfer Done,, turn back to the bus idle phase at last again according to implementation status get the hang of stage and message phase.

Scsi controller 1 selected NCR53C94 (1.1) is the conventional special chip that is used for scsi interface as the scsi interface control chip, it can guarantee on the hardware with SCSI bus be connected and sequential on cooperation, SCSI special chip NCR53C94 (1.1) links to each other with workstation by SCSI 50pin cable in this circuit, DS80C320 (1.2) is as high speed single chip microcomputer CPU, pass through data bus, address bus, this three bus of control bus links to each other with SCSI special chip (1.1), CPU (1.2) is responsible for the initialization to scsi controller 1 and image buffer storage processor 2, self diagnosis, the realization of control SCSI agreement, translation CDB, and fill order, CPU (1.2) sends view data to image buffer storage processor 2 by three buses.Serial MC1488 (1.3), the effect of MC1489 (1.4) is that the self-test result of this controller is outputed on the external connection monitors by serial port, TTL realizes with serial MC1488 and MC1489 to the conversion of RS232 level, driver 74LS245 (1.5) is a reverse driven, it is responsible for driving LED and RESET signal, latch INTEL8282 (1.6) is the address latch of CPU, and the effect of program storage 2764 (1.7) is that the program with scsi controller leaves in here.

In image buffer storage processor 2 schematic diagrams shown in Figure 3, by graphic process unit TMS34010 (2.1), video memory TMS44C251 (2.2), the image buffer storage processor 2 that video dac ADV478 (2.3) and corresponding interface circuits are formed, wherein interface circuit is realized with a slice field programmable gate array, total system is integrated on the PCB1 plate, main frame is by the I/O register of scsi interface initialization graphic process unit (2.1), to set the image scanning mode, row synchronously, field sync period and pulsewidth, the data output timing of control VRAM (2.2) is to realize screen-refresh, local bus interface realizes the unified addressing of VRAM (2.2) and D/A (2.1), the output look-up table (LUT) of initialization D/A (2.3), main frame is sent to 672 * 512 * 8 pattern matrix data video memory VRAM (2.2) and carries out screen-refresh by graphic process unit GSP (2.1).The function of each module of system comprises: graphic process unit GSP (2.1) comprises complete programmable 32 general processors, has 128M byte address space, CRT control able to programme, directly with general DRAM and VRAM interface, there is automatic CRT to show refresh function, directly and the host interface of host communication, the CRT controller of GSP (2.1) produces row synchronously through programming, frame synchronization, blanking signal and screen refresh address, GSP (2.1) carries out initialization to the output look-up table LUT of D/A (2.3), host interface by GSP (2.1) and local interface are sent to local frame with the view data of main frame and deposit, and GSP (2.1) control of video storer VRAM (2.2) carries out screen-refresh.

The host interface of graphic process unit (2.1) provides 4 16 programmable register for the host data access, these registers both can be read and write by main frame, also can read and write by GSP (2.1), by this interface, main frame and GSP can transmit order between (2.1), status information and data, GSP (2.1) local memory interface is made up of one three tunnel multiplexing address data bus and control signal corresponding, support memory read/write, screen-refresh, VRAM (2.2) such as refreshes at memory cycle, in memory cycle, row address, column address, data are delivered on the same physical bus.

Video memory VRAM (2.2) aims at computer video to show and a kind of novel dual-ported memory of design that this circuit adopts TMS44C251, and it has two access ports: one is common DRAM access port, is used for GSP (2.1) it is read and write; Another is the serial access mouth, be used for the read-write of high-speed video data, as demonstration, image sampling etc., the serial port of VRAM (2.2) comprises the shift register that can deposit data line, available shift clock moves at a high speed or shifts out data and do not influence the access of parallel port, shift register and VRAM (2.2) the transmission cycle, its specific implementation: send out a common store access cycle by GSP (2.1) to the parallel access mouth, put VRAM (2.2) transmission periodic signal TR simultaneously and effectively get final product.

It is video dac that this circuit adopts ADV478 (2.3), its frequency of operation is up to 80MHZ, the conversion figure place is 8bit, output signal and RS-343A/RS-170 compatibility, pedestal level is able to programme, there is one 256 * 24 color look-up table (R.G.B) video dac (2.3) inside, and be with 3 road 8bit video d/a converters, before ADV478 (2.3) operate as normal, its inner color look-up table palpus initialization, to determine input--output relation, in this circuit, input--output relation is linear.Referring to accompanying drawing 4.

In image buffer storage processor 2, adopted new technology--programmable gate array FPGA, improved the integrated level and the design efficiency of system greatly, the design is removing 74LS244 (2.5), all discrete devices of 74LS245 (2.6) realize with a slice FPGA, as shown in Figure 5.This circuit FPGA inside has comprised following functional circuit: local bus interface's circuit of (1) GSP (2.1); (2) the screen-refresh control circuit of video memory VRAM (2.2).Local storage is made up of VRAM0 and VRAM1, and this local bus is to VRAM0, and VRAM1 and video d/a (2.3) carry out address assignment, and realizes VRAM0, VRAM1, and D/A (2.3) carries out read-write operation; The screen-refresh control circuit is realized following operation: in the read/write cycles, distinguish VRAM0, VRAM1 by RAS; Video shows refresh process, and GSP (2.1) is to VRAM0, and VRAM1 sends out one simultaneously and transmits periodic signal, will put into serial shift register (occurring in horizontal blackout period) separately with the video data of delegation; With the reset signal of blanking level as shift counter, to shift clock counting, when count value＜512, demonstration is shifted out in shift clock control VRAM0 pointwise, and when count value＞512, demonstration is shifted out in shift clock control VRAM1 pointwise.This circuit has been selected XC3042PC84 (2.4) chip for use, replaces traditional discrete device, has dwindled volume greatly.

Claims (5)

1. Digital Image Transmission and conversion equipment, it is made up of controller (1) and image buffer storage processor (2), it is characterized in that: the input end of this device links to each other with the scsi interface of image documentation equipment computer system by the SCSI socket (3) of controller (1), controller (1) is responsible for finishing the SCSI agreement, guarantee that view data sends image buffer storage processor (2) to by SCSI from principal computer, view data is sent to video memory by graphic process unit, video dac, convert view data to external unit receivable video standard signal, and be connected with peripheral hardware by a video socket (5).

2. Digital Image Transmission according to claim 1 and conversion equipment, it is characterized in that: controller (1) is by SCSI special chip NCR53C94 (1.1), high speed single chip microcomputer DS80C320 (1.2) and corresponding interface circuits are formed, SCSI special chip (1.1) is as the scsi interface control chip, guarantee with SCSI bus be connected and sequential on cooperation, DS80C320 (1.2) is as high speed single chip microcomputer CPU, be responsible for initialization to the NCR53C94 (1.1) and the image buffer storage processor (2) of controller (1), self diagnosis, the realization of control SCSI agreement, CPU (1.2) passes through address bus, data bus, control bus transmitted image data are given the image buffer storage processor, and the self-test result of this control circuit outputs on the external connection monitors by serial port.

3. a kind of Digital Image Transmission according to claim 1 and conversion equipment, it is characterized in that: image buffer storage processor (2) comprising: graphic process unit TMS34010 (2.1), video memory TMS44C251 (2.2), video dac ADV478 (2.3) and corresponding interface circuits, main frame is by the I/O register of scsi interface initialization graphic process unit TMS34010 (2.1), to set the image scanning mode, row synchronously, field sync period and pulsewidth, the data output timing of control VRAM (2.2), to realize screen-refresh, host interface by graphic process unit (2.1), main frame and graphic process unit can transmit order between (2.1), status information and data, the local memory interface of graphic process unit (2.1) is made up of one three tunnel multiplexing address/data bus and control signal corresponding, support memory read/write, memory cycles such as screen-refresh, in memory cycle, row address, column address, data are delivered on the same physical bus, the local interface of graphic process unit (2.1) links to each other with local bus interface, realize the unified addressing of video memory VRAM (2.2) and video dac D/A (2.3) by local bus interface, the output look-up table of initialization D/A (2.3), main frame transmits the pattern matrix data VRAM (2.2) and carries out screen-refresh by graphic process unit GSP (2.1).

4. Digital Image Transmission according to claim 3 and conversion equipment is characterized in that: corresponding interface circuits realizes with a slice on-site programmable gate array FPGA in the image buffer storage processor.

5. Digital Image Transmission according to claim 4 and conversion equipment is characterized in that: the selected chip of FPGA is XC3042PC84 (2.4).

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