CN113542840A - Method for adjusting display delay, electronic device and storage medium - Google Patents

Method for adjusting display delay, electronic device and storage medium Download PDF

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Publication number
CN113542840A
CN113542840A CN202110655605.4A CN202110655605A CN113542840A CN 113542840 A CN113542840 A CN 113542840A CN 202110655605 A CN202110655605 A CN 202110655605A CN 113542840 A CN113542840 A CN 113542840A
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time
video
frame
threshold
input end
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CN113542840B (en
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宫纪伟
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Zhejiang Dahua Technology Co Ltd
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Zhejiang Dahua Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
    • H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
    • H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display

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  • Signal Processing (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The application relates to a method for adjusting display delay, an electronic device and a storage medium, wherein the method for adjusting display delay comprises the following steps: acquiring an inter-frame time interval value, the display time of the next frame of a video display end, the display time of the current frame of the video display end and the arrival time of the current frame of a video input end; determining a first threshold value according to the inter-frame time interval value and the display time of the next frame of the video display end; if the arrival time of the current frame at the video input end meets the preset condition, the pixel clock of the video display end is adjusted until the absolute value of the difference value between the arrival time of the current frame at the video input end and the first threshold is smaller than the second threshold, wherein the adjustment of the pixel clock of the video display end can cause the display time of the next frame at the video display end to be updated.

Description

Method for adjusting display delay, electronic device and storage medium
Technical Field
The present application relates to the field of image processing, and more particularly, to a method, an electronic device, and a storage medium for adjusting display delay.
Background
With the continuous improvement of transmission bandwidth and hardware performance, the requirements of customers on the real-time performance and the stability of end-to-end display are higher and higher. The video acquisition end and the video display end in the distributed system adopt independent pixel clocks, even if the initial state is in the same phase, phase difference exists between the video acquisition end and the video display end after a period of time, and display delay time appears at the video output end.
In the existing scheme, a timing sequence parameter of a video display end is mainly acquired based on an FPGA, and a frame rate of the video display end is adjusted according to the timing sequence parameter of the video display end and the frame rate of the video acquisition end, so that the video display end displays each frame of video in real time.
Disclosure of Invention
The embodiment provides a method, an electronic device and a storage medium for adjusting display delay, so as to solve the problem that the delay time of a video display end cannot be adjusted in the related art.
In a first aspect, a method for adjusting display delay is provided in this embodiment, and includes:
acquiring an inter-frame time interval value, the display time of the next frame of a video display end, the display time of the current frame of the video display end and the arrival time of the current frame of a video input end, wherein the inter-frame time interval value is determined according to the time interval between frames in the previous n frames of the video input end, and n is more than or equal to 2;
determining a first threshold value according to the inter-frame time interval value and the display time of the next frame of the video display end;
if the arrival time of the current frame at the video input end meets a preset condition, adjusting a pixel clock of a video display end until the absolute value of the difference value between the arrival time of the current frame at the video input end and the first threshold is smaller than a second threshold, wherein the preset condition is determined based on the first threshold, the display time of the next frame at the video display end and the display time of the current frame at the video display end, and the adjustment of the pixel clock at the video display end can cause the display time of the next frame at the video display end to be updated.
In some embodiments, the time of arrival of the current frame at the video input end satisfying the preset condition includes:
the difference value obtained by subtracting the first threshold value from the arrival time of the current frame at the video input end is not less than the second threshold value, and the arrival time of the current frame at the video input end is not more than the display time of the next frame at the video display end; alternatively, the first and second electrodes may be,
the difference value obtained by subtracting the arrival time of the current frame at the video input end from the first threshold value is not less than the second threshold value, and the arrival time of the current frame at the video input end is not less than the display time of the current frame at the video display end.
In some of these embodiments, determining the first threshold based on the inter-frame time interval value and the display time of the next frame of the video display comprises:
and taking the difference value between the display time of the next frame of the video display end and the inter-frame time interval value as the first threshold value.
In some embodiments, adjusting the pixel clock of the video display end until the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is smaller than the second threshold specifically includes:
adjusting a pixel clock of the video display end to obtain the updated display time of the next frame of the video display end;
acquiring the arrival time of the next frame at the video input end;
determining an updated first threshold according to the inter-frame time interval value and the updated display time of the next frame of the video display terminal;
if the absolute value of the difference between the arrival time of the next frame at the video input end and the updated first threshold is not smaller than the second threshold, the step of adjusting the pixel clock of the video display end is executed again until the absolute value of the difference between the arrival time of the next frame at the video input end and the updated first threshold is smaller than the second threshold.
In some embodiments, the pixel clock of the video display terminal is adjusted until the absolute value of the difference between the arrival time of the current frame at the video input terminal and the first threshold is less than the second threshold, and the method further comprises:
determining an actual pixel clock of the video input;
taking an actual pixel clock of the video input end as a default pixel clock of the video display end;
setting a pixel clock of the video display end as the default pixel clock;
if the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is not less than a third threshold within a preset time period, adjusting the pixel clock of the video display end until the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is less than the third threshold, wherein the third threshold is less than the second threshold.
In some of these embodiments, determining the actual pixel clock of the video input comprises:
acquiring a theoretical pixel clock of the video input end, a frame rate of the video input end, theoretical time consumption of the video input end for receiving m frames and actual time consumption of the video input end for receiving m frames, wherein m is more than or equal to 2;
obtaining a first result value according to the product of the theoretical pixel clock of the video input end and the frame rate of the video input end;
obtaining a second result value according to the product of the first result value and the actual time consumption of receiving m frames by the video input end;
and obtaining the actual pixel clock of the video input end according to the ratio of the second result to the theoretical time consumption of the video input end for receiving m frames.
In some embodiments, the determining the inter-frame time interval value according to the time interval between frames in the first n frames of the video input end specifically includes:
the inter-frame time interval value is determined according to an average time interval and/or a maximum time interval, wherein the average time interval and the maximum time interval are calculated according to the time interval between frames in the previous n frames of the video input end.
In some of these embodiments, obtaining the display time of the next frame of the video display comprises:
acquiring a theoretical pixel clock of the video display end, an actual pixel clock of the video display end and a frame rate of the video display end, and calculating time required by the video display end to output each frame;
and determining the display time of the next frame of the video display end according to the display time of the current frame of the video display end and the time required by the video display end to output each frame.
In some embodiments, obtaining the display time of the current frame at the video display end comprises:
and acquiring the display time of the current frame of the video display end according to the VSYNC signal of the current frame of the video display end.
In a second aspect, in this embodiment, there is provided an electronic apparatus, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the processor implements the method for adjusting display delay according to the first aspect.
In a third aspect, in the present embodiment, a storage medium is provided, on which a computer program is stored, which when executed by a processor, implements the method for adjusting display delay of the first aspect described above.
Compared with the related art, in the method for adjusting display delay, the electronic device and the storage medium provided in this embodiment, under the condition that the arrival time of the current frame at the video input end satisfies the preset condition, the pixel clock at the video display end is adjusted until the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is smaller than the second threshold, and the first threshold is determined by the inter-frame time interval value and the display time of the next frame at the video display end.
The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a block diagram of a hardware structure of an application terminal according to an embodiment of the present application;
FIG. 2 is a flow chart of a method of adjusting display delay according to an embodiment of the present application;
FIG. 3 is a flow chart of yet another method for adjusting display delay according to an embodiment of the present application;
FIG. 4 is a flow chart for determining an actual pixel clock at a video input according to an embodiment of the present application;
FIG. 5 is a flow chart of yet another method of adjusting display delay according to an embodiment of the present application;
fig. 6 is a flowchart of another method for adjusting display delay according to an embodiment of the present application.
Detailed Description
For a clearer understanding of the objects, aspects and advantages of the present application, reference is made to the following description and accompanying drawings.
Unless defined otherwise, technical or scientific terms used herein shall have the same general meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The use of the terms "a" and "an" and "the" and similar referents in the context of this application do not denote a limitation of quantity, either in the singular or the plural. The terms "comprises," "comprising," "has," "having," and any variations thereof, as referred to in this application, are intended to cover non-exclusive inclusions; for example, a process, method, and system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to the listed steps or modules, but may include other steps or modules (elements) not listed or inherent to such process, method, article, or apparatus. Reference throughout this application to "connected," "coupled," and the like is not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Reference to "a plurality" in this application means two or more. "and/or" describes an association relationship of associated objects, meaning that three relationships may exist, for example, "A and/or B" may mean: a exists alone, A and B exist simultaneously, and B exists alone. In general, the character "/" indicates a relationship in which the objects associated before and after are an "or". The terms "first," "second," "third," and the like in this application are used for distinguishing between similar items and not necessarily for describing a particular sequential or chronological order.
The method embodiments provided in the present embodiment may be executed in a terminal, a computer, or a similar computing device. For example, the method is executed on a terminal, and fig. 1 is a block diagram of a hardware structure of an application terminal according to the method for adjusting display delay of the embodiment of the present application. As shown in fig. 1, the terminal may include one or more processors 102 (only one shown in fig. 1) and a memory 104 for storing data, wherein the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA. The terminal may also include a transmission device 106 for communication functions and an input-output device 108. It will be understood by those of ordinary skill in the art that the structure shown in fig. 1 is merely an illustration and is not intended to limit the structure of the terminal described above. For example, the terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store a computer program, for example, a software program and a module of an application software, such as a computer program corresponding to the method for adjusting display delay in the present embodiment, and the processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, so as to implement the method described above. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to the terminal over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used to receive or transmit data via a network. The network described above includes a wireless network provided by a communication provider of the terminal. In one example, the transmission device 106 includes a Network adapter (NIC) that can be connected to other Network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.
In the present embodiment, a method for adjusting a display delay is provided, and fig. 2 is a flowchart of a method for adjusting a display delay according to an embodiment of the present application, as shown in fig. 2, the flowchart includes the following steps:
step S201, obtaining an inter-frame time interval value, display time of a next frame of a video display end, display time of a current frame of the video display end and arrival time of the current frame of a video input end, wherein the inter-frame time interval value is determined according to time intervals among frames in previous n frames of the video input end, and n is larger than or equal to 2.
Step S202, a first threshold value is determined according to the inter-frame time interval value and the display time of the next frame of the video display terminal.
In this embodiment, the arrival time of the next frame at the video input end can be calculated according to the arrival time of the current frame at the video input end and the inter-frame time interval.
Step S203, if the arrival time of the current frame at the video input end meets a preset condition, adjusting a pixel clock at the video display end until an absolute value of a difference between the arrival time of the current frame at the video input end and the first threshold is smaller than a second threshold, where the preset condition is determined based on the first threshold, the display time of the next frame at the video display end, and the display time of the current frame at the video display end, and the adjustment of the pixel clock at the video display end may cause the display time of the next frame at the video display end to be updated.
In this embodiment, the second threshold may be adjusted according to actual conditions, and in a case where the delay time of the video display end is allowed to be longer, the second threshold may be set to be larger, and in a case where the delay time of the video display end is allowed to be smaller, the second threshold may be set to be smaller.
In a particular embodiment, the magnitude of the second threshold may be set to any value of [0.5, 2] milliseconds.
Through the steps, under the condition that the arrival time of the current frame at the video input end meets the preset condition, the pixel clock of the video display end is adjusted until the absolute value of the difference value between the arrival time of the current frame at the video input end and the first threshold is smaller than the second threshold, the first threshold is determined by the inter-frame time interval value and the display time of the next frame at the video display end, and the arrival time of the next frame at the video input end can be calculated according to the arrival time of the current frame at the video input end and the inter-frame time interval.
In some embodiments, the step S203, the step of satisfying the preset condition by the arrival time of the current frame at the video input end includes:
the difference value obtained by subtracting the first threshold value from the arrival time of the current frame at the video input end is not less than a second threshold value, and the arrival time of the current frame at the video input end is not more than the display time of the next frame at the video display end; alternatively, the first and second electrodes may be,
the difference value obtained by subtracting the arrival time of the current frame at the video input end from the first threshold value is not less than the second threshold value, and the arrival time of the current frame at the video input end is not less than the display time of the current frame at the video display end.
In the above manner, if the range of the arrival time of the current frame at the video input end is [ L1, L2], the pixel clock at the video display end is adjusted, L1 is the sum of the first threshold and the second threshold, L2 is the display time of the next frame at the video display end, or the range of the arrival time of the current frame at the video input end is [ K1, K2], the pixel clock at the video display end is adjusted, K1 is the display time of the current frame at the video display end, K2 is the difference between the first threshold and the second threshold, and the adjustment of the pixel clock at the video display end causes the display time of the next frame at the video display end to be updated, so that the absolute value of the difference between the arrival time of the current frame at the video input end and the display time of the next frame at the video display end can be controlled within a threshold range, the adjustment of the delay time at the video display end is realized, and in addition, the range of the arrival time of the current frame at the video input end is not [ L1 ], l2 and K1, K2, which indicate that the absolute value of the difference between the arrival time of the current frame at the video input end and the display time of the next frame at the video display end exceeds the inter-frame time interval value, it is not necessary to adjust the pixel clock at the video display end, and the current frame at the video input end is treated as an abnormal frame.
In some embodiments, the step S202, determining the first threshold according to the inter-frame time interval value and the display time of the next frame of the video display end includes:
and taking the difference value between the display time of the next frame of the video display end and the inter-frame time interval value as a first threshold value.
By the method, under the condition that the arrival time of the current frame at the video input end meets the preset condition, the pixel clock of the video display end is adjusted until the absolute value of the difference value between the arrival time of the next frame at the video input end and the display time of the next frame at the video display end is smaller than the sum of the inter-frame time interval and the second threshold, namely, the absolute value of the difference value between the arrival time of the current frame at the video input end and the display time of the next frame at the video display end can be adjusted within a threshold range, and the threshold is the sum of the inter-frame time interval and the second threshold, so that the problem that the delay time of the video display end cannot be adjusted is solved, and the delay time of the video display end is reduced.
In some embodiments, adjusting the pixel clock of the video display end until the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is smaller than the second threshold specifically includes:
adjusting a pixel clock of the video display end to obtain the display time of the next frame of the updated video display end;
acquiring the arrival time of the next frame at the video input end;
determining an updated first threshold according to the inter-frame time interval value and the updated display time of the next frame of the video display end;
and if the absolute value of the difference value between the arrival time of the next frame at the video input end and the updated first threshold is not less than the second threshold, executing the step of adjusting the pixel clock of the video display end again until the absolute value of the difference value between the arrival time of the next frame at the video input end and the updated first threshold is less than the second threshold.
By the above mode, under the condition that the absolute value of the difference between the arrival time of the next frame of the video input end and the updated first threshold is not smaller than the second threshold, the pixel clock of the video display end is adjusted, the display time of the next frame of the video display end is updated, the absolute value of the difference between the arrival time of the next frame of the video input end and the updated display time of the next frame of the video display end can be controlled within a range, and the adjustment of the delay time of the video display end is realized.
In some embodiments, fig. 3 is a flowchart of another method for adjusting a display delay according to an embodiment of the present application, and as shown in fig. 3, the method further includes the following steps after adjusting a pixel clock of the video display terminal until an absolute value of a difference between an arrival time of a current frame at the video input terminal and the first threshold is smaller than a second threshold:
in step S301, the actual pixel clock at the video input is determined.
Step S302, the actual pixel clock at the video input end is used as the default pixel clock at the video display end.
Step S303, a pixel clock of the video display terminal is set as a default pixel clock.
Step S304, if the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is not less than the third threshold within the preset time period, adjusting the pixel clock of the video display end until the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is less than the third threshold, where the third threshold is less than the second threshold.
In this embodiment, if the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is smaller than the third threshold within the preset time period, the pixel clock at the video display end does not need to be adjusted, which indicates that the current default pixel clock at the video display end is the optimal pixel clock at the video display end.
After the pixel clock of the video display end is set as the default pixel clock, whether the absolute value of the difference value between the arrival time of the current frame of the video input end and the first threshold value in a preset time period is smaller than a third threshold value is judged, if yes, the current default pixel clock of the video display end is the optimal default pixel, if not, the current default pixel clock of the video display end is not the optimal default pixel, and at the moment, the pixel clock of the video display end needs to be adjusted until the pixel clock of the video display end is the optimal default pixel clock.
Through the steps, the optimal pixel clock of the video display end is determined, so that the absolute value of the difference value between the arrival time of the current frame of the video input end and the first threshold value is smaller than the third threshold value in a longer time period, and the pixel clock of the video display end is prevented from being frequently adjusted.
In some embodiments, fig. 4 is a flowchart of determining an actual pixel clock of a video input according to an embodiment of the present application, and as shown in fig. 4, determining the actual pixel clock of the video input includes the following steps:
step S401, obtaining a theoretical pixel clock of a video input end, a frame rate of the video input end, theoretical time consumption of the video input end for receiving m frames, and actual time consumption of the video input end for receiving m frames, wherein m is larger than or equal to 2.
Step S402, a first result value is obtained according to a product of a theoretical pixel clock at the video input end and a frame rate at the video input end.
In step S403, a second result value is obtained according to the product of the first result value and the actual consumed time for receiving m frames at the video input end.
And step S404, obtaining the actual pixel clock of the video input end according to the ratio of the second result to the theoretical consumed time of the video input end for receiving m frames.
Through the steps, under the condition that the time sequence parameters of the video display end cannot be obtained in the universal SOC chip, the actual pixel clock of the video input end is calculated by considering the theoretical time consumption of the video input end for receiving m frames, the actual time consumption of the video input end for receiving m frames and the theoretical pixel clock of the video input end, and the actual pixel clock of the video input end can be determined more accurately.
In some embodiments, the determining the inter-frame time interval value according to the time interval between frames in the first n frames of the video input end specifically includes:
the inter-frame time interval value is determined according to an average time interval and/or a maximum time interval, wherein the average time interval and the maximum time interval are calculated according to the time interval between frames in the previous n frames of the video input end.
In this embodiment, the inter-frame time interval is determined according to the average time interval and/or the maximum time interval of the first n frames of the video input end, and the arrival time of the next frame of the video input end can be calculated according to the arrival time of the current frame of the video input end and the average time interval of the first n frames of the video input end, or the arrival time of the next frame of the video input end can be calculated according to the arrival time of the current frame of the video input end and the maximum time interval of the first n frames of the video input end.
Determining a first threshold value according to an inter-frame time interval value and the display time of the next frame of the video display end, and if the absolute value of the difference value between the arrival time of the current frame of the video input end and the first threshold value is smaller than a second threshold value, indicating that the absolute value of the difference value between the arrival time of the next frame of the video input end and the arrival time of the next frame of the video display end is smaller than a preset threshold value, so that the interval between the arrival time of the next frame of the video display end and the arrival time of the next frame of the video input end can be determined according to the absolute value of the difference value between the arrival time of the current frame of the video input end and the first threshold value, the delay time of the video display end relative to the video input end can be determined according to the interval, and whether the pixel clock of the video display end needs to be adjusted or not is determined according to the delay time.
By the method, the time interval value between the arrival time of the current frame at the video input end and the arrival time of the next frame at the video input end can be determined, the arrival time of the next frame at the video input end can be calculated according to the time interval value and the arrival time of the current frame at the video input end, the absolute value of the difference value between the arrival time of the next frame at the video output end and the display time of the next frame at the video display end can be calculated, whether the delay time of the video display end is in an appropriate range can be judged according to the absolute value, and the adjustment of the delay of the video display end is realized.
In some of these embodiments, obtaining the display time of the next frame on the video display comprises:
acquiring a theoretical pixel clock of a video display end, an actual pixel clock of the video display end and a frame rate of the video display end, and calculating time required by the video display end to output each frame;
and determining the display time of the next frame of the video display end according to the display time of the current frame of the video display end and the time required by the video display end to output each frame.
Through the mode, the time required by the video display end to output each frame can be accurately calculated according to the theoretical pixel clock of the video display end, the actual pixel clock of the video display end and the frame rate of the video display end, and on the basis, the display time of the next frame of the video display end can be more accurately determined according to the display time of the current frame of the video display end and the time required by the video display end to output each frame.
In some embodiments, obtaining the display time of the current frame at the video display end comprises:
and acquiring the display time of the current frame of the video display end according to the VSYNC signal of the current frame of the video display end.
Note that, the VSYNC signal: the refreshing process of the screen is from left to right, from top to bottom, for each row. When the entire screen is refreshed, i.e., one vertical refresh cycle is completed, there is a brief blanking period, and the VSYNC signal is sent out at this time.
Through the mode, under the condition that the time sequence parameters of the video display end cannot be acquired in the universal SOC chip, the display time of the current frame of the video display end can be accurately determined according to the VSYNC signal of the current frame of the video display end.
Fig. 5 is a flowchart of another method for adjusting display delay according to an embodiment of the present application, and as shown in fig. 5, the flowchart includes the following steps:
in step S501, an inter-frame time interval value is determined according to the average time interval and/or the maximum time interval.
In this embodiment, the average time interval and the maximum time interval are calculated based on the time interval between frames in the first n frames of the video input terminal
Step S502, according to the VSYNC signal of the current frame of the video display end, the display time of the current frame of the video display end is obtained.
Step S503, acquiring a theoretical pixel clock of the video display end, an actual pixel clock of the video display end and a frame rate of the video display end, calculating time required by the video display end to output each frame, and determining display time of a next frame of the video display end according to display time of a current frame of the video display end and the time required by the video display end to output each frame.
Step S504, the arrival time of the current frame at the video input end is obtained.
In step S505, the difference between the display time of the next frame of the video display end and the inter-frame time interval value is used as a first threshold.
In step S506, if the arrival time of the current frame at the video input end meets the preset condition, the pixel clock at the video display end is adjusted until the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is smaller than the second threshold.
In this embodiment, the preset condition is determined based on the first threshold, the display time of the next frame of the video display end, and the display time of the current frame of the video display end, and the pixel clock of the video display end is adjusted to cause the display time of the next frame of the video display end to be updated.
In one embodiment, the step of the video input terminal that the arrival time of the current frame satisfies the preset condition includes:
the difference value obtained by subtracting the first threshold value from the arrival time of the current frame at the video input end is not less than a second threshold value, and the arrival time of the current frame at the video input end is not more than the display time of the next frame at the video display end; or the difference value obtained by subtracting the arrival time of the current frame at the video input end from the first threshold value is not less than the second threshold value, and the arrival time of the current frame at the video input end is not less than the display time of the current frame at the video display end.
In one embodiment, adjusting the pixel clock of the video display end until the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is smaller than a second threshold specifically includes:
adjusting a pixel clock of the video display end to obtain the display time of the next frame of the updated video display end;
acquiring the arrival time of the next frame at the video input end;
determining an updated first threshold according to the inter-frame time interval value and the updated display time of the next frame of the video display end;
and if the absolute value of the difference value between the arrival time of the next frame at the video input end and the updated first threshold is not less than the second threshold, executing the step of adjusting the pixel clock of the video display end again until the absolute value of the difference value between the arrival time of the next frame at the video input end and the updated first threshold is less than the second threshold.
Step S507, obtaining a theoretical pixel clock of the video input end, a frame rate of the video input end, theoretical time consumption of the video input end for receiving m frames and actual time consumption of the video input end for receiving m frames, wherein m is larger than or equal to 2.
Step S508, obtaining a first result value according to a product of a theoretical pixel clock at the video input end and the frame rate at the video input end, obtaining a second result value according to a product of the first result value and an actual consumed time for receiving m frames at the video input end, and obtaining an actual pixel clock at the video input end according to a ratio of the second result to the theoretical consumed time for receiving m frames at the video input end.
In step S509, the actual pixel clock at the video input end is used as the default pixel clock at the video display end, and the pixel clock at the video display end is set as the default pixel clock.
Step S510, if the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is not less than the third threshold within the preset time period, adjusting the pixel clock of the video display end until the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is less than the third threshold, where the third threshold is less than the second threshold.
Through the steps, under the condition that the arrival time of the current frame at the video input end meets the preset condition, the pixel clock of the video display end is adjusted until the absolute value of the difference value between the arrival time of the current frame at the video input end and the first threshold is smaller than the second threshold, the first threshold is determined by the inter-frame time interval value and the display time of the next frame at the video display end, and the arrival time of the next frame at the video input end can be calculated according to the arrival time of the current frame at the video input end and the inter-frame time interval.
It should be noted that the steps illustrated in the above-described flow diagrams or in the flow diagrams of the figures may be performed in a computer system, such as a set of computer-executable instructions, and that, although a logical order is illustrated in the flow diagrams, in some cases, the steps illustrated or described may be performed in an order different than here. For example, step S501 and step S502 may be interchanged.
Fig. 6 is a flowchart of another method for adjusting display delay according to an embodiment of the present application, and as shown in fig. 6, the method for adjusting display delay includes the following steps:
step S601, system initialization is completed, two frame buffer devices are allocated for display switching, a high-precision timer is started, data link creation is completed according to a task issued by an upper layer, a video input end sends a code stream, and after data preprocessing is completed, the data is updated to a standby video memory.
It should be noted that, the double buffer framebuffer: double buffered framebuffer is a drawing technique that allows drawing without the undesirable effects of flickering, tearing, etc., and reduces latency. The double buffer framebuffer is mapped into the video memory, and the display switching is completed by updating the address.
In one embodiment, the completing the creation of the data link according to the task issued by the upper layer includes: when the single-screen network pulls a stream, decoding resources, CSC resources, zooming resources and the like need to be created, if two frame buffer devices are provided, namely, a frame buffer device No. 0 and a frame buffer device No. 1, and the frame buffer device No. 0 is just used as a video memory to be output, data is stored in the frame buffer device No. 1.
Step S602, acquiring the display time of the current frame of the video display end according to the VSYNC signal trigger time of the current frame of the video display end, and acquiring the display time of the next frame of the video display end according to the VSYNC signal trigger time of the next frame of the video display end.
Step S603, obtaining the arrival time of the current frame at the video input end according to the time when the current frame at the video input end is written into the frame buffer device.
Step S604, counting the maximum time interval value in the previous n frames of the video input end.
In step S605, the maximum time interval value is subtracted from the display time of the next frame of the video display terminal to obtain a first threshold.
Step S606, setting a second threshold value, and judging whether the arrival time of the current frame at the video input end is in the range of [ L1, L2] and [ K1, K2], wherein L1 is the sum of the first threshold value and the second threshold value, L2 is the display time of the next frame at the video display end, K1 is the display time of the current frame at the video display end, and K2 is the difference between the first threshold value and the second threshold value.
In this embodiment, after each VSYNC interruption report, it is determined whether the arrival time of the current frame at the video input end is within the range of [ L1, L2] and [ K1, K2], and the second threshold is set according to the actual situation, preferably, the second threshold may be set to 1 millisecond, if the arrival time of the current frame at the video input end is within the range of [ L1, L2] and [ K1, K2], the step S607 is performed, and if the arrival time of the current frame at the video input end is not within the range of [ L1, L2] and [ K1, K2], the step S608 is performed.
Step S607, the pixel clock of the video display end is adjusted until the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is smaller than the second threshold.
In this embodiment, if the arrival time of the current frame at the video input end is in the range of [ L1, L2], the pixel clock at the video display end is slowed down, and if the arrival time of the current frame at the video input end is in the range of [ K1, K2], the pixel clock at the video display end is quickened.
According to the magnitude of the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold, the arrival time of the current frame at the video input end is recorded as T2, the first threshold is recorded as phase _ diff, the arrival time of the current frame at the video display end is recorded as the arrival time of the next frame at the video display end, the maximum time interval value in the previous n frames at the video input end is recorded as max _ diff, and assuming that the second threshold is 1ms, an appropriate adjustment value is selected, the pixel clock at the video display end is accelerated/decelerated, and finally an adjusted target | T2-phase _ diff | is less than 1ms (phase _ diff is T1-max _ diff, and the maximum value of the frame receiving interval max _ diff).
If phase _ diff +1< ═ T2< ═ T1, the pixel clock at the video display end needs to be reduced, if T0< ═ T2< ═ phase _ diff-1, the pixel clock at the video display end needs to be increased, the size of the pixel clock at the video display end is determined according to the size of | T2-phase _ diff | and the change trend of | T2-phase _ diff | is observed for a plurality of times, if the change trend is consistent with the expected trend, the pixel clock at the video display end is not modified temporarily, and the pixel clock at the video display end does not need to be adjusted up/down until | T2-phase _ diff | is less than 1 ms.
In one embodiment, the maximum adjustable value of the pixel clock (e.g. 500KHZ) and the step of each adjustment (e.g. 5KHZ) at the video display end are set, in the case of 1080P @60 code stream, the theoretical pixel clock at the video input end is 148.5MHZ, if the pixel clock at the video display end is increased by 500KHZ to 149MHZ, 0.2 frame (149000 x 60/148500) can be transmitted more per second, the theoretical frame of the video display end takes 1000s/60 frames to 16.67ms, the actual frame takes 1000s/60.2 frames to 16.61ms, the adjustment in 1s is close to 0.6ms, and the average frame of the video display end is adjusted by 0.01ms (0.6/60).
In step S608, the current frame at the video input end is discarded.
In this embodiment, the current frame at the video input end is discarded and the process goes to step S602.
Step S609, a theoretical pixel clock of the video input end, a frame rate of the video input end, theoretical time consumption of the video input end for receiving m frames and actual time consumption of the video input end for receiving m frames are obtained, wherein m is larger than or equal to 2.
Step S610, obtaining a first result value according to a product of a theoretical pixel clock at the video input end and the frame rate at the video input end, obtaining a second result value according to a product of the first result value and an actual consumed time of receiving m frames at the video input end, and obtaining an actual pixel clock at the video input end according to a ratio of the second result to the theoretical consumed time of receiving m frames at the video input end.
In one embodiment, assuming that the theoretical pixel clock at the video input is PLL (the theoretical pixel clock is 148.5MHZ), the frame rate is FPS, the time T1 is counted for each fixed frame received at the video input, and the theoretical time T2, for example, 1080P60, takes 1s for each 60 frames received at the video input, the actual pixel clock is PLL × T1 × FPS/T2.
In step S611, the actual pixel clock at the video input end is used as the default pixel clock at the video display end.
Step S612, determining whether the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is less than a third threshold within a preset time period.
In this embodiment, the third threshold is smaller than the second threshold, the preset time period may be set to [3, 8] minutes, but the preset time is not limited to this time period, and the preset time period may be adjusted according to the actual situation, if the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is smaller than the third threshold, the adjustment of the pixel clock at the video display end is completed, and if the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is not smaller than the third threshold, step S609 is entered, the theoretical consumed time and the actual consumed time of more frames at the video input end are counted, and the actual pixel clock at the video input end is recalculated until the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is smaller than the third threshold.
In step S613, the default pixel clock of the current video display terminal is used as the optimal pixel clock.
Through the above steps, in the case where the arrival time of the current frame at the video input terminal is within the range of [ L1, L2] and [ K1, K2], the pixel clock at the video display terminal is adjusted until the absolute value of the difference between the arrival time of the current frame at the video input terminal and the first threshold value, which is determined by the inter-frame time interval value and the display time of the next frame at the video display terminal, is smaller than the second threshold value, and the arrival time of the next frame at the video input terminal can be calculated from the arrival time of the current frame at the video input terminal and the inter-frame time interval, so that the absolute value of the difference between the arrival time of the next frame at the video input terminal and the display time of the next frame at the video display terminal can be controlled within a threshold range, the problem that the delay time of the video display terminal cannot be adjusted in a general SOC chip is solved, the delay time of the video display terminal is reduced, and, in addition, the absolute value of the difference between the arrival time of the next frame at the video input terminal and the display time of the next frame at the video display terminal is controlled within a threshold range of the display time of the next frame at the video display terminal After the absolute value is controlled within a threshold range, the optimal pixel clock of the video display end is determined, so that the absolute value of the difference value between the arrival time of the current frame at the video input end and the first threshold is smaller than a third threshold in a longer time period, and the pixel clock of the video display end is prevented from being frequently adjusted.
It should be noted that the steps illustrated in the above-described flow diagrams or in the flow diagrams of the figures may be performed in a computer system, such as a set of computer-executable instructions, and that, although a logical order is illustrated in the flow diagrams, in some cases, the steps illustrated or described may be performed in an order different than here. For example, step S602 and step S603 may be interchanged.
There is also provided in this embodiment an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.
Optionally, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.
Optionally, in this embodiment, the processor may be configured to execute the following steps by a computer program:
the method comprises the steps of obtaining an inter-frame time interval value, the display time of the next frame of a video display end, the display time of the current frame of the video display end and the arrival time of the current frame of a video input end, wherein the inter-frame time interval value is determined according to the time interval between frames in the previous n frames of the video input end, and n is larger than or equal to 2.
And determining a first threshold value according to the inter-frame time interval value and the display time of the next frame of the video display terminal.
If the arrival time of the current frame at the video input end meets a preset condition, adjusting a pixel clock of the video display end until the absolute value of the difference value between the arrival time of the current frame at the video input end and the first threshold is smaller than a second threshold, wherein the preset condition is determined based on the first threshold, the display time of the next frame at the video display end and the display time of the current frame at the video display end, and the adjustment of the pixel clock at the video display end can cause the display time of the next frame at the video display end to be updated.
It should be noted that, for specific examples in this embodiment, reference may be made to the examples described in the foregoing embodiments and optional implementations, and details are not described again in this embodiment.
In addition, in combination with the method for adjusting display delay provided in the foregoing embodiment, a storage medium may also be provided in this embodiment. The storage medium having stored thereon a computer program; the computer program, when executed by a processor, implements any of the above-described embodiments of a method of adjusting display delay.
It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to be limiting. All other embodiments, which can be derived by a person skilled in the art from the examples provided herein without any inventive step, shall fall within the scope of protection of the present application.
It is obvious that the drawings are only examples or embodiments of the present application, and it is obvious to those skilled in the art that the present application can be applied to other similar cases according to the drawings without creative efforts. Moreover, it should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another.
The term "embodiment" is used herein to mean that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly or implicitly understood by one of ordinary skill in the art that the embodiments described in this application may be combined with other embodiments without conflict.
The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the patent protection. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims (11)

1. A method of adjusting display delay, comprising:
acquiring an inter-frame time interval value, the display time of the next frame of a video display end, the display time of the current frame of the video display end and the arrival time of the current frame of a video input end, wherein the inter-frame time interval value is determined according to the time interval between frames in the previous n frames of the video input end, and n is more than or equal to 2;
determining a first threshold value according to the inter-frame time interval value and the display time of the next frame of the video display end;
if the arrival time of the current frame at the video input end meets a preset condition, adjusting a pixel clock of a video display end until the absolute value of the difference value between the arrival time of the current frame at the video input end and the first threshold is smaller than a second threshold, wherein the preset condition is determined based on the first threshold, the display time of the next frame at the video display end and the display time of the current frame at the video display end, and the adjustment of the pixel clock at the video display end can cause the display time of the next frame at the video display end to be updated.
2. The method of claim 1, wherein the step of adjusting the display delay when the arrival time of the current frame at the video input end satisfies the predetermined condition comprises:
the difference value obtained by subtracting the first threshold value from the arrival time of the current frame at the video input end is not less than the second threshold value, and the arrival time of the current frame at the video input end is not more than the display time of the next frame at the video display end; alternatively, the first and second electrodes may be,
the difference value obtained by subtracting the arrival time of the current frame at the video input end from the first threshold value is not less than the second threshold value, and the arrival time of the current frame at the video input end is not less than the display time of the current frame at the video display end.
3. The method of claim 1, wherein determining the first threshold value according to the inter-frame time interval value and the display time of the next frame of the video display comprises:
and taking the difference value between the display time of the next frame of the video display end and the inter-frame time interval value as the first threshold value.
4. The method according to claim 1, wherein adjusting the pixel clock of the video display end until an absolute value of a difference between an arrival time of a current frame at the video input end and the first threshold is smaller than the second threshold comprises:
adjusting a pixel clock of the video display end to obtain the updated display time of the next frame of the video display end;
acquiring the arrival time of the next frame at the video input end;
determining an updated first threshold according to the inter-frame time interval value and the updated display time of the next frame of the video display terminal;
if the absolute value of the difference between the arrival time of the next frame at the video input end and the updated first threshold is not smaller than the second threshold, the step of adjusting the pixel clock of the video display end is executed again until the absolute value of the difference between the arrival time of the next frame at the video input end and the updated first threshold is smaller than the second threshold.
5. The method according to claim 1, wherein the pixel clock of the video display terminal is adjusted until the absolute value of the difference between the arrival time of the current frame at the video input terminal and the first threshold is less than the second threshold, and the method further comprises:
determining an actual pixel clock of the video input;
taking an actual pixel clock of the video input end as a default pixel clock of the video display end;
setting a pixel clock of the video display end as the default pixel clock;
if the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is not less than a third threshold within a preset time period, adjusting the pixel clock of the video display end until the absolute value of the difference between the arrival time of the current frame at the video input end and the first threshold is less than the third threshold, wherein the third threshold is less than the second threshold.
6. The method of adjusting display delay of claim 5, wherein determining an actual pixel clock of the video input comprises:
acquiring a theoretical pixel clock of the video input end, a frame rate of the video input end, theoretical time consumption of the video input end for receiving m frames and actual time consumption of the video input end for receiving m frames, wherein m is more than or equal to 2;
obtaining a first result value according to the product of the theoretical pixel clock of the video input end and the frame rate of the video input end;
obtaining a second result value according to the product of the first result value and the actual time consumption of receiving m frames by the video input end;
and obtaining the actual pixel clock of the video input end according to the ratio of the second result to the theoretical time consumption of the video input end for receiving m frames.
7. The method according to claim 1, wherein the inter-frame time interval value is determined according to a time interval between frames in the first n frames of the video input end, and specifically comprises:
the inter-frame time interval value is determined according to an average time interval and/or a maximum time interval, wherein the average time interval and the maximum time interval are calculated according to the time interval between frames in the previous n frames of the video input end.
8. The method of claim 1, wherein obtaining the display time of the next frame of the video display comprises:
acquiring a theoretical pixel clock of the video display end, an actual pixel clock of the video display end and a frame rate of the video display end, and calculating time required by the video display end to output each frame;
and determining the display time of the next frame of the video display end according to the display time of the current frame of the video display end and the time required by the video display end to output each frame.
9. The method of claim 1, wherein obtaining the display time of the current frame at the video display end comprises:
and acquiring the display time of the current frame of the video display end according to the VSYNC signal of the current frame of the video display end.
10. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and the processor is configured to execute the computer program to perform the method of adjusting display delay of any of claims 1 to 9.
11. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of adjusting display delay of any one of claims 1 to 9.
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