CN111082870B - Clock recovery and adaptive equalizer combined device and method in coherent optical communication - Google Patents
Clock recovery and adaptive equalizer combined device and method in coherent optical communication Download PDFInfo
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- CN111082870B CN111082870B CN201911399626.3A CN201911399626A CN111082870B CN 111082870 B CN111082870 B CN 111082870B CN 201911399626 A CN201911399626 A CN 201911399626A CN 111082870 B CN111082870 B CN 111082870B
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- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/40—Transceivers
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Abstract
The invention discloses a clock recovery and self-adaptive equalizer combined device and a method in coherent optical communication, relating to the technical field of coherent optical communication. Specifically, a two-stage real number equalization structure and a second-stage adaptive coefficient are adopted to calculate a timing error so as to realize clock recovery, polarization demultiplexing and dispersion compensation. According to the structure, a separate clock recovery module is omitted, the calculation complexity is reduced compared with the traditional structure, the clock recovery accuracy is improved, and the tolerance of IQ data imbalance of a receiving end is improved. Because the two-stage equalization of the structure adopts real number equalization, IQ two paths of data are not combined together in the equalization process, and the problem that the performance of the system is greatly influenced under the condition that IQ has time delay can be effectively solved.
Description
Technical Field
The invention relates to the technical field of coherent optical communication, in particular to a clock recovery and adaptive equalizer combination device and method in coherent optical communication.
Background
The coherent optical communication technology is widely applied in 40G and 100G optical communication times due to the characteristics of high sensitivity, good frequency selectivity and high spectrum efficiency. In a coherent transmission system, DSP (Digital Signal Processing) technology plays a key role. After the receiving end coherently receives and demodulates the signal light, an ADC (Analog-Digital Converter) is used for sampling the demodulated electronic signal, and then the sampled Digital signal is used for compensating and recovering the damage generated in the signal transmission process through a DSP algorithm.
The DSP algorithm comprises: clock recovery, adaptive equalization, carrier recovery (frequency difference estimation and compensation), carrier recovery (phase difference estimation and compensation), symbol decision. Clock recovery and adaptive equalizers are important components. The clock recovery algorithm mainly plays a role in recovering a clock of signal data obtained by ADC sampling, and the traditional algorithms mainly comprise a Gardner algorithm, an M & M algorithm, a digital filtering square timing clock recovery algorithm and the like. The channel equalization plays roles of polarization demultiplexing and dispersion compensation, and generally comprises a linear equalizer and an adaptive equalization coefficient updating part. Common algorithms include a constant modulus algorithm, a least mean square algorithm and the like. The complexity of the equalizer is closely related to the order selection of its coefficients.
In practical applications, the complexity of the DSP algorithm implementation and the resource occupation are important considerations. In a conventional dual-polarization QPSK (Quadrature Phase Shift keying) system, a 2 × 2 multiple input multiple output complex equalization structure is most commonly used, two polarization complex signals are input, two polarization complex signals are output, and N-order coefficients of the two polarization complex signals are both complex, so that the computation amount is large and the resource consumption is large. A conventional clock recovery and adaptive equalization architecture is shown in fig. 1. Data Ein after ADC samplingxAnd (4) entering an interpolation filter, detecting the timing error of output data of the interpolation filter through a Gardner algorithm, and adjusting the coefficient of the interpolation filter through filtering and a numerical control oscillator so as to achieve the purpose of clock synchronization. Synchronized data EintxEntering a 2 x 2 butterfly complex equalization module. The coefficients are Hxx, Hxy, Hyx and Hyy, the coefficients are of the N-order, and 16N multipliers are required by the equalization structure. And because two IQ paths (the IQ paths are that data is divided into two paths which are respectively modulated by carriers, the two paths of carriers are mutually orthogonal, I is in-phase, and q is quadrature). When the data are combined together, the complex equalizer has low tolerance to IQ input imbalance, and the system performance is greatly affected under the condition of IQ input imbalance.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a clock recovery and adaptive equalizer combination device and method in coherent optical communication, which reduce resource consumption, accurately realize clock recovery and simultaneously complete data equalization.
In order to achieve the above purposes, the technical scheme adopted by the invention is as follows: the utility model provides a clock recovery and adaptive equalizer combination unit among coherent light communication, includes two interpolation filters, two sets of first order multichannel real number equalizer, two second order single channel linear real number equalizer, two timing error detector, two filters and two numerical control oscillator, wherein:
two interpolation filters are used: respectively receiving the sampled data of two polarizations, and outputting the data to two groups of first-stage multi-channel real number equalizers;
two sets of first-stage multi-channel real equalizers are used for: receiving data sent by the interpolation filter, carrying out depolarization multiplexing, and respectively outputting the data to a second-stage single-channel linear real number equalizer connected with the data;
two second-stage single-channel linear real equalizers are used: receiving data processed by a first-stage multi-channel real number equalizer, and performing equalization processing, wherein two filter coefficients are output to a connected timing error detector;
two timing error detectors are used: two equalization coefficients which are continuously adjusted in the second-stage single-channel linear real number equalizer are extracted, timing error detection is carried out, and the two equalization coefficients are output to a filter;
two filters are used: filtering the result of timing error detection, and sending the result to a numerically controlled oscillator;
two numerically controlled oscillators are used for: and receiving error data processed by the filter, outputting interpolation parameters to the interpolation filter, and adjusting the coefficient of the interpolation filter.
On the basis of the scheme, the first-stage multichannel real number equalizer is a 4 x 4 real number equalizer, and 16 independent equalization coefficients with the order of 1 are adopted.
On the basis of the scheme, the Nth-order coefficients of the second-stage single-channel linear real number equalizer are h (- (N-1)/2, k), … … h (-1, k), h (0, k), and h (1, k) … … h ((N-1)/2, k).
On the basis of the scheme, two equalization coefficients of the extracted second-stage single-channel linear real number equalizer are h (-1, k) and h (1, k).
On the basis of the scheme, the calculation formula of the error detection is as follows:
ekt＝h(-1，k)-h(1，k)。
the invention also provides a clock recovery and self-adaptive equalization method in coherent optical communication, which comprises the following steps:
respectively receiving the sampled data of two polarizations by two interpolation filters, and outputting the data to two groups of first-stage multi-channel real number equalizers;
each group of first-stage multi-channel real number equalizer performs depolarization multiplexing on the data sent by the interpolation filter, and outputs the data to a connected second-stage single-channel linear real number equalizer;
the two second-stage single-channel linear real number equalizers respectively receive the data processed by the first-stage multi-channel real number equalizer and perform equalization processing, wherein two filter coefficients are output to a connected timing error detector;
the two timing error detectors respectively extract two equalization coefficients which are continuously adjusted in the second-stage single-channel linear real number equalizer, perform timing error detection and output the timing error detection to the filter;
the two filters respectively carry out filtering processing on the results of the timing error detection and send the results to the numerical control oscillator;
two numerically controlled oscillators are used for: and receiving error data processed by the filter, and outputting interpolation parameters to the interpolation filter.
On the basis of the scheme, the first-stage multichannel real number equalizer adopts a 4 x 4 real number equalizer and 16 independent equalization coefficients with the order of 1.
On the basis of the scheme, the Nth-order coefficients of the second-stage single-channel linear real number equalizer are h (- (N-1)/2, k), … … h (-1, k), h (0, k), and h (1, k) … … h ((N-1)/2, k).
On the basis of the scheme, when the two timing error detectors respectively extract the data processed by the second-stage single-channel linear real number equalizer, two equalization coefficients of the extracted second-stage single-channel linear real number equalizer are h (-1, k) and h (1, k).
On the basis of the scheme, the calculation formula of the error detection is as follows:
ekt＝h(-1，k)-h(1，k)。
compared with the prior art, the invention has the advantages that:
the invention adopts a new equalizer structure and algorithm, and simultaneously realizes clock recovery and adaptive equalization. Specifically, a two-stage real number equalization structure and a second-stage adaptive coefficient are adopted to calculate a timing error so as to realize clock recovery, polarization demultiplexing and dispersion compensation. According to the structure, a separate clock recovery module is omitted, the calculation complexity is reduced compared with the traditional structure, the clock recovery accuracy is improved, and the tolerance of IQ data imbalance of a receiving end is improved.
Because the two-stage equalization of the structure adopts real number equalization, IQ two paths of data are not combined together in the equalization process, and the problem that the performance of the system is greatly influenced under the condition that IQ has time delay can be effectively solved. And because the order of the first-stage equalizer is only 1, the calculation complexity is greatly reduced, and the required number of multipliers is reduced to 16+ 4N.
Because the error detection data used by the clock recovery module is subjected to one-stage equalization, the calculated error detection value is more accurate, and the clock recovery is more efficient.
Drawings
Fig. 1 is a block diagram of a conventional clock recovery and adaptive equalizer of the background art.
Fig. 2 is a schematic structural diagram of a clock recovery and adaptive equalizer combination apparatus in coherent optical communication according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
The embodiment of the invention provides a clock recovery and self-adaptive equalizer combined device in coherent optical communication, which comprises two interpolation filters, two groups of first-stage multi-channel real number equalizers, two second-stage single-channel linear real number equalizers, two timing error detectors, two filters and two numerically controlled oscillators, wherein:
two interpolation filters are used: respectively receiving the sampled data of two polarizations, and outputting the data to two groups of first-stage multi-channel real number equalizers;
two sets of first-stage multi-channel real equalizers are used for: receiving data sent by the interpolation filter, carrying out depolarization multiplexing, and respectively outputting the data to a second-stage single-channel linear real number equalizer connected with the data;
two second-stage single-channel linear real equalizers are used: receiving data processed by a first-stage multi-channel real number equalizer, and performing equalization processing, wherein two filter coefficients are output to a connected timing error detector;
two timing error detectors are used: two equalization coefficients which are continuously adjusted in the second-stage single-channel linear real number equalizer are extracted, timing error detection is carried out, and the two equalization coefficients are output to a filter;
two filters are used: filtering the result of timing error detection, and sending the result to a numerically controlled oscillator;
two numerically controlled oscillators are used for: and receiving error data processed by the filter, outputting interpolation parameters to the interpolation filter, and adjusting the coefficient of the interpolation filter.
As a preferred embodiment, as shown in fig. 2, the first stage employs a real number equalizer 4 × 4(4 inputs and 4 outputs) configuration for performing demultiplexing, uses two-polarized IQ two-way real number signals as four inputs and outputs of the equalizer, and employs 16 independent equalization coefficients with order 1. Output 4-way data Emidxi，Emidxq，Emidyi，EmidyqAnd entering a second-stage single-channel linear real number equalizer, wherein the Nth-order coefficient of the second-stage equalizer is h (- (N-1)/2, k), … … h (-1, k), h (0, k), h (1, k) … … h ((N-1)/2, k).
As a preferred embodiment, the timing error detection calculation e is performed by extracting the two equalization coefficients h (-1, k) and h (1, k) of the second stage equalizer from the first stage equalizerktAnd adjusting the coefficient of the interpolation filter through filtering and a numerical control oscillator to realize clock synchronization.
Because the two-stage equalization of the structure adopts real number equalization, IQ two paths of data are not combined together in the equalization process, and the problem that the performance of the system is greatly influenced under the condition that IQ has time delay can be effectively solved. And because the order of the first-stage equalizer is only 1, the calculation complexity is greatly reduced, and the required number of multipliers is reduced to 16+ 4N. In addition, because the error detection data used by the clock recovery module is subjected to one-stage equalization, the calculated error detection value is more accurate, and the clock recovery is more efficient. Namely, the algorithm with the structure simultaneously realizes clock recovery and data balance under the effects of reducing the calculation complexity, reducing the resource consumption and improving the system robustness.
The embodiment of the invention also provides a clock recovery and self-adaptive equalization method in coherent optical communication, which comprises the following steps:
respectively receiving the sampled data of two polarizations by two interpolation filters, and outputting the data to two groups of first-stage multi-channel real number equalizers;
each group of first-stage multi-channel real number equalizer performs depolarization multiplexing on the data sent by the interpolation filter, and outputs the data to a connected second-stage single-channel linear real number equalizer;
the two second-stage single-channel linear real number equalizers respectively receive the data processed by the first-stage multi-channel real number equalizer and perform equalization processing, wherein two filter coefficients are output to a connected timing error detector;
the two timing error detectors respectively extract two equalization coefficients which are continuously adjusted in the second-stage single-channel linear real number equalizer, perform timing error detection and output the timing error detection to the filter;
the two filters respectively carry out filtering processing on the results of the timing error detection and send the results to the numerical control oscillator;
two numerically controlled oscillators are used for: and receiving error data processed by the filter, outputting interpolation parameters to the interpolation filter, and adjusting the coefficient of the interpolation filter.
In a preferred embodiment, the first-stage multi-channel real number equalizer is a 4 × 4 real number equalizer, and 16 independent equalization coefficients with an order of 1 are used.
In a preferred embodiment, the nth order coefficients of the second-stage single-channel linear real number equalizer are h (- (N-1)/2, k), … … h (-1, k), and h (0, k), h (1, k) … … h ((N-1)/2, k), respectively.
As a preferred embodiment, the timing error detection calculation e is performed by extracting the two equalization coefficients h (-1, k) and h (1, k) of the second stage equalizer from the first stage equalizerktAnd adjusting the coefficient of the interpolation filter through filtering and a numerical control oscillator to realize clock synchronization.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (6)
1. The utility model provides a clock recovery and adaptive equalizer combination unit among coherent optical communication which characterized in that includes two interpolation filters, two sets of first order multichannel real number equalizer, two second order single channel linear real number equalizer, two timing error detector, two filters and two numerical control oscillator, wherein:
two interpolation filters are used: respectively receiving the sampled data of two polarizations, and outputting the data to two groups of first-stage multi-channel real number equalizers;
two sets of first-stage multi-channel real equalizers are used for: receiving data sent by the interpolation filter, carrying out depolarization multiplexing, and respectively outputting the data to a second-stage single-channel linear real number equalizer connected with the data; the first-stage multi-channel real number equalizer is a 4 multiplied by 4 real number equalizer and adopts 16 independent equalization coefficients with the order of 1;
two second-stage single-channel linear real equalizers are used: receiving data processed by a first-stage multi-channel real number equalizer, and performing equalization processing, wherein two filter coefficients are output to a connected timing error detector; the Nth-order coefficients of the second-stage single-channel linear real number equalizer are h ((N-1)/2, k), … … h (-1, k), h (0, k), h (1, k) … … h ((N-1)/2, k);
two timing error detectors are used: two equalization coefficients which are continuously adjusted in the second-stage single-channel linear real number equalizer are extracted, timing error detection is carried out, and the two equalization coefficients are output to a filter;
two filters are used: filtering the result of timing error detection, and sending the result to a numerically controlled oscillator;
two numerically controlled oscillators are used for: and receiving error data processed by the filter, outputting interpolation parameters to the interpolation filter, and adjusting the coefficient of the interpolation filter.
2. The apparatus of claim 1, wherein the two equalization coefficients of the decimated second-stage single-channel linear real equalizer are h (-1, k) and h (1, k).
3. The apparatus of claim 2, wherein the error detection is calculated by:
ekt＝h(-1，k)-h(1，k)。
4. a clock recovery and adaptive equalization method in coherent optical communication is characterized by comprising the following steps:
respectively receiving the sampled data of two polarizations by two interpolation filters, and outputting the data to two groups of first-stage multi-channel real number equalizers;
each group of first-stage multi-channel real number equalizer performs depolarization multiplexing on the data sent by the interpolation filter, and outputs the data to a connected second-stage single-channel linear real number equalizer; the first-stage multi-channel real number equalizer adopts a 4 multiplied by 4 real number equalizer and 16 independent equalization coefficients with the order of 1;
the two second-stage single-channel linear real number equalizers respectively receive the data processed by the first-stage multi-channel real number equalizer and perform equalization processing, wherein two filter coefficients are output to a connected timing error detector; the Nth-order coefficients of the second-stage single-channel linear real number equalizer are h ((N-1)/2, k), … … h (-1, k), h (0, k), h (1, k) … … h ((N-1)/2, k);
the two timing error detectors respectively extract two equalization coefficients which are continuously adjusted in the second-stage single-channel linear real number equalizer, perform timing error detection and output the timing error detection to the filter;
the two filters respectively carry out filtering processing on the results of the timing error detection and send the results to the numerical control oscillator;
two numerically controlled oscillators are used for: and receiving error data processed by the filter, and outputting interpolation parameters to the interpolation filter.
5. The method of claim 4, wherein when the two timing error detectors respectively extract the data processed by the second-stage single-channel linear real number equalizer, the two extracted equalization coefficients of the second-stage single-channel linear real number equalizer are h (-1, k) and h (1, k).
6. The method of claim 5, wherein the error detection is calculated by:
ekt＝h(-1，k)-h(1，k)。
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| CN112291009B (en) * | 2020-10-20 | 2022-02-08 | 武汉邮电科学研究院有限公司 | Multi-stage equalizer for coherent reception of burst data and implementation method |
| CN112600625B (en) * | 2020-12-08 | 2022-09-23 | 复旦大学 | Distance measurement and communication integrated spatial laser heterodyne coherent demodulation processing module and method |
| CN112636842B (en) * | 2020-12-29 | 2022-03-25 | 武汉邮电科学研究院有限公司 | Low-power-consumption DSP device and working method thereof |
| CN114337843B (en) * | 2021-12-23 | 2023-11-28 | 武汉邮电科学研究院有限公司 | Self-adaptive channel equalization method and system for coherent optical communication |
| CN115001645B (en) * | 2022-06-13 | 2023-12-26 | 北京邮电大学 | Clock recovery method, clock recovery device, electronic equipment and computer storage medium |
| CN115102628B (en) * | 2022-06-14 | 2024-01-16 | 武汉邮电科学研究院有限公司 | Adaptive channel equalization algorithm and device |
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