CN112636842B - Low-power-consumption DSP device and working method thereof - Google Patents
Low-power-consumption DSP device and working method thereof Download PDFInfo
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- CN112636842B CN112636842B CN202011610124.3A CN202011610124A CN112636842B CN 112636842 B CN112636842 B CN 112636842B CN 202011610124 A CN202011610124 A CN 202011610124A CN 112636842 B CN112636842 B CN 112636842B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
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- H04B10/616—Details of the electronic signal processing in coherent optical receivers
- H04B10/6164—Estimation or correction of the frequency offset between the received optical signal and the optical local oscillator
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
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- H04B10/61—Coherent receivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/61—Coherent receivers
- H04B10/616—Details of the electronic signal processing in coherent optical receivers
- H04B10/6165—Estimation of the phase of the received optical signal, phase error estimation or phase error correction
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Abstract
The application relates to a low-power consumption DSP device and a using method thereof, relating to the technical field of communication, wherein the device comprises: the adaptive equalization module comprises a single-channel equalization submodule and an MIMO equalization submodule which are sequentially connected, wherein the MIMO equalization submodule is used for carrying out channel equalization work; the CORDIC conversion module comprises a plurality of CORDIC conversion submodules which are connected in sequence; the frequency offset recovery module comprises a plurality of frequency offset recovery sub-modules which are connected in sequence; the phase deviation recovery module comprises a plurality of phase deviation recovery submodules which are sequentially connected. According to the method and the device, partial modules of the DSP device are subjected to grading processing, specific grading modules are selected according to performance requirements, and unnecessary grading modules are closed and do not work, so that the DSP device can keep the lowest power consumption working state according to the link condition.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a low-power-consumption DSP device and a working method thereof.
Background
In recent years, the bandwidth and distance requirements of optical access networks have increased dramatically. In a current Passive Optical Network (PON) system, both upstream and downstream transmissions adopt a traditional intensity modulation and direct detection scheme, and a transmission distance and capacity are limited. Future PON systems will use an advanced Phase Shift Keying (QPSK) format to effectively increase the data rate per wavelength. And by adopting the coherent receiving scheme, due to the high sensitivity and the advancement of Digital Signal Processing (DSP), the input dynamic range is expanded and the transmission distance is prolonged while the extremely high receiving sensitivity of coherent detection is kept.
The digital signal processing module of the traditional coherent optical communication receiver consists of a plurality of complex arithmetic units, comprising: clock recovery → dispersion compensation → adaptive equalization → CORDIC angle transformation → frequency difference estimation and compensation → phase difference estimation and compensation → symbol decision, the clock recovery module is used to recover the clock of the transmitting and receiving end in the asynchronization in frequency and phase. The dispersion compensation module is used for compensating dispersion suffered by the optical fiber channel transmission process. The main function of the adaptive equalizer is to remove the signal from the impairments due to the chromatic dispersion, polarization film dispersion, and intersymbol interference. CORDIC angle transformation transforms complex information into angle information. The frequency offset estimation and compensation is used for removing the influence of the frequency offset on the phase information of the received signal, the phase difference estimation and compensation is used for removing the influence of the phase offset on the phase information of the received signal, and the code element judgment is used for restoring the angle information into the original binary data.
The equipment of the optical network unit has the requirements of low cost and low power consumption in the PON system. Because in the coherent detection scheme, the power consumption of the DSP is the largest, how to design the DSP makes the power consumption of the ONU receiving devices in different environments and different distances all to be kept the lowest is a key problem to be solved by this patent.
Disclosure of Invention
The application provides a low-power consumption DSP device and a working method thereof, wherein partial modules of the DSP device are subjected to grading treatment, specific grading modules are selected according to performance requirements, and unnecessary grading modules are closed and do not work, so that the DSP device can keep the lowest power consumption working state according to link conditions.
In a first aspect, the present application provides a low power consumption DSP apparatus, the apparatus comprising:
the adaptive equalization module comprises a single-channel equalization submodule and an MIMO equalization submodule which are sequentially connected, wherein the single-channel equalization submodule is used for selecting whether to assist the MIMO equalization submodule to perform channel equalization work according to performance requirements;
the CORDIC conversion module comprises a plurality of CORDIC conversion submodules which are sequentially connected, and each stage of the CORDIC conversion submodule is used for selecting whether to cooperatively perform CORDIC conversion work according to performance requirements;
the frequency offset recovery module comprises a plurality of frequency offset recovery sub-modules which are connected in sequence, and each level of frequency offset recovery sub-module is used for selecting whether to carry out frequency offset recovery work in a coordinated manner according to performance requirements;
the phase deviation recovery module comprises a plurality of phase deviation recovery submodules which are sequentially connected, and each phase deviation recovery submodule is used for selecting whether to cooperatively perform phase deviation recovery work according to performance requirements.
Specifically, the adaptive equalization module is configured with a first enable switch, and the first enable switch is used for controlling the single-channel equalization submodule to enter an enable state according to a performance requirement;
the CORDIC conversion module is provided with a second enabling switch, and the second enabling switch is used for controlling the CORDIC conversion sub-module to enter an enabling state according to performance requirements;
the frequency offset recovery module is configured with a third enabling switch, and the third enabling switch is used for controlling the frequency offset recovery submodule to enter an enabling state according to the performance requirement;
and the phase deviation recovery module is configured with a fourth enabling switch, and the fourth enabling switch is used for controlling the phase deviation recovery submodule to enter an enabling state according to the performance requirement.
Further, the apparatus further comprises:
the clock recovery module is in signal connection with the self-adaptive equalization module;
and the judgment module is in signal connection with the phase offset recovery module.
In a second aspect, the present application provides a low power consumption DSP apparatus, the apparatus comprising:
the adaptive equalization module comprises a single-channel equalization submodule and an MIMO equalization submodule which are sequentially connected, wherein the single-channel equalization submodule is used for selecting whether to assist the MIMO equalization submodule to perform channel equalization work according to performance requirements;
the CORDIC conversion module comprises a first-order CORDIC conversion submodule and a second-order CORDIC conversion submodule which are sequentially connected, wherein the first-order CORDIC conversion submodule is used for carrying out CORDIC conversion work, and the second-order CORDIC conversion submodule is used for selecting whether to assist the first-order CORDIC conversion submodule to carry out CORDIC conversion work according to performance requirements;
the frequency offset recovery module comprises a frequency offset recovery primary submodule and a frequency offset recovery secondary submodule which are sequentially connected, wherein the frequency offset recovery primary submodule is used for carrying out frequency offset recovery work, and the frequency offset recovery secondary submodule is used for selecting whether to assist the frequency offset recovery primary submodule to carry out frequency offset recovery work according to performance requirements;
the phase offset recovery module comprises a phase offset recovery primary submodule and a phase offset recovery secondary submodule which are sequentially connected, wherein the phase offset recovery primary submodule is used for performing phase offset recovery work, and the phase offset recovery secondary submodule is used for selecting whether to assist the phase offset recovery primary submodule to perform frequency offset recovery work according to performance requirements.
Specifically, the adaptive equalization module is configured with a first enable switch, and the first enable switch is configured to respond to the first enable signal to control the single-channel equalization sub-module to enter an enable state;
the CORDIC conversion module is provided with a second enabling switch, and the second enabling switch is used for responding to a second enabling signal to control the CORDIC secondary conversion submodule to enter an enabling state;
the frequency offset recovery module is configured with a third enabling switch, and the third enabling switch is used for responding to a third enabling signal to control the frequency offset recovery secondary sub-module to enter an enabling state;
the phase deviation recovery module is provided with a fourth enabling switch, and the fourth enabling switch is used for responding to a fourth enabling signal to control the phase deviation recovery secondary submodule to enter an enabling state.
In a third aspect, the present application provides a method for operating a low power consumption DSP apparatus, the method comprising the steps of:
placing a low-power-consumption DSP device at an ONU end in a minimum enabling mode, sending a communication handshake frame to the ONU by utilizing an OLT, and detecting the data receiving performance of the communication handshake frame by the ONU;
controlling the single-channel equalization submodule, the rest CORDIC conversion submodule, the rest frequency offset recovery submodule and the rest phase offset recovery submodule step by step to enter an enabling state, enabling the low-power-consumption DSP device to be in different working states, and simultaneously detecting the data receiving performance of the communication handshake frame in different working states;
after the communication handshake frame is transmitted, selecting a working state corresponding to the condition that the data receiving performance of the communication handshake frame in the step-by-step control process firstly meets the preset data receiving performance standard as an optimal working state;
and controlling the single-channel equalization submodule, the residual CORDIC conversion submodule, the residual frequency offset recovery submodule and the residual phase offset recovery submodule to enter an enabling state corresponding to each module enabling state corresponding to the optimal working state.
Specifically, when only the MIMO equalization submodule of the adaptive equalization module, the first CORDIC transformation submodule of the CORDIC transformation module, the first frequency offset recovery submodule of the frequency offset recovery module, and the first phase offset recovery submodule of the phase offset recovery module operate, the low-power-consumption DSP apparatus is in a minimum enable mode;
and when the single-channel equalization submodule, the rest CORDIC transformation submodules, the rest frequency offset recovery submodules and the rest phase offset recovery submodules are all in an enabling state, the low-power-consumption DSP device is in a maximum enabling mode.
Further, the method comprises the following steps:
controlling the single-channel equalization submodule to enter an enabling state by utilizing a first enabling switch;
controlling the rest CORDIC conversion sub-modules to enter an enabling state by using a second enabling switch;
controlling the residual frequency offset recovery sub-module to enter an enabling state by using a third enabling switch;
and controlling the remaining phase deviation recovery submodules to enter an enabling state by using a fourth enabling switch.
In a fourth aspect, the present application provides a method for operating a low power consumption DSP apparatus, the method comprising the steps of:
placing a low-power-consumption DSP device at an ONU end into a minimum enabling mode, sending a communication handshake frame to the ONU by utilizing the OLT, detecting the data receiving performance of the communication handshake frame by the ONU,
controlling the single-channel equalization submodule, the CORDIC second-stage transformation submodule, the frequency offset recovery second-stage submodule and the phase offset recovery second-stage submodule step by step to enter an enabling state, enabling the low-power-consumption DSP device to be in different working states, and simultaneously detecting the data receiving performance of the communication handshake frame in different working states;
after the communication handshake frame is transmitted, selecting a working state corresponding to the condition that the data receiving performance of the communication handshake frame in the step-by-step control process firstly meets the preset data receiving performance standard as an optimal working state;
and controlling the single-channel equalization submodule, the CORDIC secondary transformation submodule, the frequency offset recovery submodule and the phase offset recovery submodule to enter the enabling state corresponding to each module enabling state corresponding to the optimal working state.
Further, the method comprises the following steps:
controlling the single-channel equalization submodule to enter an enabling state by utilizing a first enabling switch;
controlling the CORDIC secondary transformation submodule to enter an enabling state by utilizing a second enabling switch;
controlling the frequency offset recovery secondary sub-module to enter an enabling state by using a third enabling switch;
and controlling the phase deviation recovery secondary submodule to enter an enabling state by using a fourth enabling switch.
The beneficial effect that technical scheme that this application provided brought includes:
according to the method and the device, partial modules of the DSP device are subjected to grading processing, specific grading modules are selected according to performance requirements, and unnecessary grading modules are closed and do not work, so that the DSP device can keep the lowest power consumption working state according to the link condition.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a low power consumption DSP apparatus according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a low power consumption DSP apparatus according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a prior art DSP apparatus provided by an embodiment of the present application;
the labels in the figure are:
1. a self-adaptive equalization module; 10. a single-channel equalization submodule; 11. a MIMO equalization submodule; 12. a first enable switch; 2. a CORDIC conversion module; 20. a CORDIC transform submodule; 21. a CORDIC first-order transformation submodule; 22. a CORDIC second-order transformation submodule; 23. a second enable switch; 3. a frequency offset recovery module; 30. a frequency offset recovery submodule; 31. recovering a first-level sub-module from the frequency offset; 32. recovering a secondary submodule of the frequency offset; 33. a third enable switch; 4. a phase offset recovery module; 40. a phase offset recovery submodule; 41. restoring a first-level submodule by phase offset; 42. phase deviation recovery secondary sub-modules; 43. a fourth enable switch; 5. a clock recovery module; 6. and a decision module.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
The embodiment of the invention provides a low-power-consumption DSP device and a working method thereof, which are used for carrying out grading processing on partial modules of the DSP device, selecting specific grading modules according to performance requirements, and closing unnecessary grading modules to be out of work, so that the DSP device can keep the lowest-power-consumption working state according to the link condition.
In order to achieve the technical effects, the general idea of the application is as follows:
a low power consumption DSP apparatus, the apparatus comprising:
the adaptive equalization module 1, the adaptive equalization module 1 includes a single-channel equalization submodule 10 and an MIMO equalization submodule 11 for performing channel equalization work, which are connected in sequence, the single-channel equalization submodule 10 is used for selecting whether to assist the MIMO equalization submodule 11 to perform channel equalization work according to performance requirements;
the CORDIC conversion module 2 is characterized in that the CORDIC conversion module 2 comprises a plurality of CORDIC conversion submodules 20 which are sequentially connected, and each stage of CORDIC conversion submodule 20 is used for selecting whether to cooperatively perform CORDIC conversion work according to performance requirements;
the frequency offset recovery module 3, the frequency offset recovery module 3 includes a plurality of frequency offset recovery submodules 30 connected in sequence, each level of frequency offset recovery submodule 30 is used for selecting whether to carry out frequency offset recovery work cooperatively according to performance requirements;
the phase offset recovery module 4, the phase offset recovery module 4 includes a plurality of phase offset recovery submodules 40 connected in sequence, and each phase offset recovery submodule 40 is used to select whether to cooperate with the phase offset recovery according to the performance requirement.
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
In a first aspect, referring to fig. 1 to 3, an embodiment of the present invention provides a low power consumption DSP apparatus, including:
the adaptive equalization module 1, the adaptive equalization module 1 includes a single-channel equalization submodule 10 and an MIMO equalization submodule 11 for performing channel equalization work, which are connected in sequence, the single-channel equalization submodule 10 is used for selecting whether to assist the MIMO equalization submodule 11 to perform channel equalization work according to performance requirements;
the CORDIC conversion module 2 is characterized in that the CORDIC conversion module 2 comprises a plurality of CORDIC conversion submodules 20 which are sequentially connected, and each stage of CORDIC conversion submodule 20 is used for selecting whether to cooperatively perform CORDIC conversion work according to performance requirements;
the frequency offset recovery module 3, the frequency offset recovery module 3 includes a plurality of frequency offset recovery submodules 30 connected in sequence, each level of frequency offset recovery submodule 30 is used for selecting whether to carry out frequency offset recovery work cooperatively according to performance requirements;
the phase offset recovery module 4, the phase offset recovery module 4 includes a plurality of phase offset recovery submodules 40 connected in sequence, and each phase offset recovery submodule 40 is used to select whether to cooperate with the phase offset recovery according to the performance requirement.
In the embodiment of the application, partial modules of the DSP device are subjected to grading processing, specific grading modules are selected according to performance requirements, and unnecessary grading modules are closed and do not work, so that the DSP device can keep the lowest power consumption working state according to the link condition.
Further, the adaptive equalization module 1 is configured with a first enable switch 12, and the first enable switch 12 is used for controlling the single-channel equalization submodule 10 to enter an enable state according to the performance requirement;
the CORDIC transformation module 2 is configured with a second enable switch 23, and the second enable switch 23 is used for controlling the CORDIC transformation submodule 20 to enter an enable state according to the performance requirement;
the frequency offset recovery module 3 is configured with a third enable switch 33, and the third enable switch 33 is used for controlling the frequency offset recovery submodule 30 to enter an enable state according to the performance requirement;
the phase offset recovery module 4 is configured with a fourth enable switch 43, and the fourth enable switch 43 is used for controlling the phase offset recovery submodule 40 to enter an enable state according to the performance requirement.
Further, the apparatus further comprises:
the clock recovery module 5 is in signal connection with the adaptive equalization module 1;
and the decision module 6 is connected with the phase offset recovery module 4 through signals.
It should be noted that, in the embodiment of the present application, in the burst-mode coherent PON based on dual-polarization multi-phase modulation, a part of modules of a DSP is processed in a hierarchical manner, and an ONU determines which level the hierarchical module of the DSP in a local ONU needs to enable through performance monitoring of a transmitted communication handshake frame, and the module that does not need to enable turns off the hierarchical module of the DSP in the local ONU does not work, so that the DSP part of the local ONU can keep working at the lowest power according to the condition of the link, thereby achieving the effect of low power consumption.
Specifically, in another aspect of the embodiment of the present application, specifically, as follows, the low power consumption DSP apparatus includes:
the adaptive equalization module 1, the adaptive equalization module 1 includes a single-channel equalization submodule 10 and an MIMO equalization submodule 11 for performing channel equalization work, which are connected in sequence, the single-channel equalization submodule 10 is used for selecting whether to assist the MIMO equalization submodule 11 to perform channel equalization work according to performance requirements;
the CORDIC conversion module 2 is characterized in that the CORDIC conversion module 2 comprises a first-order CORDIC conversion submodule 21 and a second-order CORDIC conversion submodule 22 which are sequentially connected, the first-order CORDIC conversion submodule 21 is used for carrying out CORDIC conversion work, and the second-order CORDIC conversion submodule 22 is used for selecting whether to assist the first-order CORDIC conversion submodule 21 in carrying out CORDIC conversion work according to performance requirements;
the frequency offset recovery module 3, the frequency offset recovery module 3 includes a frequency offset recovery primary submodule 31 and a frequency offset recovery secondary submodule 32 which are connected in sequence, the frequency offset recovery primary submodule 31 is used for performing frequency offset recovery work, and the frequency offset recovery secondary submodule 32 is used for selecting whether to assist the frequency offset recovery primary submodule 31 to perform frequency offset recovery work according to performance requirements;
the phase offset recovery module 4, the phase offset recovery module 4 includes a phase offset recovery primary sub-module 41 and a phase offset recovery secondary sub-module 42 that are connected in sequence, the phase offset recovery primary sub-module 41 is used for performing phase offset recovery, and the phase offset recovery secondary sub-module 42 is used for selecting whether to assist the phase offset recovery primary sub-module 41 to perform frequency offset recovery according to performance requirements.
Correspondingly, in this case, the adaptive equalization module 1 is configured with a first enable switch 12, the first enable switch 12 being configured to control the single-channel equalization submodule 10 into an enabled state in response to a first enable signal;
the CORDIC conversion module 2 is provided with a second enabling switch 23, and the second enabling switch 23 is used for responding to a second enabling signal to control the CORDIC second-order conversion submodule 22 to enter an enabling state;
the frequency offset recovery module 3 is configured with a third enable switch 33, and the third enable switch 33 is configured to control the frequency offset recovery secondary sub-module 32 to enter an enable state in response to a third enable signal;
the phase offset recovery module 4 is configured with a fourth enable switch 43, and the fourth enable switch 43 is used for controlling the phase offset recovery secondary sub-module 42 to enter an enable state in response to a fourth enable signal.
Also in this case, the apparatus also includes:
the clock recovery module 5 is in signal connection with the adaptive equalization module 1;
and the decision module 6 is connected with the phase offset recovery module 4 through signals.
In practical implementation, the design of the DSP grading module is as follows:
the original channel adaptive equalization module is divided into two stages, namely a 3-tap single-channel adaptive equalization module and a 5-tap 2 multiplied by 2 MIMO adaptive equalization module;
the CORDIC module is divided into 10 stages of iteration and subsequent 8 stages of iteration by direct 18 stages of iteration;
the frequency difference and phase difference compensation module is an adaptive equalization module which is divided into 2 levels and 16 windows in an original 32-length window equalization mode.
At this time, all the modules of the DSP include a clock recovery module, a 3-tap single-channel adaptive equalization module, a 5-tap MIMO adaptive equalization module, a first stage CORDIC transformation module, a second stage CORDIC transformation module, a first stage frequency offset recovery module, a second stage frequency offset recovery module, a first stage phase offset recovery module, a second stage phase offset recovery module, and a decision module.
It should be noted that all modules are enabled to be in a full-enabled mode, and at this time, the performance of the receiving system is optimal;
the 3-tap single-channel self-adaptive equalization module, the CORDIC conversion secondary module, the frequency offset recovery secondary module and the phase offset recovery secondary module are controlled to be turned on and turned off by enabling switches ena1, ena2, ena3 and ena4 respectively;
and when the system is in the minimum enabling mode, the system works in the partial enabling mode.
When the low-power-consumption DSP device is used, firstly, the OLT sends a communication handshake frame to the ONU, the ONU detects and records the receiving performance of the frame data in different DSP modes, and an enabling module of the DSP at a receiving end is adjusted according to the performance parameters of the received data;
the specific judgment basis is the error rate, when the error rate is lower than a preset error rate threshold value, the fact that the power of the current DSP device is too low is indicated, and adjustment is needed until the effect of low power consumption is achieved on the premise that the performance requirement is met.
In the process of sending handshake data, firstly, an ONU end DSP is set in a minimum enabling mode, the receiving performance of a receiving end at the moment is detected and recorded, then an ena1 enabling switch is started to set the DSP in the enabling mode, the receiving performance at the moment is recorded, then an ena2 enabling switch is started to set the DSP in the enabling mode, the receiving performance in the mode is recorded, then an ena3 enabling switch is started to set the DSP in the enabling mode, the receiving performance in the mode is recorded, and finally an ena4 enabling switch is started to set the DSP in the enabling mode, and the receiving performance in the mode is recorded;
after the data transmission of the communication frame for handshaking is finished, the ONU finishes recording the performance data in each mode, compares the performance data, selects a module needing to be started which firstly reaches the performance standard above as a working mode, and receives and processes the subsequent data frame;
if the receiving performance reaches the standard in the simplest mode, the DSP keeps working in the simplest mode without starting any enabling module.
According to the embodiment of the application, the original DSP processing module is subjected to hierarchical processing, the PON system communication handshake frame is used for determining the minimum module number required by the DSP of the ONU terminal, and the power consumption and the time delay of the ONU receiving terminal can be dynamically adjusted under the condition that the resource consumption is not increased, so that the DSP part of the ONU is always in the mode of minimum power consumption and minimum time delay.
In a second aspect, an embodiment of the present invention provides a method for operating a low power consumption DSP apparatus, where the method includes:
s1, placing the low-power-consumption DSP device at the ONU end in a minimum enabling mode, sending a communication handshake frame to the ONU by using the OLT, and detecting the data receiving performance of the communication handshake frame by the ONU;
s2, controlling the single-channel equalization submodule 10, the residual CORDIC transformation submodule 20, the residual frequency offset recovery submodule 30 and the residual phase offset recovery submodule 40 step by step to enter an enabling state, enabling the low-power-consumption DSP device to be in different working states, and detecting the data receiving performance of a communication handshake frame in different working states;
s3, after the transmission of the communication handshake frame is finished, selecting the working state corresponding to the condition that the data receiving performance of the communication handshake frame in the step-by-step control process firstly meets the preset data receiving performance standard as the optimal working state;
and S4, controlling the single-channel equalization submodule 10, the residual CORDIC transformation submodule 20, the residual frequency offset recovery submodule 30 and the residual phase offset recovery submodule 40 to enter the enabling state correspondingly according to the enabling state of each module corresponding to the optimal working state.
In the embodiment of the application, partial modules of the DSP device are subjected to grading processing, specific grading modules are selected according to performance requirements, and unnecessary grading modules are closed and do not work, so that the DSP device can keep the lowest power consumption working state according to the link condition.
It should be noted that, when only the MIMO equalizing submodule 11 of the adaptive equalizing module 1, the first CORDIC transformation submodule 20 of the CORDIC transformation module 2, the first frequency offset recovery submodule 30 of the frequency offset recovery module 3, and the first phase offset recovery submodule 40 of the phase offset recovery module 4 work, the low-power DSP apparatus is in the minimum enabling mode;
when the single-channel equalization submodule 10, the residual CORDIC transformation submodule 20, the residual frequency offset recovery submodule 30 and the residual phase offset recovery submodule 40 are all in an enabling state, the low-power-consumption DSP apparatus is in a maximum enabling mode.
Further, the method comprises the following steps:
a1, controlling the single-channel equalization submodule 10 to enter an enabling state by utilizing the first enabling switch 12;
a2, controlling the remaining CORDIC conversion submodule 20 to enter an enabling state by using a second enabling switch 23;
a3, using the third enabling switch 33 to control the residual frequency offset recovery submodule 30 to enter the enabling state;
a4, using the fourth enable switch 43 to control the remaining phase offset recovery submodule 40 to enter the enabled state.
Here, a low power consumption DSP apparatus based on the embodiment of the present application is explained, the low power consumption DSP apparatus including:
the adaptive equalization module 1, the adaptive equalization module 1 includes a single-channel equalization submodule 10 and an MIMO equalization submodule 11 for performing channel equalization work, which are connected in sequence, the single-channel equalization submodule 10 is used for selecting whether to assist the MIMO equalization submodule 11 to perform channel equalization work according to performance requirements;
the CORDIC conversion module 2 is characterized in that the CORDIC conversion module 2 comprises a plurality of CORDIC conversion submodules 20 which are sequentially connected, and each stage of CORDIC conversion submodule 20 is used for selecting whether to cooperatively perform CORDIC conversion work according to performance requirements;
the frequency offset recovery module 3, the frequency offset recovery module 3 includes a plurality of frequency offset recovery submodules 30 connected in sequence, each level of frequency offset recovery submodule 30 is used for selecting whether to carry out frequency offset recovery work cooperatively according to performance requirements;
the phase offset recovery module 4, the phase offset recovery module 4 includes a plurality of phase offset recovery submodules 40 connected in sequence, and each phase offset recovery submodule 40 is used to select whether to cooperate with the phase offset recovery according to the performance requirement.
Further, the adaptive equalization module 1 is configured with a first enable switch 12, and the first enable switch 12 is used for controlling the single-channel equalization submodule 10 to enter an enable state according to the performance requirement;
the CORDIC transformation module 2 is configured with a second enable switch 23, and the second enable switch 23 is used for controlling the CORDIC transformation submodule 20 to enter an enable state according to the performance requirement;
the frequency offset recovery module 3 is configured with a third enable switch 33, and the third enable switch 33 is used for controlling the frequency offset recovery submodule 30 to enter an enable state according to the performance requirement;
the phase offset recovery module 4 is configured with a fourth enable switch 43, and the fourth enable switch 43 is used for controlling the phase offset recovery submodule 40 to enter an enable state according to the performance requirement.
Further, the low power consumption DSP apparatus further includes:
the clock recovery module 5 is in signal connection with the adaptive equalization module 1;
and the decision module 6 is connected with the phase offset recovery module 4 through signals.
In a third aspect, an embodiment of the present invention provides another method for operating a low-power-consumption DSP apparatus, where the method includes:
q1, placing the low-power consumption DSP device at the ONU end into a minimum enabling mode, sending a communication handshake frame to the ONU by utilizing the OLT, detecting the data receiving performance of the communication handshake frame by the ONU,
q2, controlling the single-channel equalization submodule 10, the CORDIC second-order transformation submodule 22, the frequency offset recovery second-order submodule 32 and the phase offset recovery second-order submodule 42 step by step to enter an enabling state, enabling the low-power-consumption DSP device to be in different working states, and detecting the data receiving performance of a communication handshake frame in different working states;
q3, after the transmission of the communication handshake frame is finished, selecting the working state corresponding to the condition that the data receiving performance of the communication handshake frame in the step-by-step control process firstly meets the preset data receiving performance standard as the optimal working state;
and Q4, controlling the single-channel equalization submodule 10, the CORDIC second-order transformation submodule 22, the frequency offset recovery second-order submodule 32 and the phase offset recovery second-order submodule 42 to enter the enabling state correspondingly according to the enabling state of each module corresponding to the optimal working state.
In the embodiment of the application, partial modules of the DSP device are subjected to grading processing, specific grading modules are selected according to performance requirements, and unnecessary grading modules are closed and do not work, so that the DSP device can keep the lowest power consumption working state according to the link condition.
It should be noted that, when only the MIMO equalization submodule 11, the CORDIC first-order transformation submodule 21, the frequency offset recovery first-order submodule 31, and the phase offset recovery first-order submodule 41 of the adaptive equalization module 1 work, the low-power-consumption DSP apparatus is in the minimum enable mode;
when the single-channel equalization submodule 10, the CORDIC second-order transformation submodule 22, the frequency offset recovery second-order submodule 32 and the phase offset recovery second-order submodule 42 are all in the enabling state, the low-power-consumption DSP apparatus is in the maximum enabling mode.
Further, the method comprises the following steps:
b1, controlling the single-channel equalization submodule 10 to enter an enabling state by utilizing the first enabling switch 12;
b2, controlling the CORDIC second-order transformation submodule 22 to enter an enabling state by using a second enabling switch 23;
b3, controlling the frequency offset recovery secondary submodule 32 to enter an enabling state by using a third enabling switch 33;
b4, using the fourth enable switch 43 to control the phase offset recovery secondary sub-module 42 to enter the enabled state.
Here, a low power consumption DSP apparatus based on the embodiment of the present application is explained, the low power consumption DSP apparatus including:
the adaptive equalization module 1, the adaptive equalization module 1 includes a single-channel equalization submodule 10 and an MIMO equalization submodule 11 for performing channel equalization work, which are connected in sequence, the single-channel equalization submodule 10 is used for selecting whether to assist the MIMO equalization submodule 11 to perform channel equalization work according to performance requirements;
the CORDIC conversion module 2 is characterized in that the CORDIC conversion module 2 comprises a first-order CORDIC conversion submodule 21 and a second-order CORDIC conversion submodule 22 which are sequentially connected, the first-order CORDIC conversion submodule 21 is used for carrying out CORDIC conversion work, and the second-order CORDIC conversion submodule 22 is used for selecting whether to assist the first-order CORDIC conversion submodule 21 in carrying out CORDIC conversion work according to performance requirements;
the frequency offset recovery module 3, the frequency offset recovery module 3 includes a frequency offset recovery primary submodule 31 and a frequency offset recovery secondary submodule 32 which are connected in sequence, the frequency offset recovery primary submodule 31 is used for performing frequency offset recovery work, and the frequency offset recovery secondary submodule 32 is used for selecting whether to assist the frequency offset recovery primary submodule 31 to perform frequency offset recovery work according to performance requirements;
the phase offset recovery module 4, the phase offset recovery module 4 includes a phase offset recovery primary sub-module 41 and a phase offset recovery secondary sub-module 42 that are connected in sequence, the phase offset recovery primary sub-module 41 is used for performing phase offset recovery, and the phase offset recovery secondary sub-module 42 is used for selecting whether to assist the phase offset recovery primary sub-module 41 to perform frequency offset recovery according to performance requirements.
Correspondingly, the adaptive equalization module 1 is configured with a first enable switch 12, and the first enable switch 12 is used for controlling the single-channel equalization sub-module 10 to enter an enable state in response to a first enable signal;
the CORDIC conversion module 2 is provided with a second enabling switch 23, and the second enabling switch 23 is used for responding to a second enabling signal to control the CORDIC second-order conversion submodule 22 to enter an enabling state;
the frequency offset recovery module 3 is configured with a third enable switch 33, and the third enable switch 33 is configured to control the frequency offset recovery secondary sub-module 32 to enter an enable state in response to a third enable signal;
the phase offset recovery module 4 is configured with a fourth enable switch 43, and the fourth enable switch 43 is used for controlling the phase offset recovery secondary sub-module 42 to enter an enable state in response to a fourth enable signal.
Further, the low power consumption DSP apparatus further includes:
the clock recovery module 5 is in signal connection with the adaptive equalization module 1;
and the decision module 6 is connected with the phase offset recovery module 4 through signals.
It is noted that, in the present application, relational terms such as "first" and "second", and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present application and are presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A low power consumption DSP apparatus, characterized in that the apparatus comprises:
the adaptive equalization module (1), the adaptive equalization module (1) comprises a single-channel equalization submodule (10) and an MIMO equalization submodule (11) which are connected in sequence, the single-channel equalization submodule (10) is used for selecting whether to assist the MIMO equalization submodule (11) to perform channel equalization work according to performance requirements;
the CORDIC conversion module (2) comprises a plurality of CORDIC conversion submodules (20) which are sequentially connected, and each stage of the CORDIC conversion submodule (20) is used for selecting whether to cooperatively perform CORDIC conversion work according to performance requirements;
the frequency offset recovery module (3), the frequency offset recovery module (3) includes a plurality of frequency offset recovery submodules (30) connected in sequence, each level of the frequency offset recovery submodules (30) is used for selecting whether to carry out frequency offset recovery work cooperatively according to performance requirements;
the phase deviation recovery module (4), the phase deviation recovery module (4) comprises a plurality of phase deviation recovery submodules (40) which are connected in sequence, and each phase deviation recovery submodule (40) is used for selecting whether to carry out phase deviation recovery work in a coordinated mode according to performance requirements;
the low-power consumption DSP device comprises the following working procedures:
controlling the single-channel equalization submodule (10), the residual CORDIC conversion submodule (20), the residual frequency offset recovery submodule (30) and the residual phase offset recovery submodule (40) to enter an enabling state step by step, enabling the low-power-consumption DSP device to be in different working states, and detecting the data receiving performance of a communication handshake frame under different working states;
after the communication handshake frame is transmitted, selecting a working state corresponding to the condition that the data receiving performance of the communication handshake frame in the step-by-step control process firstly meets the preset data receiving performance standard as an optimal working state;
and controlling the single-channel equalization submodule (10), the residual CORDIC conversion submodule (20), the residual frequency offset recovery submodule (30) and the residual phase offset recovery submodule (40) to enter an enabling state correspondingly according to the enabling state of each module corresponding to the optimal working state.
2. The low power consumption DSP apparatus of claim 1, wherein:
the adaptive equalization module (1) is provided with a first enabling switch (12), and the first enabling switch (12) is used for controlling the single-channel equalization submodule (10) to enter an enabling state according to performance requirements;
the CORDIC conversion module (2) is provided with a second enabling switch (23), and the second enabling switch (23) is used for controlling the CORDIC conversion sub-module (20) to enter an enabling state according to performance requirements;
the frequency offset recovery module (3) is configured with a third enable switch (33), and the third enable switch (33) is used for controlling the frequency offset recovery submodule (30) to enter an enable state according to performance requirements;
the phase deviation recovery module (4) is provided with a fourth enabling switch (43), and the fourth enabling switch (43) is used for controlling the phase deviation recovery submodule (40) to enter an enabling state according to performance requirements.
3. The low power consumption DSP apparatus of claim 1, wherein said apparatus further comprises:
a clock recovery module (5) in signal connection with the adaptive equalization module (1);
and the decision module (6) is in signal connection with the phase deviation recovery module (4).
4. A low power consumption DSP apparatus, characterized in that the apparatus comprises:
the adaptive equalization module (1), the adaptive equalization module (1) comprises a single-channel equalization submodule (10) and an MIMO equalization submodule (11) which are connected in sequence, the single-channel equalization submodule (10) is used for selecting whether to assist the MIMO equalization submodule (11) to perform channel equalization work according to performance requirements;
the CORDIC conversion module (2) comprises a first-order CORDIC conversion submodule (21) and a second-order CORDIC conversion submodule (22) which are sequentially connected, wherein the first-order CORDIC conversion submodule (21) is used for carrying out CORDIC conversion work, and the second-order CORDIC conversion submodule (22) is used for selecting whether to assist the first-order CORDIC conversion submodule (21) in carrying out the CORDIC conversion work according to performance requirements;
the frequency offset recovery module (3), the frequency offset recovery module (3) includes a frequency offset recovery first-level sub-module (31) and a frequency offset recovery second-level sub-module (32) which are connected in sequence, the frequency offset recovery first-level sub-module (31) is used for performing frequency offset recovery work, and the frequency offset recovery second-level sub-module (32) is used for selecting whether to assist the frequency offset recovery first-level sub-module (31) to perform frequency offset recovery work according to performance requirements;
the phase offset recovery module (4), the phase offset recovery module (4) comprises a phase offset recovery primary sub-module (41) and a phase offset recovery secondary sub-module (42) which are sequentially connected, the phase offset recovery primary sub-module (41) is used for performing phase offset recovery work, and the phase offset recovery secondary sub-module (42) is used for selecting whether to assist the phase offset recovery primary sub-module (41) in performing frequency offset recovery work according to performance requirements;
the low-power consumption DSP device comprises the following working procedures:
controlling the single-channel equalization submodule (10), the residual CORDIC conversion submodule (20), the residual frequency offset recovery submodule (30) and the residual phase offset recovery submodule (40) to enter an enabling state step by step, enabling the low-power-consumption DSP device to be in different working states, and detecting the data receiving performance of a communication handshake frame under different working states;
after the communication handshake frame is transmitted, selecting a working state corresponding to the condition that the data receiving performance of the communication handshake frame in the step-by-step control process firstly meets the preset data receiving performance standard as an optimal working state;
and controlling the single-channel equalization submodule (10), the residual CORDIC conversion submodule (20), the residual frequency offset recovery submodule (30) and the residual phase offset recovery submodule (40) to enter an enabling state correspondingly according to the enabling state of each module corresponding to the optimal working state.
5. The low power consumption DSP apparatus of claim 4, wherein:
the adaptive equalization module (1) is provided with a first enabling switch (12), and the first enabling switch (12) is used for responding to the first enabling signal to control the single-channel equalization submodule (10) to enter an enabling state;
the CORDIC conversion module (2) is provided with a second enabling switch (23), and the second enabling switch (23) is used for responding to a second enabling signal to control the CORDIC second-order conversion submodule (22) to enter an enabling state;
the frequency offset recovery module (3) is configured with a third enable switch (33), and the third enable switch (33) is used for responding to a third enable signal to control the frequency offset recovery secondary submodule (32) to enter an enable state;
the phase deviation recovery module (4) is provided with a fourth enabling switch (43), and the fourth enabling switch (43) is used for responding to a fourth enabling signal to control the phase deviation recovery secondary submodule (42) to enter an enabling state.
6. A method for operating a low power DSP apparatus, as set forth in claim 1, wherein the method comprises the steps of:
placing a low-power-consumption DSP device at an ONU end in a minimum enabling mode, sending a communication handshake frame to the ONU by utilizing an OLT, and detecting the data receiving performance of the communication handshake frame by the ONU;
controlling the single-channel equalization submodule (10), the residual CORDIC conversion submodule (20), the residual frequency offset recovery submodule (30) and the residual phase offset recovery submodule (40) to enter an enabling state step by step, enabling the low-power-consumption DSP device to be in different working states, and detecting the data receiving performance of the communication handshake frame under different working states;
after the communication handshake frame is transmitted, selecting a working state corresponding to the condition that the data receiving performance of the communication handshake frame in the step-by-step control process firstly meets the preset data receiving performance standard as an optimal working state;
and controlling the single-channel equalization submodule (10), the residual CORDIC conversion submodule (20), the residual frequency offset recovery submodule (30) and the residual phase offset recovery submodule (40) to enter an enabling state correspondingly according to the enabling state of each module corresponding to the optimal working state.
7. The method of operating a low power consumption DSP apparatus of claim 6, wherein:
when only the MIMO equalizing submodule (11) of the self-adaptive equalizing module (1), the first CORDIC converting submodule (20) of the CORDIC converting module (2), the first frequency offset recovery submodule (30) of the frequency offset recovery module (3) and the first phase offset recovery submodule (40) of the phase offset recovery module (4) work, the low-power-consumption DSP device is in a minimum enabling mode;
and when the single-channel equalization submodule (10), the residual CORDIC conversion submodule (20), the residual frequency offset recovery submodule (30) and the residual phase offset recovery submodule (40) are all in an enabling state, the low-power-consumption DSP device is in a maximum enabling mode.
8. The method of operating a low power consumption DSP apparatus of claim 6, wherein said method further comprises the steps of:
controlling the single-channel equalization submodule (10) into an enabling state by using a first enabling switch (12);
controlling the rest CORDIC conversion submodules (20) to enter an enabling state by using a second enabling switch (23);
controlling the remaining frequency offset recovery submodule (30) to enter an enabled state by using a third enable switch (33);
and controlling the rest of the phase deviation recovery submodules (40) to enter an enabling state by using a fourth enabling switch (43).
9. A method for operating a low power DSP apparatus as claimed in claim 4, the method comprising the steps of:
placing a low-power-consumption DSP device at an ONU end into a minimum enabling mode, sending a communication handshake frame to the ONU by utilizing the OLT, detecting the data receiving performance of the communication handshake frame by the ONU,
controlling the single-channel equalization submodule (10), the CORDIC second-stage transformation submodule (22), the frequency offset recovery second-stage submodule (32) and the phase offset recovery second-stage submodule (42) to enter an enabling state step by step, enabling the low-power-consumption DSP device to be in different working states, and simultaneously detecting the data receiving performance of the communication handshake frame in different working states;
after the communication handshake frame is transmitted, selecting a working state corresponding to the condition that the data receiving performance of the communication handshake frame in the step-by-step control process firstly meets the preset data receiving performance standard as an optimal working state;
and controlling the single-channel equalization submodule (10), the CORDIC secondary transformation submodule (22), the frequency offset recovery secondary submodule (32) and the phase offset recovery secondary submodule (42) to correspondingly enter an enabling state according to the enabling state of each module corresponding to the optimal working state.
10. The method of operating a low power consumption DSP apparatus of claim 9, wherein said method further comprises the steps of:
controlling the single-channel equalization submodule (10) into an enabling state by using a first enabling switch (12);
controlling the CORDIC second-order transformation submodule (22) to enter an enabling state by using a second enabling switch (23);
controlling the frequency offset recovery secondary submodule (32) to enter an enabling state by using a third enabling switch (33);
and controlling the phase deviation recovery secondary submodule (42) to enter an enabling state by using a fourth enabling switch (43).
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