CN111082786B

CN111082786B - Power circuit and driving circuit

Info

Publication number: CN111082786B
Application number: CN201910262081.5A
Authority: CN
Inventors: 杨长暻
Original assignee: Anchorage Semiconductor Co ltd
Current assignee: Anchorage Semiconductor Co ltd
Priority date: 2018-10-22
Filing date: 2019-04-02
Publication date: 2024-03-29
Anticipated expiration: 2039-04-02
Also published as: TW202017296A; TWI691157B; CN111082786A

Abstract

A power circuit and a driving circuit, wherein the power circuit comprises a power transistor and a driving circuit. The power transistor extracts power current to the ground terminal according to the driving voltage of the driving node. The driving circuit includes a driver including an upper bridge transistor, a lower bridge transistor, and an upper bridge driver. The upper bridge transistor supplies a low voltage to the driving node according to an upper bridge voltage. The lower bridge transistor couples the driving node to the ground terminal according to the control signal. The upper bridge driver includes a plurality of N-type transistors, and provides a high voltage to an upper bridge node according to a control signal. The high voltage exceeds the gate operating voltages of the plurality of N-type transistors of the driving circuit.

Description

Power circuit and driving circuit

Technical Field

The present invention relates to a driving circuit for gallium nitride (GaN) power elements.

Background

In a power circuit, it is often necessary to boost the supply voltage to a higher voltage with a charge pump to drive the power transistor. Fig. 1 shows a general power circuit. As shown in fig. 1, the power circuit 100 includes a power transistor 110, an upper bridge transistor 121, and a lower bridge transistor 122. The upper bridge transistor 121 and the lower bridge transistor 122 are used for generating a driving voltage VD at the driving node ND, so that the power transistor 110 draws a power current IP according to the driving voltage VD.

Since the driving voltage VD reaches the operating voltage VS, the upper bridge voltage VHS exceeds the operating voltage VS to fully turn on the upper bridge transistor 121, so that the upper bridge voltage VHS exceeds the operating voltage VS to ensure that the upper bridge transistor is fully turned on.

Disclosure of Invention

In view of this, the present invention proposes a power circuit comprising: a power transistor and a driving circuit. The power transistor extracts a power current to a ground terminal according to a driving voltage of a driving node. The driving circuit comprises a driver. The driver includes an upper bridge transistor, a lower bridge transistor and an upper bridge driver. The upper bridge transistor provides a low voltage to the driving node according to an upper bridge voltage of an upper bridge node. The lower bridge transistor couples the driving node to the ground terminal according to a control signal. The upper bridge driver comprises a plurality of N-type transistors, and provides a high voltage to the upper bridge node according to the control signal, wherein the high voltage exceeds a gate operating voltage of the N-type transistors of the driving circuit.

The invention further provides a driving circuit for driving a power transistor, wherein the power transistor draws a power current to a ground terminal according to a driving voltage of a driving node. The driving circuit comprises a driver. The driver includes an upper bridge transistor, a lower bridge transistor and an upper bridge driver. The upper bridge transistor provides a low voltage to the driving node according to an upper bridge voltage of an upper bridge node. The lower bridge transistor couples the driving node to the ground terminal according to a control signal. The upper bridge driver comprises a plurality of N-type transistors, and provides a high voltage to the upper bridge node according to the control signal, wherein the high voltage exceeds a gate operating voltage of the N-type transistors of the driving circuit.

Drawings

FIG. 1 is a schematic diagram showing a general power circuit;

FIG. 2 is a block diagram showing a power circuit according to an embodiment of the invention;

FIG. 3 is a block diagram illustrating a power circuit according to an embodiment of the invention;

FIG. 4 is a circuit diagram showing the driver of FIG. 3 according to another embodiment of the present invention;

FIG. 5 is a circuit diagram showing the driver of FIG. 3 according to another embodiment of the present invention;

FIG. 6 is a circuit diagram showing the driver of FIG. 3 according to another embodiment of the present invention;

FIG. 7 is a circuit diagram illustrating the first voltage regulator of FIG. 3 according to an embodiment of the present invention;

FIG. 8 is a circuit diagram illustrating the second voltage regulator of FIG. 3 according to an embodiment of the present invention;

FIG. 9 is a circuit diagram showing the under-voltage lockout circuit of FIG. 3 according to an embodiment of the present invention;

fig. 10 is a block diagram showing a power circuit according to another embodiment of the present invention;

FIG. 11 is a circuit diagram illustrating the driver of FIG. 10 according to an embodiment of the present invention;

FIG. 12 is a circuit diagram illustrating the driver of FIG. 11 according to an embodiment of the present invention;

FIG. 13 is a circuit diagram showing the driver of FIG. 11 according to another embodiment of the present invention; and

Fig. 14 is a circuit diagram showing the driver of fig. 11 according to another embodiment of the present invention.

Reference numerals illustrate:

100. 200, 300, 1000 power circuit

110. 10 power transistor

121 upper bridge transistor

122 lower bridge transistor

220. 320, 1020 driving circuit

221 voltage stabilizer

222. 323, 400, 500, 600, 1023, 1100, 1200, 1300, 1400 drivers

321. 700 first voltage stabilizer

322. 800, 1022 second voltage stabilizer

324. 900, 1024 under-voltage locking circuit

410. 510, 610, 1110, 1210, 1310, 1410 upper bridge driver

520. 620, 1320, 1420 first predriver

630. 1430 second predriver

640. 1440 third predriver

1111. 1211, 1311, 1411 differential amplifier

ND driving node

VD drive voltage

IP power current

VS operation voltage

VHS upper bridge voltage

VDD supply voltage

VH high voltage

VL low voltage

SC control signal

SCB inverted control signal

MHS upper bridge transistor

MLS (Metal-insulator-semiconductor) lower bridge transistor

HSD upper bridge driver

INV inverter

ME1 first normally-off transistor

ME2 second normally-off transistor

ME3 third normally-off transistor

ME4 fourth normally-off transistor

ME5 fifth normally-off transistor

ME6 sixth normally-off transistor

ME7 seventh normally-off transistor

ME8 eighth normally-off transistor

ME9 ninth normally-off transistor

ME10 tenth normally-off transistor

ME11 eleventh normally-off transistor

ME12 twelfth normally-off transistor

ME13 thirteenth normally-off transistor

ME14 fourteenth normally-off transistor

ME15 fifteenth normally-off transistor

ME16 sixteenth normally-off transistor

ME17 seventeenth normally-off transistor

ME18 eighteenth normally-off transistor

ME19 nineteenth normally-off transistor

ME20 twentieth normally-off transistor

ME21 twenty-first normally-off transistor

MD1 first normally-on transistor

MD2 second normally-on transistor

MD3 third normally-on transistor

MD4 fourteenth normally-on transistor

MD5 fifth normally-on transistor

MD6 sixth normally-on transistor

MD7 seventh normally-on transistor

MD8 eighth normally-on transistor

MR1 first voltage-stabilizing normally-off transistor

MR2 second voltage-stabilizing normally-off transistor

MR3 third voltage-stabilizing normally-off transistor

MR4 fourth voltage-stabilizing normally-off transistor

MR5 fifth voltage-stabilizing normally-off transistor

MR6 sixth voltage-stabilizing normally-off transistor

MR7 seventh voltage-stabilizing normally-off transistor

MR8 eighth voltage-stabilizing normally-off transistor

MA1 first amplifier normally-off transistor

MA2 second amplifier normally-off transistor

MA3 third amplifier normally-off transistor

MA4 fourth amplifier normally-off transistor

MA5 fifth amplifier normally-off transistor

MA6 sixth amplifier normally-off transistor

MA7 seventh amplifier normally-off transistor

MA8 eighth amplifier normally-off transistor

MA9 ninth amplifier normally-off transistor

MA10 tenth amplifier normally-off transistor

MA11 eleventh amplifier normally-off transistor

R1 first resistor

R2 second resistor

R3 third resistor

R4 fourth resistor

R5 fifth resistor

R6 sixth resistor

R7 seventh resistor

R8 eighth resistor

R9 ninth resistor

RX undervoltage resistor

IC1 first current source

IC2 second current source

IA1 amplifier current source

I1 first current

I2 second current

IB bias current

D1 first voltage divider

D2 second voltage divider

D3 third voltage divider

CL1 first clamping circuit

CL2 second clamping circuit

CL3 third clamping circuit

NH upper bridge node

NI1 first internal node

NI2 second internal node

NI3 third internal node

SI1 first internal Signal

SI2 second internal Signal

SI3 third internal Signal

SUVLO under-voltage lock signal

N1 first node

N2 second node

N3 third node

VREF reference voltage

NR1 first voltage stabilizing node

NR2 second voltage stabilizing node

NR3 third voltage stabilizing node

NR4 fourth voltage stabilizing node

NR5 fifth voltage stabilizing node

NU1 first undervoltage node

NU2 second undervoltage node

NU3 third undervoltage node

NU4 fourth undervoltage node

NUVLO undervoltage locking node

NIP positive input node

NIN negative input node

NO output node

NA1 first amplifier node

NA2 second amplifier node

NA3 third amplifier node

VFB1 first feedback voltage

VFB2 second feedback voltage

VDV divided voltage

Detailed Description

The following description is of embodiments of the invention. It is intended that the general principles of the invention be defined and not in limitation, but that the scope of the invention is defined by the claims.

It is noted that the following disclosure may provide numerous embodiments or examples of different features for practicing the invention. The specific examples and arrangements of components are set forth below in order to provide a brief description of the principles of the present invention and are not intended to limit the scope of the invention. In addition, the following description may repeat use of the same reference numerals and/or letters in the various examples. However, repeated use is for purposes of providing a simplified and clear illustration only and is not intended to limit the relationship between the various embodiments and/or configurations discussed below. Furthermore, descriptions of one feature being connected to, coupled to, and/or formed on another feature described in the specification below may actually be comprised of a multitude of different embodiments, comprising the feature in direct contact, or other additional features being formed between the features, etc., so that the features are not in direct contact.

Fig. 2 is a block diagram showing a power circuit according to an embodiment of the present invention. As shown in fig. 2, the power circuit 200 includes a power transistor 10 and a driving circuit 220. According to an embodiment of the present invention, the power transistor 10 is a gallium nitride transistor.

The driving circuit 220 includes a voltage regulator 221 and a driver 222. The voltage regulator is used for reducing the supply voltage VDD to the low voltage VL. According to an embodiment of the present invention, the supply voltage VDD exceeds the gate operation voltages of all the transistors of the driving circuit 220, such that the voltage regulator 221 has to step down the supply voltage VDD to a low voltage VL, wherein the low voltage VL is equal to the gate operation voltages of all the transistors of the driving circuit 220.

As shown in fig. 2, the driver 222 includes an upper bridge transistor MHS, a lower bridge transistor MLS, an upper bridge driver HSD, and an inverter INV. According to an embodiment of the present invention, the upper bridge transistor MHS corresponds to the upper bridge transistor 121 of fig. 1, and the lower bridge transistor MLS corresponds to the lower bridge transistor 122 of fig. 1.

The upper bridge driver HSD is powered by a high voltage VH to boost the high logic level (level) of the control signal SC to the high voltage VH so as to fully turn on the upper bridge transistor MHS. According to an embodiment of the invention, the high voltage VH exceeds the low voltage VL.

According to an embodiment of the invention, the high voltage VH exceeds the supply voltage VDD. According to another embodiment of the present invention, the high voltage VH is converted from the supply voltage VDD. The lower bridge transistor MLS pulls down the driving voltage VD to the ground level according to the control signal SC.

Fig. 3 is a block diagram showing a power circuit according to an embodiment of the present invention. As shown in fig. 3, the power circuit 300 includes the power transistor 10 and the driving circuit 320, wherein the power circuit 300 is an embodiment of the power circuit 200 of fig. 2, and is not limited thereto in any way. According to an embodiment of the invention, the power transistor is a gallium nitride transistor.

The driving circuit 320 includes a first voltage regulator 321, a second voltage regulator 322, a driver 323, and an under-voltage lockout (UVLO) circuit 324. The first voltage regulator 321 is configured to step down the supply voltage VDD to the high voltage VH, and the second voltage regulator 322 is configured to step down the supply voltage VDD to the low voltage VL. According to an embodiment of the present invention, the low voltage VL is lower than the high voltage VH, and the low voltage VL and the high voltage VH are both lower than the supply voltage VDD.

The driver 323 is powered by the high voltage VH and the low voltage VL, and generates a driving voltage VD at the driving node ND according to the control signal SC, so that the power transistor 10 draws the power current IP according to the driving voltage VD.

According to an embodiment of the invention, the driver 323 includes the upper bridge transistor 121 and the lower bridge transistor 122 of fig. 1, the low voltage VL corresponds to the operating voltage VS of fig. 1, and the high voltage VH is used to drive the upper bridge transistor MHS, which will be described in detail below.

The undervoltage lockout circuit 324 is powered by a low voltage VL to detect the supply voltage VDD. When the supply voltage VDD is lower than the threshold value, the under-voltage lock circuit 324 pulls down the control signal SC to the ground level, disabling the driver 323.

According to an embodiment of the present invention, the driving circuit 320 may further include a level shifter for converting the control signal SC ranging from the supply voltage VDD to the ground level into the control signal SC ranging from the low voltage VL to the ground level. For simplicity of explanation, the level shifter is omitted herein, and in the following paragraphs, the control signal SC ranging from the low voltage VL to the ground level will be explained.

Fig. 4 is a circuit diagram showing the driver of fig. 3 according to another embodiment of the present invention. As shown in fig. 4, the driver 400 includes an upper bridge transistor MHS, a lower bridge transistor MLS, an upper bridge driver 410, and an inverter INV. According to an embodiment of the present invention, the upper bridge transistor MHS corresponds to the upper bridge transistor 120 of fig. 1, and the lower bridge transistor MLS corresponds to the lower bridge transistor 122 of fig. 1.

The upper bridge driver 410 includes a first normally-off transistor ME1, a second normally-off transistor ME2, and a first normally-on transistor MD1. The first normally-off transistor ME1 includes a source terminal coupled to the upper bridge node NH, a gate terminal receiving the control signal SC, and a drain terminal supplied by the high voltage VH.

The second normally-off transistor ME2 includes a source terminal coupled to the ground terminal, a gate terminal receiving the inverted control signal SCB generated by the inverter INV, and a drain terminal coupled to the upper bridge node NH. According to an embodiment of the present invention, the gate terminal of the lower bridge transistor MLS receives the inverted control signal SCB.

The first normally-on transistor MD1 includes a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the upper bridge node NH, and the drain terminal is supplied by the high voltage VH. According to an embodiment of the present invention, the first normally-on transistor MD1 is used for providing the high voltage VH to the upper bridge node NH, and the first normally-off transistor ME1 is used for increasing the upper bridge voltage VHs to reach the high voltage VH.

Fig. 5 is a circuit diagram showing the driver of fig. 3 according to another embodiment of the present invention. As shown in fig. 5, the driver 500 includes an upper bridge transistor MHS, a lower bridge transistor MLS, an upper bridge driver 510, a first pre-driver 520, and an inverter INV, wherein the driver 500 is configured to drive the power transistor 10 to draw the power current IP. In accordance with an embodiment of the present invention, the upper bridge driver 510 corresponds to the upper bridge driver 410 of fig. 4.

The first pre-driver 520 generates a first internal signal SI1 at a first internal node NI1 according to the control signal SC and the inverted control signal SCB, wherein the first pre-driver 520 includes a third normally-off transistor ME3, a fourth normally-off transistor ME4, a fifth normally-off transistor ME5, a second normally-on transistor MD2, and a sixth normally-off transistor ME6.

The third normally-off transistor ME3 includes a source terminal coupled to the first internal node NI1, a gate terminal coupled to the first node N1, and a drain terminal powered by the low voltage VL.

The fourth normally-off transistor ME4 includes a source terminal coupled to the ground terminal, a gate terminal receiving the control signal SC, and a drain terminal coupled to the first internal node NI1.

The fifth normally-off transistor ME5 includes a source terminal coupled to the first node N1, a gate terminal receiving the inverted control signal SCB generated by the inverter INV, and a drain terminal supplied by the high voltage VH.

The second normally-on transistor MD2 includes a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are coupled to the first node N1, and the drain terminal is powered by the high voltage VH. According to an embodiment of the present invention, the second normally-on transistor MD2 is used to enhance the current driving capability of the high voltage VH provided at the first node N1.

According to an embodiment of the present invention, the second normally-on transistor MD2 is used for providing the high voltage VH to the first node N1, and the fifth normally-off transistor ME5 is used for increasing the speed of the first node N1 reaching the high voltage VH.

The sixth normally-off transistor ME6 includes a source terminal coupled to the ground terminal, a gate terminal receiving the control signal SC, and a drain terminal coupled to the first node N1.

According to an embodiment of the invention, since the first internal signal SI1 is an inverse of the control signal SC, the upper bridge driver 510 generates the upper bridge voltage VHS at the upper bridge node NH according to the control signal SC and the first internal signal SI 1.

Fig. 6 is a circuit diagram showing the driver of fig. 3 according to another embodiment of the present invention. As shown in fig. 6, the driver 600 includes an upper bridge transistor MHS, a lower bridge transistor MLS, an upper bridge driver 610, a first pre-driver 620, a second pre-driver 630, a third pre-driver 640, and an inverter INV. The driver 600 generates a driving voltage VD at the driving node ND, so that the power transistor 10 draws the power current IP according to the driving voltage VD.

In accordance with an embodiment of the present invention, the upper bridge driver 610 corresponds to the upper bridge driver 410 of fig. 4. According to an embodiment of the present invention, the first pre-driver 620 corresponds to the first pre-driver 520 of fig. 5, wherein the second internal signal SI2 and the third internal signal SI3 of fig. 6 correspond to the control signal SC and the inverted control signal SCB of fig. 5, respectively.

The second pre-driver 630 generates a second internal signal SI2 at a second internal node NI2 according to the third internal signal SI3 and the control signal SC, wherein the second pre-driver 630 includes a seventh normally-off transistor ME7, an eighth normally-off transistor ME8, a ninth normally-off transistor ME9, a third normally-on transistor MD3, and a tenth normally-off transistor ME10.

The seventh normally-off transistor ME7 includes a source terminal coupled to the second internal node NI2, a gate terminal coupled to the second node N2, and a drain terminal powered by the low voltage VL.

The eighth normally-off transistor ME8 includes a source terminal coupled to the ground terminal, a gate terminal receiving the third internal signal SI3, and a drain terminal coupled to the second internal node NI2.

The ninth normally-off transistor ME9 includes a source terminal coupled to the second node N2, a gate terminal receiving the third internal signal SI3, and a drain terminal powered by the high voltage VH.

The third normally-on transistor MD3 includes a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the second node N2, and the drain terminal is powered by the high voltage VH. According to an embodiment of the present invention, the third normally-on transistor MD3 is used for providing the high voltage VH to the second node N2, and the ninth normally-off transistor ME9 is used for increasing the speed of the voltage of the second node N2 reaching the high voltage VH.

The tenth normally-off transistor ME10 includes a source terminal coupled to the ground terminal, a gate terminal receiving the third internal signal SI3, and a drain terminal coupled to the second node N2.

The third pre-driver 640 is configured to generate a third internal signal SI3 at a third internal node NI3 according to the control signal SC and the inverted control signal SCB generated by the inverter INV. The third predriver 640 includes an eleventh normally-off transistor ME11, a twelfth normally-off transistor ME12, a thirteenth normally-off transistor ME13, a fourteenth normally-on transistor MD4, and a fourteenth normally-off transistor ME14.

The eleventh normally-off transistor ME11 includes a source terminal coupled to the third internal node NI3, a gate terminal coupled to the third node N3, and a drain terminal powered by the low voltage VL.

The twelfth normally-off transistor ME12 includes a source terminal coupled to the ground terminal, a gate terminal receiving the control signal SC, and a drain terminal coupled to the third internal node NI3.

The thirteenth normally-off transistor ME13 includes a source terminal coupled to the third node N3, a gate terminal receiving the inverted control signal SCB generated by the inverter INV, and a drain terminal supplied by the high voltage VH.

The fourth normally-on transistor MD4 includes a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the third node N3, and the drain terminal is powered by the high voltage VH. According to an embodiment of the present invention, the fourth normally-on transistor MD4 is used for providing the high voltage VH to the third node N3, and the thirteenth normally-off transistor ME13 is used for increasing the voltage of the third node N3 to reach the speed of the high voltage VH.

The fourteenth normally-off transistor ME14 includes a source terminal coupled to the ground terminal, a gate terminal receiving the control signal SC, and a drain terminal coupled to the third node N3.

According to other embodiments of the present invention, the driver 500 of fig. 5 or the driver 600 of fig. 6 may be connected in series with any even number of pre-drivers identical to the first pre-driver, the second pre-driver and/or the third pre-driver of fig. 5 and 6, so as to facilitate enhancing the driving capability of the control signal SC.

Fig. 7 is a circuit diagram showing the first voltage regulator of fig. 3 according to an embodiment of the invention. As shown in fig. 7, the first voltage regulator 700 includes a first voltage-stabilizing normally-closed transistor MR1, a first resistor R1, a second voltage-stabilizing normally-closed transistor MR2, a second resistor R2, a first current source IC1, a third voltage-stabilizing normally-closed transistor MR3, a third resistor R3, a fourth voltage-stabilizing normally-closed transistor MR4, and a first voltage divider D1.

The first voltage-stabilizing normally-off transistor MR1 includes a source terminal, a gate terminal and a drain terminal, wherein the gate terminal receives the reference voltage VREF, the source terminal is coupled to the first voltage-stabilizing node NR1, and the drain terminal is coupled to the second voltage-stabilizing node NR2.

According to an embodiment of the present invention, the reference voltage VREF may be generated by a bandgap (bandgap) circuit. According to another embodiment of the present invention, the reference voltage VREF may divide the supply voltage VDD by a factor. The first resistor R1 is coupled between the supply voltage VDD and the second voltage stabilizing node NR2.

The second voltage-stabilizing normally-off transistor MR2 includes a source terminal, a gate terminal and a drain terminal, wherein the gate terminal receives the first feedback voltage VFB1, and the source terminal is coupled to the first voltage-stabilizing node NR1. The second resistor R2 is coupled between the supply voltage and the drain terminal of the second voltage stabilizing normally-off transistor MR 2. The first current source IC1 draws a first current I1 from the first voltage stabilizing node NR1 to ground.

The third voltage-stabilizing normally-off transistor MR3 includes a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the second voltage-stabilizing node NR2, the source terminal is coupled to the ground terminal, and the drain terminal is coupled to the third voltage-stabilizing node NR3. The third resistor R3 is coupled between the supply voltage VDD and the third voltage stabilizing node NR3.

The fourth voltage-stabilizing normally-off transistor MR4 includes a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the third voltage-stabilizing node NR3, the source terminal generates the high voltage VH, and the drain terminal is supplied by the supply voltage VDD.

The first voltage divider D1 divides the high voltage VH by a first coefficient to generate a first feedback voltage VFB1. According to an embodiment of the present invention, the first voltage divider D1 includes two resistors connected in series, such that the first coefficient is determined by the ratio of the resistance values of the two resistors connected in series.

According to an embodiment of the present invention, the first voltage regulator 700 is configured to maintain the first feedback voltage VFB1 equal to the reference voltage VREF, such that the high voltage VH is equal to the reference voltage VREF multiplied by a first coefficient determined by the first voltage divider D1.

According to an embodiment of the present invention, the first voltage regulator 700 further includes a first clamping circuit CL1. The first clamping circuit CL1 is configured to clamp a voltage across the gate terminal and the source terminal of the fourth voltage-stabilizing normally-off transistor MR4, such that the voltage across the gate terminal and the source terminal of the fourth voltage-stabilizing normally-off transistor MR4 is smaller than a breakdown voltage of the fourth voltage-stabilizing normally-off transistor MR 4.

According to some embodiments of the present invention, the first clamping circuit CL1 may include a plurality of diodes connected in series or a plurality of transistors connected in series and coupled in diode form, such that a voltage across the gate terminal and the source terminal of the fourth voltage stabilizing normally-off transistor MR4 does not exceed a forward turn-on voltage of the diodes connected in series or the transistors connected in series and coupled in diode form.

Fig. 8 is a circuit diagram showing the second voltage regulator of fig. 3 according to an embodiment of the invention. As shown in fig. 8, the second voltage regulator 800 includes a fifth voltage-stabilizing normally-closed transistor MR5, a fourth resistor R4, a sixth voltage-stabilizing normally-closed transistor MR6, a fifth resistor R5, a second current source IC2, a seventh voltage-stabilizing normally-closed transistor MR7, a sixth resistor R6, an eighth voltage-stabilizing normally-closed transistor MR8, and a second voltage divider D2.

The fifth voltage-stabilizing normally-off transistor MR5 includes a source terminal, a gate terminal and a drain terminal, wherein the gate terminal receives the reference voltage VREF, the source terminal is coupled to the fourth voltage-stabilizing node NR4, and the drain terminal is coupled to the fifth voltage-stabilizing node NR5. The fourth resistor R4 is coupled between the supply voltage VDD and the second voltage stabilizing node NR 2.

The sixth voltage-stabilizing normally-off transistor MR6 includes a source terminal, a gate terminal and a drain terminal, wherein the gate terminal receives the second feedback voltage VFB2, and the source terminal is coupled to the fourth voltage-stabilizing node NR4. The fifth resistor R5 is coupled between the supply voltage VDD and the sixth voltage stabilizing normally-off transistor MR 6. The second current source IC2 draws the second current I2 from the fourth voltage stabilizing node NR4 to the ground.

The seventh voltage-stabilizing normally-off transistor MR7 includes a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the fifth voltage-stabilizing node NR5, the source terminal is coupled to the ground terminal, and the drain terminal is coupled to the sixth voltage-stabilizing node NR6. The sixth resistor R6 is coupled to the supply voltage VDD and the sixth voltage stabilizing node NR6.

The eighth voltage-stabilizing normally-off transistor MR8 includes a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the sixth voltage-stabilizing node NR6, the source terminal generates the low voltage VL, and the drain terminal is supplied by the supply voltage VDD.

The second voltage divider D2 divides the low voltage VL by a second coefficient to generate a second feedback voltage VFB2. According to an embodiment of the present invention, the second voltage divider D2 includes two resistors connected in series, such that the second coefficient is determined by the ratio of the resistance values of the two resistors connected in series.

According to an embodiment of the present invention, the second voltage regulator 800 is configured to maintain the second feedback voltage VFB2 equal to the reference voltage VREF, such that the low voltage VL is equal to the reference voltage VREF multiplied by a second coefficient determined by the second voltage divider D2.

According to an embodiment of the present invention, the second voltage regulator 800 further includes a second clamping circuit CL2. The second clamping circuit CL2 is configured to clamp a voltage across the eighth voltage-stabilizing normally-off transistor MR8 between the gate terminal and the source terminal, such that the voltage across the eighth voltage-stabilizing normally-off transistor MR8 between the gate terminal and the source terminal is lower than the breakdown voltage of the eighth voltage-stabilizing normally-off transistor MR 8.

According to some embodiments of the present invention, the second clamping circuit CL2 may include a plurality of diodes connected in series or a plurality of transistors connected in series and coupled in diode form, such that a voltage across the gate terminal to the source terminal of the eighth voltage stabilizing normally-off transistor MR8 does not exceed a forward turn-on voltage of the diodes connected in series or the transistors connected in series and coupled in diode form.

FIG. 9 is a circuit diagram showing the under-voltage lock-out circuit of FIG. 3 according to an embodiment of the present invention. As shown in fig. 9, the under-voltage lock circuit 900 includes a third voltage divider D3, a fifth normally-on transistor MD5, a fifteenth normally-on transistor ME15, a sixteenth normally-on transistor ME16, an under-voltage resistor RX, a seventeenth normally-on transistor ME17, an eighteenth normally-on transistor ME18, a nineteenth normally-on transistor ME19, a twentieth normally-on transistor ME20, and a twenty first normally-on transistor ME21.

The third voltage divider D3 divides the supply voltage VDD by a third coefficient to generate a divided voltage VDV. According to an embodiment of the present invention, the third voltage divider D3 is composed of a plurality of resistors connected in series. According to another embodiment of the present invention, the third voltage divider D3 is composed of a plurality of diodes or a plurality of transistor series-connected diodes.

The fifth normally-on transistor MD5 includes a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are coupled to the first under-voltage node NU1, and the drain terminal is powered by the low voltage VL.

The fifteenth normally-off transistor ME15 includes a source terminal coupled to the ground terminal, a gate terminal receiving the divided voltage VDV, and a drain terminal coupled to the first under-voltage node NU1.

The sixteenth normally-off transistor ME16 includes a source terminal coupled to the second under-voltage node NU2, a gate terminal coupled to the first under-voltage node NU1, and a drain terminal coupled to the third under-voltage node NU3. The undervoltage resistor RX is coupled between the low voltage VL and the third undervoltage node NU3.

The seventeenth normally-off transistor ME17 includes a source terminal coupled to the ground terminal, a gate terminal coupled to the first under-voltage node NU1, and a drain terminal coupled to the second under-voltage node NU2.

The eighteenth normally-off transistor ME18 includes a source terminal coupled to the second under-voltage node NU2, a gate terminal coupled to the third under-voltage node NU3, and a drain terminal coupled to the fourth under-voltage node NU4.

The nineteenth normally-off transistor ME19 includes a source terminal coupled to the under-voltage-locked node NUVLO, a gate terminal coupled to the fourth under-voltage node NU4, and a drain terminal supplied by the low voltage VL.

The twenty-first normally-off transistor ME20 includes a source terminal coupled to the ground terminal, a gate terminal coupled to the third under-voltage node NU3, and a drain terminal coupled to the under-voltage latch node NUVLO. The under-voltage lock signal SUVLO is generated at the under-voltage lock node NUVLO.

The twenty-first normally-off transistor ME21 includes a source terminal coupled to the ground terminal, a gate terminal coupled to the under-voltage-lock node NUVLO, and a drain terminal coupled to the control signal SC. The twenty-first normally-off transistor ME21 pulls down the control signal SC to the ground level according to the under-voltage lock signal SUVLO.

According to an embodiment of the present invention, it is assumed that the third coefficient generated by the third voltage divider D3 is 2/7, the threshold voltage of the fifteenth normally-closed transistor ME15 is 2V, and the under-voltage lock signal SUVLO is at a low logic level when the supply voltage VDD exceeds 7V. Thus, the control signal SC drives the driver 323 of fig. 3 to trigger the power transistor 10 to draw the power current IP. The above-described values are for illustration only and are not intended to be limiting in any way.

Fig. 10 is a block diagram showing a power circuit according to another embodiment of the present invention. The power circuit 1000 is another embodiment of the power circuit 200 of fig. 2, wherein the power circuit 100 includes the power transistor 10 and the driving circuit 1020. According to an embodiment of the present invention, the power transistor 10 is a gallium nitride transistor.

As shown in fig. 10, the driving circuit 1020 includes a second voltage regulator 1022, a driver 1023, and an under-voltage lock circuit 1024. Comparing fig. 10 with fig. 3, the driver 1023 of fig. 10 is supplied with the supply voltage VDD and the low voltage VL generated by the second voltage regulator 1022. In other words, the high voltage VH of fig. 2 is directly supplied by the supply voltage VDD of fig. 10. According to an embodiment of the present invention, the second voltage stabilizer 1022 corresponds to the second voltage stabilizer 322 of fig. 3, and the under-voltage locking circuit 1024 corresponds to the under-voltage locking circuit 324 of fig. 3. According to an embodiment of the present invention, the under-voltage lockout circuit 900 of FIG. 9 is shown as under-voltage lockout circuit 1024 of FIG. 10.

Fig. 11 is a circuit diagram showing the driver of fig. 10 according to an embodiment of the present invention. As shown in fig. 11, the driver 1100 includes an upper bridge transistor MHS, a lower bridge transistor MLS, an upper bridge driver 1110, and an inverter INV, wherein the upper bridge driver 1110 includes a differential amplifier 1111.

Differential amplifier 1111 includes a positive input node NIP, a negative input node NIN, and an output node NO. The positive input node NIP receives the control signal SC and the negative input node NIN is coupled to the driving node ND. The differential amplifier 1111 compares the control signal SC of the positive input node NIP with the driving voltage VD of the driving node ND, and generates the upper bridge voltage VHS at the output node NO, so that the upper bridge transistor MHS is fully turned on according to the upper bridge voltage VHS. When the upper bridge transistor MHS is fully on, the driving voltage VD is equal to the low voltage VL.

Fig. 12 is a circuit diagram showing the driver of fig. 11 according to an embodiment of the present invention. As shown in fig. 12, the driver 1200 includes an upper bridge transistor MHS, a lower bridge transistor MLS, an upper bridge driver 1210, and an inverter INV, wherein the upper bridge driver 1210 includes a differential amplifier 1211. Comparing fig. 12 with fig. 10, the differential amplifier 1211 corresponds to the differential amplifier 1011.

The differential amplifier 1211 includes a first amplifier normally-off transistor MA1, a seventh resistor R7, a second amplifier normally-off transistor MA2, an eighth resistor R8, an amplifier current source IA1, a third amplifier normally-off transistor MA3, a ninth resistor R9, a fourth amplifier normally-off transistor MA4, and a fifth amplifier normally-off transistor MA5.

The first amplifier normally-off transistor MA1 includes a source terminal, a gate terminal and a drain terminal, wherein the gate terminal receives the control signal SC, the source terminal is coupled to the first amplifier node NA1, and the drain terminal is coupled to the second amplifier node NA2. The seventh resistor R7 is coupled between the supply voltage VDD and the second amplifier node NA2.

The second amplifier normally-off transistor MA2 includes a source terminal coupled to the driving node ND, a gate terminal coupled to the first amplifier node NA1, and a drain terminal. The eighth resistor R8 is coupled to the supply voltage VDD and the drain terminal of the second amplifier normally-off transistor MA 2. The amplifier current source IA1 draws a bias current IB from the first amplifier node NA1 to the ground.

The third amplifier normally-off transistor MA3 includes a source terminal, a gate terminal, and a drain terminal, wherein the gate terminal is coupled to the second amplifier node NA2, the source terminal is coupled to the ground terminal, and the drain terminal is coupled to the third amplifier node NA3. The ninth resistor R9 is coupled to the supply voltage VDD and the third amplifier node NA3.

The fourth amplifier normally-off transistor MA4 includes a source terminal coupled to the third amplifier node NA3, a gate terminal coupled to the amplifier node NO, and a drain terminal supplied by the supply voltage VDD. The third amplifier node NA3 is coupled to the upper bridge node NH.

The fifth amplifier normally-off transistor MA5 includes a source terminal receiving the inverted control signal SCB, a gate terminal coupled to the ground terminal, and a drain terminal coupled to the output node NO of the differential amplifier 1211.

According to an embodiment of the present invention, the differential amplifier 1211 further includes a third clamp circuit CL3. The third clamping circuit CL3 is used for clamping the voltage across the gate terminal and the source terminal of the fourth amplifier normally-off transistor MA4, which is lower than the breakdown voltage of the fourth amplifier normally-off transistor MA 4. Therefore, the fourth amplifier normally-off transistor MA4 is protected from exceeding the breakdown voltage by the third clamp circuit CL3.

According to some embodiments of the present invention, the third clamping circuit CL3 may include a plurality of diodes connected in series or a plurality of transistors connected in series and coupled in diode form, such that a voltage across the gate terminal and the source terminal of the fourth amplifier normally-off transistor MA4 does not exceed a forward turn-on voltage of the plurality of diodes connected in series or the plurality of transistors connected in series and coupled in diode form.

According to an embodiment of the present invention, the control signal SC is at a high voltage level, and the driving voltage VD is at a low voltage level relative to the control signal SC. The first amplifier normally-off transistor MA1 pulls down the voltage of the second amplifier node NA2 such that the third amplifier normally-off transistor MA3 is non-conductive and the ninth resistor R9 pulls up the third amplifier node NA3 to the supply voltage VDD.

Next, the voltage of the third amplifier node NA3 turns on the fourth amplifier normally-off transistor MA4, and the reverse control signal SCB does not turn on the fifth amplifier normally-off transistor MA5. Thus, the differential amplifier 1211 outputs the supply voltage VDD at the output node NO, and turns on the upper bridge transistor MHS.

According to another embodiment of the present invention, the control signal SC is at a low voltage level. Since the reverse control signal SCB is at a high voltage level and turns on the fifth amplifier normally-off transistor MA5 when the control signal SC is at a low voltage level, the output node NO of the differential amplifier 1211 is pulled down to the ground. Thus, the reverse control signal SCB does not turn on the upper bridge transistor MHS and turns on the lower bridge transistor MLS.

Fig. 13 is a circuit diagram showing the driver of fig. 11 according to another embodiment of the present invention. As shown in fig. 13, the driver 1300 includes an upper bridge driver 1310 including a differential amplifier 1311, and a first pre-driver 1320.

According to an embodiment of the present invention, the differential amplifier 1311 is the same as the differential amplifier 1211 of fig. 12. The first pre-driver 1320 generates a first internal signal SI1 at the first internal node according to the control signal SC and the inverted control signal SCB to enhance the driving capability of the control signal SC. The first predriver 1320 includes a sixth amplifier normally-off transistor MA6, a sixth normally-on transistor MD6, and a seventh amplifier normally-off transistor MA7.

The sixth amplifier normally-off transistor MA6 includes a source terminal coupled to the first internal node NI1, a gate terminal receiving the inversion control signal SCB generated by the inverter INV, and a drain terminal supplied by the low voltage VL.

The sixth normally-on transistor MD6 includes a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the first internal node NI1, and the drain terminal is supplied by the low voltage VL. According to an embodiment of the present invention, the sixth normally-on transistor MD6 is used to enhance the current driving capability of the low voltage VL to the first internal node NI 1.

The seventh amplifier normally-off transistor MA7 includes a source terminal coupled to the ground terminal, a gate terminal receiving the control signal SC, and a drain terminal coupled to the first node N1.

Fig. 14 is a circuit diagram showing the driver of fig. 11 according to another embodiment of the present invention. As shown in fig. 14, the driver 1400 includes an upper bridge driver 1410, a first pre-driver 1420, a second pre-driver 1430, and a third pre-driver 1440, wherein the upper bridge driver 1410 includes a differential amplifier 1411. According to an embodiment of the invention, the upper bridge driver 1410 corresponds to the upper bridge driver 1210 of fig. 12, and the differential amplifier 1411 corresponds to the differential amplifier 1211 of fig. 12. According to an embodiment of the present invention, the first pre-driver 1420, the second pre-driver 1430 and the third pre-driver 1440 are used to enhance the driving capability of the control signal SC.

According to another embodiment of the present invention, the first predriver 1420 corresponds to the first predriver 1320 of fig. 13. The second pre-driver 1430 generates the second internal signal SI2 at the second internal node NI2 according to the third internal signal SI3 and the control signal SC. As shown in fig. 14, the second predriver 1430 includes an eighth amplifier normally-off transistor MA8, a seventh normally-on transistor MD7, and a ninth amplifier normally-off transistor MA9.

The eighth amplifier normally-off transistor MA8 includes a source terminal coupled to the second internal node NI2, a gate terminal receiving the control signal SC, and a drain terminal supplied by the low voltage VL.

The seventh normally-on transistor MD7 includes a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the second internal node NI2, and the drain terminal is supplied by the low voltage VL. According to an embodiment of the present invention, the first normally-on transistor MD7 is used for providing the low voltage VL to the second internal node NI2, and the eighth amplifier normally-off transistor MA8 is used for increasing the speed of the voltage of the second internal node NI2 reaching the low voltage VL.

The ninth amplifier normally-off transistor MA9 includes a source terminal coupled to the ground terminal, a gate terminal coupled to the third internal node NI3 for receiving the third internal signal SI3, and a drain terminal coupled to the second internal node NI2.

The third pre-driver 1440 generates the third internal signal SI3 at the third internal node NI3 according to the control signal SC and the inverted control signal SCB. As shown in fig. 14, the third preamplifier 1440 includes a tenth amplifier normally-off transistor MA10, an eighth normally-on transistor MD8, and an eleventh amplifier normally-off transistor MA11.

The tenth amplifier normally-off transistor MA10 includes a source terminal coupled to the third internal node NI3, a gate terminal receiving the inverted control signal SCB generated by the inverter INV, and a drain terminal supplied by the low voltage VL.

The eighth normally-on transistor MD8 includes a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the third internal node NI3, and the drain terminal is supplied by the low voltage VL. According to an embodiment of the present invention, the eighth normally-on transistor MD8 is used to enhance the current driving capability from the low voltage VL to the third internal node NI3.

The eleventh amplifier normally-off transistor MA11 includes a source terminal coupled to the ground terminal, a gate terminal receiving the control signal SC, and a drain terminal coupled to the third internal node NI3.

According to other embodiments of the present invention, the driver 1400 of fig. 14 is further connected in series with any even number of the same predriver as the first predriver, the second predriver and/or the third predriver of fig. 13 and 14 for enhancing the driving capability of the control signal SC.

Comparing fig. 3 to 6 with fig. 10 to 14, since the first voltage regulator 321 of fig. 3 is moved to the upper bridge driver, the first front driver, the second front driver, and/or the third front driver shown in fig. 5 and 6 can be simplified to the first front driver, the second front driver, and/or the third front driver shown in fig. 13 and 14.

The foregoing is a summary of the embodiments. Those skilled in the art should readily devise and/or modify this invention based on such knowledge to achieve the same ends and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also realize that the same arrangements do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention. The illustrative method only represents exemplary steps, but the steps do not have to be performed in the order represented. Additional steps may be added, substituted, altered in order and/or eliminated to make adjustments as appropriate and consistent with the spirit and scope of the disclosed embodiments.

Claims

1. A power circuit, comprising:

a power transistor for extracting a power current to a ground terminal according to a driving voltage of a driving node; and

a driving circuit, comprising:

a driver, comprising:

an upper bridge transistor for providing a low voltage to the driving node according to an upper bridge voltage of an upper bridge node;

a lower bridge transistor for coupling the driving node to the ground terminal according to a control signal;

An upper bridge driver including a plurality of N-type transistors, and providing a high voltage to the upper bridge node according to the control signal, wherein the high voltage exceeds a gate operating voltage of the N-type transistors of the driving circuit;

a second voltage stabilizer for reducing a supply voltage to the low voltage;

a first pre-driver for generating a first internal signal at a first internal node according to the control signal and the inverse of the control signal, wherein the upper bridge driver provides the high voltage to the upper bridge node according to the control signal and the first internal signal;

a second pre-driver for generating a third internal signal and the control signal,

generating a second internal signal at a second internal node; and

a third pre-driver for generating a third internal signal at a third internal node according to the control signal and the inverse of the control signal;

wherein the first predriver generates the first internal signal according to the second internal signal and the third internal signal.

2. The power circuit of claim 1, wherein the power transistor is a gallium nitride transistor.

3. The power circuit of claim 1, wherein said drive circuit further comprises:

and a first voltage regulator for reducing the supply voltage to the high voltage, wherein the low voltage is lower than the high voltage.

4. A power circuit according to claim 3, wherein said first voltage regulator comprises:

the first voltage-stabilizing normally-off transistor comprises a source electrode terminal, a gate electrode terminal and a drain electrode terminal, wherein the gate electrode terminal receives a reference voltage, the source electrode terminal is coupled to a first voltage-stabilizing node, and the drain electrode terminal is coupled to a second voltage-stabilizing node;

a first resistor coupled between the supply voltage and the second voltage stabilizing node;

a second voltage-stabilizing normally-off transistor, including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal receives a first feedback voltage, and the source terminal is coupled to the first voltage-stabilizing node;

a second resistor coupled between the supply voltage and the drain terminal of the second voltage-stabilizing normally-off transistor;

a first current source for extracting a first current from the first voltage stabilizing node to flow to the grounding terminal;

a third voltage-stabilizing normally-off transistor, which comprises a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the second voltage-stabilizing node, the source terminal is coupled to the ground terminal, and the drain terminal is coupled to a third voltage-stabilizing node;

A third resistor coupled between the supply voltage and the third voltage stabilizing node;

a fourth voltage-stabilizing normally-off transistor including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the third voltage-stabilizing node, the source terminal generates the high voltage, and the drain terminal is powered by the supply voltage; and

the first feedback voltage is generated by dividing the high voltage by a first coefficient.

5. The power circuit of claim 4 wherein said first voltage regulator further comprises:

a first clamping circuit for clamping that the voltage across the gate and source terminals of the fourth normally-off transistor is lower than the breakdown voltage of the fourth normally-off transistor.

6. A power circuit according to claim 3, wherein said upper bridge driver comprises:

a first normally-off transistor including a source terminal coupled to the upper bridge node, a gate terminal receiving the control signal, and a drain terminal supplied by a high voltage;

a first normally-on transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the upper bridge node, and the drain terminal is powered by the high voltage; and

A second normally-off transistor includes a source terminal coupled to the ground terminal, a gate terminal receiving the first internal signal, and a drain terminal coupled to the upper bridge node.

7. The power circuit of claim 1, wherein said first predriver comprises:

a third normally-off transistor including a source terminal coupled to the first internal node, a gate terminal coupled to a first node, and a drain terminal powered by the low voltage;

a fourth normally-off transistor including a source terminal coupled to the ground terminal, a gate terminal receiving the control signal, and a drain terminal coupled to the first internal node;

a fifth normally-off transistor including a source terminal coupled to the first node, a gate terminal receiving an inverse of the control signal, and a drain terminal supplied by the high voltage;

a second normally-on transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the first node, and the drain terminal is powered by the high voltage; and

A sixth normally-off transistor includes a source terminal coupled to the ground terminal, a gate terminal receiving the control signal, and a drain terminal coupled to the first node.

8. The power circuit of claim 1, wherein said second predriver comprises:

a seventh normally-off transistor including a source terminal coupled to the second internal node, a gate terminal coupled to a second node, and a drain terminal powered by the low voltage;

an eighth normally-off transistor including a source terminal coupled to the ground terminal, a gate terminal receiving the third internal signal, and a drain terminal coupled to the second internal signal;

a ninth normally-off transistor including a source terminal coupled to the second node, a gate terminal receiving the third internal signal, and a drain terminal supplied by the high voltage;

a third normally-on transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are coupled to the second node, and the drain terminal is powered by the high voltage; and

A tenth normally-off transistor including a source terminal coupled to the ground terminal, a gate terminal receiving the third internal signal, and a drain terminal coupled to the second node.

9. The power circuit of claim 8, wherein said third predriver comprises:

an eleventh normally-off transistor including a source terminal coupled to the third internal node, a gate terminal coupled to a third node, and a drain terminal powered by the low voltage;

a twelfth normally-off transistor including a source terminal coupled to the ground terminal, a gate terminal receiving the control signal, and a drain terminal coupled to the third internal node;

a thirteenth normally-off transistor including a source terminal coupled to the third node, a gate terminal receiving an inverse of the control signal, and a drain terminal supplied by the high voltage;

a fourth normally-on transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the third node, and the drain terminal is powered by the high voltage; and

A fourteenth normally-off transistor includes a source terminal coupled to the ground terminal, a gate terminal receiving the control signal, and a drain terminal coupled to the third node.

10. The power circuit of claim 1, wherein said high voltage is equal to said supply voltage.

11. The power circuit of claim 10, wherein said upper bridge driver comprises:

the differential amplifier comprises a positive input node, a negative input node and an output node, wherein the positive input node receives the control signal, the negative input node is coupled to the driving node, and the output node is coupled to the upper bridge node.

12. The power circuit of claim 11, wherein said differential amplifier comprises:

a first amplifier normally-off transistor including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal receives the control signal, the source terminal is coupled to a first amplifier node, and the drain terminal is coupled to a second amplifier node;

a seventh resistor coupled between the supply voltage and the second amplifier node;

a second amplifier normally-off transistor including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the driving node and the source terminal is coupled to the first amplifier node;

An eighth resistor coupled between the supply voltage and the drain terminal of the normally-off transistor of the second amplifier;

an amplifier current source for extracting a bias current from the first amplifier node to the ground;

a third amplifier normally-off transistor including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the second amplifier node, the source terminal is coupled to the ground terminal, and the drain terminal is coupled to a third amplifier node;

a ninth amplifier normally-off transistor including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the third amplifier node and the source terminal is coupled to the output node; and

a fifth amplifier normally-off transistor includes a source terminal, a gate terminal and a drain terminal, wherein the gate terminal receives the first internal signal, the source terminal is coupled to the ground terminal, and the drain terminal is coupled to the output node of the differential amplifier.

13. The power circuit of claim 12 wherein said differential amplifier further comprises:

and a third clamping circuit for clamping the voltage across the gate terminal and the source terminal of the normally-off transistor of the fourth amplifier.

14. The power circuit of claim 11, wherein said first predriver comprises:

a sixth amplifier normally-off transistor including a source terminal coupled to the first internal node, a gate terminal receiving an inverse of the control signal, and a drain terminal supplied by the low voltage;

a sixth amplifier normally-on transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the first internal node, and the drain terminal is powered by the low voltage; and

a seventh amplifier normally-off transistor includes a source terminal coupled to the ground terminal, a gate terminal receiving the control signal, and a drain terminal coupled to the first internal node.

15. The power circuit of claim 11, wherein said driver further comprises:

a second pre-driver for generating a second internal signal at a second internal node according to a third internal signal and the control signal; and

16. The power circuit of claim 15, wherein said second predriver comprises:

an eighth amplifier normally-off transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the second internal node, the gate terminal receives the control signal, and the drain terminal is supplied by the low voltage;

a seventh amplifier normally-on transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the second internal node, and the drain terminal is powered by the low voltage; and

a ninth amplifier normally-off transistor includes a source terminal coupled to the ground terminal, a gate terminal receiving the third internal signal, and a drain terminal coupled to the second internal node.

17. The power circuit of claim 16, wherein said third predriver comprises:

a tenth amplifier normally-off transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the third internal node, the gate terminal receives an inverse of the control signal, and the drain terminal is supplied by the low voltage;

An eighth amplifier normally-on transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the third internal node, and the drain terminal is powered by the low voltage; and

an eleventh amplifier normally-off transistor includes a source terminal coupled to the ground terminal, a gate terminal receiving the control signal, and a drain terminal coupled to the third internal node.

18. The power circuit of claim 1, wherein said second voltage regulator comprises:

a fifth voltage-stabilizing normally-off transistor, which comprises a source terminal, a gate terminal and a drain terminal, wherein the gate terminal receives a reference voltage, the source terminal is coupled to a fourth voltage-stabilizing node, and the drain terminal is coupled to a fifth voltage-stabilizing node;

a fourth resistor coupled between the supply voltage and a second voltage stabilizing node;

a sixth voltage-stabilizing normally-off transistor, including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal receives a second feedback voltage, and the source terminal is coupled to the fourth voltage-stabilizing node;

a fifth resistor coupled between the supply voltage and the drain terminal of the sixth voltage-stabilizing normally-off transistor;

A second current source for extracting a second current from the fourth voltage stabilizing node to flow to the ground terminal;

a seventh voltage-stabilizing normally-off transistor, comprising a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the fifth voltage-stabilizing node, the source terminal is coupled to the ground terminal, and the drain terminal is coupled to a sixth voltage-stabilizing node;

a sixth resistor coupled between the supply voltage and the sixth voltage stabilizing node;

an eighth voltage-stabilizing normally-off transistor comprising a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the sixth voltage-stabilizing node, the source terminal generates the low voltage, and the drain terminal is supplied by the supply voltage; and

a second resistor divider divides the low voltage by a second coefficient to generate the second feedback voltage.

19. The power circuit of claim 18, wherein said second voltage regulator further comprises:

and the second clamping circuit is used for clamping the voltage across the gate end and the source end of the eighth voltage-stabilizing normally-off transistor and is smaller than the breakdown voltage of the eighth voltage-stabilizing normally-off transistor.

20. The power circuit of claim 1, wherein said drive circuit further comprises:

An undervoltage lock circuit, powered by the low voltage, pulls down the control signal to the ground when the supply voltage is below a threshold.

21. The power circuit of claim 20, wherein said under-voltage lockout circuit comprises:

a third voltage divider for dividing the supply voltage to generate a divided voltage;

a fifth normally-on transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are coupled to a first under-voltage node, and the drain terminal is powered by the low voltage;

a fifteenth normally-off transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal receives the divided voltage, and the drain terminal is coupled to the first under-voltage node;

a sixteenth normally-off transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to a second under-voltage node, the gate terminal is coupled to the first under-voltage node, and the drain terminal is coupled to a third under-voltage node;

an undervoltage resistor coupled between the low voltage and a third undervoltage node;

a seventeenth normally-off transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal is coupled to the first under-voltage node, and the drain terminal is coupled to the second under-voltage node;

An eighteenth normally-off transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the second under-voltage node, the gate terminal is coupled to the third under-voltage node, and the drain terminal is coupled to a fourth under-voltage node;

a nineteenth normally-off transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to an under-voltage-locked node, the gate terminal is coupled to the fourth under-voltage-locked node, and the drain terminal is supplied by the low voltage;

a second normally-off transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal is coupled to the third under-voltage node, the drain terminal is coupled to the under-voltage lock node, and an under-voltage lock signal is generated at the under-voltage lock node; and

a twenty-first normally-off transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal is coupled to the under-voltage lock node, and the drain terminal is coupled to the control signal, wherein the twenty-first normally-off transistor pulls down the control signal to the ground terminal according to the under-voltage lock signal.

22. A driving circuit for driving a power transistor, wherein the power transistor draws a power current to a ground terminal according to a driving voltage of a driving node, the driving circuit comprising:

a driver, comprising:

an upper bridge driver including a plurality of N-type transistors for providing a high voltage to the upper bridge node according to the control signal, wherein the high voltage exceeds the gate operating voltages of the N-type transistors;

a second voltage stabilizer for reducing a supply voltage to the low voltage;

23. The driving circuit of claim 22, wherein the power transistor is a gallium nitride transistor.

24. The drive circuit of claim 22, further comprising:

25. The driving circuit of claim 24, wherein the first voltage regulator comprises:

26. The driving circuit of claim 25, wherein said first voltage regulator further comprises:

27. The driving circuit of claim 24, wherein the upper bridge driver comprises:

28. The driving circuit of claim 22, wherein the first predriver comprises:

29. The driving circuit of claim 22, wherein the second predriver comprises:

30. The driving circuit of claim 29, wherein the third predriver comprises:

31. The driving circuit of claim 22, wherein said high voltage is equal to said supply voltage.

32. The driving circuit of claim 31, wherein the upper bridge driver comprises:

33. The driving circuit of claim 32, wherein the differential amplifier comprises:

34. The driving circuit of claim 33, wherein said differential amplifier further comprises:

35. The driving circuit of claim 32, wherein the first pre-driver comprises:

36. The drive circuit of claim 32, further comprising:

37. The driving circuit of claim 36, wherein the second predriver comprises:

38. The driving circuit of claim 37, wherein the third predriver comprises:

39. The driving circuit as recited in claim 22 wherein said second voltage regulator comprises:

40. The driving circuit of claim 39, wherein the second voltage regulator further comprises:

41. The drive circuit of claim 22, further comprising:

42. The driving circuit of claim 41, wherein the under-voltage lockout circuit comprises: