CN111082786A

CN111082786A - Power circuit and drive circuit

Info

Publication number: CN111082786A
Application number: CN201910262081.5A
Authority: CN
Inventors: 杨长暻
Original assignee: Delta Electronics Inc
Current assignee: Anchorage Semiconductor Co ltd
Priority date: 2018-10-22
Filing date: 2019-04-02
Publication date: 2020-04-28
Anticipated expiration: 2039-04-02
Also published as: TW202017296A; TWI691157B; CN111082786B

Abstract

A power circuit and a driving circuit are provided, wherein the power circuit comprises a power transistor and a driving circuit. The power transistor draws power current to the ground terminal according to the driving voltage of the driving node. The driving circuit comprises a driver, and the driver comprises an upper bridge transistor, a lower bridge transistor and an upper bridge driver. The upper bridge transistor supplies a low voltage to the driving node according to the upper bridge voltage. The lower bridge transistor couples the driving node to the ground terminal according to the control signal. The upper bridge driver includes a plurality of N-type transistors, and supplies a high voltage to an upper bridge node according to a control signal. The high voltage exceeds a gate operating voltage of a plurality of N-type transistors of the driving circuit.

Description

Power circuit and drive circuit

Technical Field

The present invention relates to a driving circuit of a gallium nitride (GaN) power element.

Background

In a power circuit, it is often necessary to boost the supply voltage to a higher voltage with a charge pump to drive the power transistor. Fig. 1 shows a general power circuit. As shown in fig. 1, the power circuit 100 includes a power transistor 110, an upper bridge transistor 121, and a lower bridge transistor 122. The upper bridge transistor 121 and the lower bridge transistor 122 are used for generating a driving voltage VD at the driving node ND, so that the power transistor 110 draws a power current IP according to the driving voltage VD.

Since the driving voltage VD reaches the operating voltage VS, the upper bridge voltage VHS exceeds the operating voltage VS to fully turn on the upper bridge transistor 121, so that the upper bridge voltage VHS exceeds the operating voltage VS to ensure the upper bridge transistor is fully turned on.

Disclosure of Invention

In view of the above, the present invention provides a power circuit, including: a power transistor and a driving circuit. The power transistor draws a power current to a ground terminal according to a driving voltage of a driving node. The driving circuit comprises a driver. The driver includes an upper bridge transistor, a lower bridge transistor and an upper bridge driver. The upper bridge transistor provides a low voltage to the driving node according to an upper bridge voltage of an upper bridge node. The lower bridge transistor couples the driving node to the ground terminal according to a control signal. The upper bridge driver includes a plurality of N-type transistors, and provides a high voltage to the upper bridge node according to the control signal, wherein the high voltage exceeds a gate operating voltage of the plurality of N-type transistors of the driving circuit.

The present invention further provides a driving circuit for driving a power transistor, wherein the power transistor draws a power current to a ground terminal according to a driving voltage of a driving node. The driving circuit comprises a driver. The driver includes an upper bridge transistor, a lower bridge transistor and an upper bridge driver. The upper bridge transistor provides a low voltage to the driving node according to an upper bridge voltage of an upper bridge node. The lower bridge transistor couples the driving node to the ground terminal according to a control signal. The upper bridge driver includes a plurality of N-type transistors, and provides a high voltage to the upper bridge node according to the control signal, wherein the high voltage exceeds a gate operating voltage of the plurality of N-type transistors of the driving circuit.

Drawings

FIG. 1 shows a general power circuit;

FIG. 2 is a block diagram illustrating a power circuit according to an embodiment of the invention;

FIG. 3 is a block diagram illustrating a power circuit according to an embodiment of the invention;

fig. 4 is a circuit diagram showing the driver of fig. 3 according to another embodiment of the present invention;

fig. 5 is a circuit diagram showing the driver of fig. 3 according to another embodiment of the present invention;

fig. 6 is a circuit diagram showing the driver of fig. 3 according to another embodiment of the present invention;

FIG. 7 is a circuit diagram of the first regulator of FIG. 3 according to one embodiment of the present invention;

FIG. 8 is a circuit diagram of the second regulator of FIG. 3 according to an embodiment of the present invention;

FIG. 9 is a circuit diagram of the under-voltage lockout circuit of FIG. 3 according to an embodiment of the present invention;

FIG. 10 is a block diagram illustrating a power circuit according to another embodiment of the present invention;

fig. 11 is a circuit diagram showing the driver of fig. 10 according to an embodiment of the present invention;

fig. 12 is a circuit diagram showing the driver of fig. 11 according to an embodiment of the present invention;

fig. 13 is a circuit diagram showing the driver of fig. 11 according to another embodiment of the present invention; and

fig. 14 is a circuit diagram showing the driver of fig. 11 according to another embodiment of the present invention.

Description of reference numerals:

100. 200, 300, 1000 power circuit

110. 10 power transistor

121 upper bridge transistor

122 lower bridge transistor

220. 320, 1020 drive circuit

221 voltage stabilizer

222. 323, 400, 500, 600, 1023, 1100, 1200, 1300, 1400 driver

321. 700 first voltage regulator

322. 800, 1022 second voltage stabilizer

324. 900, 1024 under-voltage locking circuit

410. 510, 610, 1110, 1210, 1310, 1410 bridge drivers

520. 620, 1320, 1420 first predriver

630. 1430 second predriver

640. 1440 third predriver

1111. 1211, 1311, 1411 differential amplifier

ND drive node

VD drive voltage

IP power current

VS operating voltage

VHS upper bridge voltage

VDD supply voltage

VH high voltage

VL low voltage

SC control signal

SCB inverted control signal

MHS upper bridge transistor

MLS lower bridge transistor

HSD upper bridge driver

INV inverter

ME1 first normally-off transistor

ME2 second normally-off transistor

ME3 third normally-off transistor

ME4 fourth normally-off transistor

ME5 fifth normally-off transistor

ME6 sixth normally-off transistor

ME7 seventh normally-off transistor

ME8 eighth normally-off transistor

Ninth normally-off transistor of ME9

Tenth normally-off transistor of ME10

ME11 eleventh normally-closed transistor

ME12 twelfth normally-off transistor

Thirteenth normally-closed transistor of ME13

ME14 fourteenth normally-off transistor

ME15 fifteenth normally-off transistor

ME16 sixteenth normally-off transistor

ME17 seventeenth normally-closed transistor

ME18 eighteenth normally-off transistor

Nineteenth normally-off transistor of ME19

Twentieth normally-off transistor of ME20

ME21 twenty-first normally-closed transistor

MD1 first normally-on transistor

MD2 second normally-on transistor

MD3 third normally-on transistor

Md4 fourteenth normally-on transistor

MD5 fifth normally-on transistor

MD6 sixth normally-on transistor

Seventh normally-on transistor of MD7

MD8 eighth normally-on transistor

MR1 first voltage-stabilizing normally-closed transistor

MR2 second voltage-stabilizing normally-closed transistor

MR3 third voltage-stabilizing normally-closed transistor

MR4 fourth voltage regulation normally-closed transistor

MR5 fifth voltage-stabilizing normally-closed transistor

MR6 sixth voltage-stabilizing normally-closed transistor

MR7 seventh voltage-stabilizing normally-closed transistor

MR8 eighth voltage regulator normally-closed transistor

MA1 first amplifier normally-off transistor

MA2 second Amplifier normally closed transistor

MA3 third amplifier normally-off transistor

MA4 fourth amplifier transistor normally closed

MA5 fifth Amplifier normally closed transistor

MA6 sixth Amplifier normally closed transistor

MA7 seventh amplifier normally-off transistor

MA8 eighth Amplifier normally closed transistor

MA9 ninth Amplifier normally closed transistor

MA10 tenth Amplifier normally closed transistor

MA11 eleventh Amplifier normally closed transistor

R1 first resistor

R2 second resistor

R3 third resistor

R4 fourth resistor

R5 fifth resistor

R6 sixth resistor

R7 seventh resistor

R8 eighth resistor

Ninth resistor R9

RX undervoltage resistor

IC1 first current source

IC2 second current source

IA1 amplifier current source

I1 first Current

I2 second Current

IB bias current

D1 first voltage divider

D2 second voltage divider

D3 third voltage divider

CL1 first clamp circuit

CL2 second clamp circuit

CL3 third clamp circuit

NH upper bridge node

NI1 first internal node

NI2 second internal node

NI3 third internal node

SI1 first internal signal

SI2 second internal signal

SI3 third internal Signal

SUVLO undervoltage locking signal

N1 first node

N2 second node

N3 third node

VREF reference voltage

NR1 first regulator node

NR2 second regulator node

NR3 third regulator node

NR4 fourth regulator node

NR5 fifth regulator node

NU1 first under-voltage node

NU2 second under-voltage node

NU3 third under-voltage node

NU4 fourth under-voltage node

NUVLO undervoltage locking node

NIP positive input node

NIN negative input node

NO output node

NA1 first amplifier node

NA2 second amplifier node

NA3 third amplifier node

VFB1 first feedback Voltage

VFB2 second feedback Voltage

VDV divided voltage

Detailed Description

The following description is an example of the present invention. It is intended to illustrate the general principles of the invention and not to limit the invention, which is defined by the claims.

It is noted that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. The following specific examples and arrangements of components are provided to illustrate the principles of the present invention in a simplified form and are not intended to limit the scope of the invention. Moreover, the following description may repeat reference numerals and/or letters in the various examples. However, this repetition is for the purpose of providing a simplified and clear illustration only and is not intended to limit the scope of the various embodiments and/or configurations discussed below. Moreover, the description below of one feature connected to, coupled to, and/or formed on another feature, and the like, may actually encompass a variety of different embodiments that include the feature in direct contact, or that include other additional features formed between the features, and the like, such that the features are not in direct contact.

Fig. 2 is a block diagram illustrating a power circuit according to an embodiment of the invention. As shown in fig. 2, the power circuit 200 includes a power transistor 10 and a driving circuit 220. According to an embodiment of the present invention, the power transistor 10 is a gan transistor.

The driving circuit 220 includes a voltage regulator 221 and a driver 222. The voltage regulator is used for reducing the supply voltage VDD to a low voltage VL. According to an embodiment of the present invention, the supply voltage VDD exceeds the gate operating voltages of all the transistors of the driving circuit 220, so that the voltage regulator 221 needs to step down the supply voltage VDD to a low voltage VL, wherein the low voltage VL is equal to the gate operating voltages of all the transistors of the driving circuit 220.

As shown in fig. 2, the driver 222 includes an upper bridge transistor MHS, a lower bridge transistor MLS, an upper bridge driver HSD, and an inverter INV. According to an embodiment of the present invention, the upper bridge transistor MHS corresponds to the upper bridge transistor 121 of fig. 1, and the lower bridge transistor MLS corresponds to the lower bridge transistor 122 of fig. 1.

The upper bridge driver HSD is powered by the high voltage VH for boosting the high logic level of the control signal SC to the high voltage VH, so as to completely turn on the upper bridge transistor MHS. According to an embodiment of the present invention, the high voltage VH exceeds the low voltage VL.

According to an embodiment of the present invention, the high voltage VH exceeds the supply voltage VDD. According to another embodiment of the present invention, the high voltage VH is converted from the supply voltage VDD. The lower bridge transistor MLS pulls down the driving voltage VD to the ground level according to the control signal SC.

Fig. 3 is a block diagram illustrating a power circuit according to an embodiment of the invention. As shown in fig. 3, the power circuit 300 includes the power transistor 10 and a driving circuit 320, wherein the power circuit 300 is an embodiment of the power circuit 200 of fig. 2, and is not limited thereto in any way. According to an embodiment of the present invention, the power transistor is a gan transistor.

The driving circuit 320 includes a first voltage regulator 321, a second voltage regulator 322, a driver 323, and an under-voltage lockout (UVLO) circuit 324. The first regulator 321 is used for reducing the supply voltage VDD to the high voltage VH, and the second regulator 322 is used for reducing the supply voltage VDD to the low voltage VL. According to an embodiment of the present invention, the low voltage VL is lower than the high voltage VH, and both the low voltage VL and the high voltage VH are lower than the supply voltage VDD.

The driver 323 is powered by the high voltage VH and the low voltage VL, and generates a driving voltage VD at the driving node ND according to the control signal SC, so that the power transistor 10 draws a power current IP according to the driving voltage VD.

According to an embodiment of the present invention, the driver 323 includes the upper bridge transistor 121 and the lower bridge transistor 122 of fig. 1, the low voltage VL corresponds to the operating voltage VS of fig. 1, and the high voltage VH is used to drive the upper bridge transistor MHS, which will be described in detail below.

The under-voltage locking circuit 324 is powered by the low voltage VL for detecting the supply voltage VDD. When the supply voltage VDD is lower than the threshold, the under-voltage locking circuit 324 pulls down the control signal SC to the ground level, so that the driver 323 is disabled.

According to an embodiment of the present invention, the driving circuit 320 may further include a level shifter for converting the control signal SC ranging from the supply voltage VDD to the ground level into the control signal SC ranging from the low voltage VL to the ground level. For simplicity, the level shifter is omitted here, and the control signal SC ranging from the low voltage VL to the ground level will be described in the following paragraphs.

Fig. 4 is a circuit diagram illustrating the driver of fig. 3 according to another embodiment of the present invention. As shown in fig. 4, the driver 400 includes an upper bridge transistor MHS, a lower bridge transistor MLS, an upper bridge driver 410, and an inverter INV. According to an embodiment of the present invention, the upper bridge transistor MHS corresponds to the upper bridge transistor 120 of fig. 1, and the lower bridge transistor MLS corresponds to the lower bridge transistor 122 of fig. 1.

The upper bridge driver 410 includes a first normally-closed transistor ME1, a second normally-closed transistor ME2, and a first normally-open transistor MD 1. The first normally-closed transistor ME1 includes a source terminal coupled to the bridge node NH, a gate terminal receiving the control signal SC, and a drain terminal powered by the high voltage VH.

The second normally-closed transistor ME2 includes a source terminal coupled to the ground terminal, a gate terminal receiving the inverted control signal SCB generated by the inverter INV, and a drain terminal coupled to the upper bridge node NH. According to an embodiment of the present invention, the gate terminal of the lower bridge transistor MLS receives the inverted control signal SCB.

The first normally-on transistor MD1 includes a source terminal, a gate terminal, and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the bridge node NH, and the drain terminal is powered by the high voltage VH. According to an embodiment of the present invention, the first normally-on transistor MD1 is used for providing the high voltage VH to the upper bridge node NH, and the first normally-off transistor ME1 is used for increasing the speed at which the upper bridge voltage VHs reaches the high voltage VH.

Fig. 5 is a circuit diagram illustrating the driver of fig. 3 according to another embodiment of the present invention. As shown in fig. 5, the driver 500 includes an upper bridge transistor MHS, a lower bridge transistor MLS, an upper bridge driver 510, a first pre-driver 520, and an inverter INV, wherein the driver 500 is used for driving the power transistor 10 to draw the power current IP. The upper bridge driver 510 corresponds to the upper bridge driver 410 of fig. 4 according to an embodiment of the present invention.

The first pre-driver 520 generates a first internal signal SI1 at a first internal node NI1 according to the control signal SC and the inverted control signal SCB, wherein the first pre-driver 520 includes a third normally-closed transistor ME3, a fourth normally-closed transistor ME4, a fifth normally-closed transistor ME5, a second normally-open transistor MD2, and a sixth normally-closed transistor ME 6.

The third normally-closed transistor ME3 includes a source terminal coupled to the first internal node NI1, a gate terminal coupled to the first node N1, and a drain terminal supplied by the low voltage VL.

The fourth normally-closed transistor ME4 includes a source terminal coupled to the ground terminal, a gate terminal receiving the control signal SC, and a drain terminal coupled to the first internal node NI 1.

The fifth normally-off transistor ME5 includes a source terminal coupled to the first node N1, a gate terminal receiving the inverted control signal SCB generated by the inverter INV, and a drain terminal supplied with the high voltage VH.

The second normally-on transistor MD2 includes a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are coupled to the first node N1, and the drain terminal is powered by the high voltage VH. According to an embodiment of the present invention, the second normally-on transistor MD2 is used to improve the current driving capability for providing the high voltage VH to the first node N1.

According to an embodiment of the present invention, the second normally-on transistor MD2 is used to provide the high voltage VH to the first node N1, and the fifth normally-off transistor ME5 is used to improve the speed of the first node N1 reaching the high voltage VH.

The sixth normally-closed transistor ME6 includes a source terminal coupled to the ground terminal, a gate terminal receiving the control signal SC, and a drain terminal coupled to the first node N1.

According to an embodiment of the present invention, since the first internal signal SI1 is an inverse of the control signal SC, the upper bridge driver 510 generates the upper bridge voltage VHS at the upper bridge node NH according to the control signal SC and the first internal signal SI 1.

Fig. 6 is a circuit diagram showing the driver of fig. 3 according to another embodiment of the present invention. As shown in fig. 6, the driver 600 includes an upper bridge transistor MHS, a lower bridge transistor MLS, an upper bridge driver 610, a first predriver 620, a second predriver 630, a third predriver 640, and an inverter INV. The driver 600 generates a driving voltage VD at the driving node ND, so that the power transistor 10 draws the power current IP according to the driving voltage VD.

The upper bridge driver 610 corresponds to the upper bridge driver 410 of fig. 4 according to an embodiment of the present invention. According to an embodiment of the present invention, the first pre-driver 620 corresponds to the first pre-driver 520 of fig. 5, wherein the second internal signal SI2 and the third internal signal SI3 of fig. 6 correspond to the control signal SC and the inverted control signal SCB of fig. 5, respectively.

The second pre-driver 630 generates the second internal signal SI2 at the second internal node NI2 according to the third internal signal SI3 and the control signal SC, wherein the second pre-driver 630 includes a seventh normally-closed transistor ME7, an eighth normally-closed transistor ME8, a ninth normally-closed transistor ME9, a third normally-open transistor MD3, and a tenth normally-closed transistor ME 10.

The seventh normally-closed transistor ME7 includes a source terminal coupled to the second internal node NI2, a gate terminal coupled to the second node N2, and a drain terminal supplied by the low voltage VL.

The eighth normally-closed transistor ME8 includes a source terminal coupled to the ground terminal, a gate terminal receiving the third internal signal SI3, and a drain terminal coupled to the second internal node NI 2.

The ninth normally-closed transistor ME9 includes a source terminal coupled to the second node N2, a gate terminal receiving the third internal signal SI3, and a drain terminal supplied by the high voltage VH.

The third normally-on transistor MD3 includes a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the second node N2, and the drain terminal is powered by the high voltage VH. According to an embodiment of the present invention, the third normally-on transistor MD3 is used for providing the high voltage VH to the second node N2, and the ninth normally-off transistor ME9 is used for increasing the speed of the voltage at the second node N2 reaching the high voltage VH.

The tenth normally-closed transistor ME10 includes a source terminal coupled to the ground terminal, a gate terminal receiving the third internal signal SI3, and a drain terminal coupled to the second node N2.

The third pre-driver 640 generates a third internal signal SI3 at the third internal node NI3 according to the control signal SC and the inverted control signal SCB generated by the inverter INV. The third pre-driver 640 includes an eleventh normally-closed transistor ME11, a twelfth normally-closed transistor ME12, a thirteenth normally-closed transistor ME13, a fourteenth normally-open transistor MD4, and a fourteenth normally-closed transistor ME 14.

The eleventh normally-closed transistor ME11 includes a source terminal coupled to the third internal node NI3, a gate terminal coupled to the third node N3, and a drain terminal supplied by the low voltage VL.

The twelfth normally-closed transistor ME12 includes a source terminal coupled to the ground terminal, a gate terminal receiving the control signal SC, and a drain terminal coupled to the third internal node NI 3.

The thirteenth normally closed transistor ME13 includes a source terminal coupled to the third node N3, a gate terminal receiving the inverted control signal SCB generated by the inverter INV, and a drain terminal supplied with the high voltage VH.

The fourth normally-on transistor MD4 includes a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the third node N3, and the drain terminal is powered by the high voltage VH. According to an embodiment of the present invention, the fourth normally-on transistor MD4 is used for providing the high voltage VH to the third node N3, and the thirteenth normally-off transistor ME13 is used for increasing the speed of the voltage at the third node N3 to reach the high voltage VH.

The fourteenth normally-closed transistor ME14 includes a source terminal coupled to the ground terminal, a gate terminal receiving the control signal SC, and a drain terminal coupled to the third node N3.

According to other embodiments of the present invention, the driver 500 of fig. 5 or the driver 600 of fig. 6 may be connected in series with any even number of pre-drivers identical to the first pre-driver, the second pre-driver and/or the third pre-driver of fig. 5 and fig. 6, so as to improve the driving capability of the control signal SC.

Fig. 7 is a circuit diagram of the first voltage regulator of fig. 3 according to an embodiment of the invention. As shown in fig. 7, the first voltage regulator 700 includes a first voltage regulator normally-closed transistor MR1, a first resistor R1, a second voltage regulator normally-closed transistor MR2, a second resistor R2, a first current source IC1, a third voltage regulator normally-closed transistor MR3, a third resistor R3, a fourth voltage regulator normally-closed transistor MR4, and a first voltage divider D1.

The first voltage-stabilizing normally-closed transistor MR1 includes a gate terminal, a gate terminal and a drain terminal, wherein the gate terminal receives the reference voltage VREF, the source terminal is coupled to the first voltage-stabilizing node NR1, and the drain terminal is coupled to the second voltage-stabilizing node NR 2.

According to an embodiment of the present invention, the reference voltage VREF may be generated by a bandgap (bandgap) circuit. According to another embodiment of the present invention, the reference voltage VREF may utilize a voltage divider to divide the supply voltage VDD by a factor. The first resistor R1 is coupled between the supply voltage VDD and the second voltage regulation node NR 2.

The second voltage-stabilizing normally-closed transistor MR2 includes a gate terminal receiving the first feedback voltage VFB1, a gate terminal coupled to the first voltage-stabilizing node NR1, and a drain terminal. The second resistor R2 is coupled between the supply voltage and the drain terminal of the second voltage regulator normally-closed transistor MR 2. The first current source IC1 draws a first current I1 from the first voltage regulation node NR1 to ground.

The third voltage-stabilizing normally-closed transistor MR3 includes a gate terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the second voltage-stabilizing node NR2, the source terminal is coupled to the ground terminal, and the drain terminal is coupled to the third voltage-stabilizing node NR 3. The third resistor R3 is coupled between the supply voltage VDD and the third regulation node NR 3.

The fourth voltage-stabilizing normally-closed transistor MR4 includes a gate terminal coupled to the third voltage-stabilizing node NR3, a source terminal generating the high voltage VH, and a drain terminal supplied by the supply voltage VDD.

The first voltage divider D1 divides the high voltage VH by a first coefficient to generate a first feedback voltage VFB 1. According to an embodiment of the present invention, the first voltage divider D1 includes two resistors connected in series, such that the first coefficient is determined by the ratio of the resistances of the two resistors connected in series.

According to an embodiment of the present invention, the first voltage regulator 700 is configured to maintain the first feedback voltage VFB1 equal to the reference voltage VREF such that the high voltage VH is equal to the reference voltage VREF multiplied by a first coefficient determined by the first voltage divider D1.

According to an embodiment of the present invention, the first voltage regulator 700 further includes a first clamp circuit CL 1. The first clamp circuit CL1 is used to clamp the cross-voltage between the gate terminal and the source terminal of the fourth normally-closed transistor MR4, so that the cross-voltage between the gate terminal and the source terminal of the fourth normally-closed transistor MR4 is smaller than the breakdown voltage of the fourth normally-closed transistor MR 4.

According to some embodiments of the present invention, the first clamp circuit CL1 may include a plurality of serially connected diodes or a plurality of serially connected transistors in the form of diodes, such that the voltage across the gate terminal and the source terminal of the fourth voltage-stabilizing normally-closed transistor MR4 does not exceed the forward conduction voltage of the serially connected diodes or the serially connected transistors in the form of diodes.

Fig. 8 is a circuit diagram of the second regulator of fig. 3 according to an embodiment of the invention. As shown in fig. 8, the second regulator 800 includes a fifth regulator normally-off transistor MR5, a fourth resistor R4, a sixth regulator normally-off transistor MR6, a fifth resistor R5, a second current source IC2, a seventh regulator normally-off transistor MR7, a sixth resistor R6, an eighth regulator normally-off transistor MR8, and a second voltage divider D2.

The fifth voltage-stabilizing normally-closed transistor MR5 includes a gate terminal, a gate terminal and a drain terminal, wherein the gate terminal receives the reference voltage VREF, the source terminal is coupled to the fourth voltage-stabilizing node NR4, and the drain terminal is coupled to the fifth voltage-stabilizing node NR 5. The fourth resistor R4 is coupled between the supply voltage VDD and the second voltage regulation node NR 2.

The sixth voltage-stabilizing normally-closed transistor MR6 includes a source terminal, a gate terminal and a drain terminal, wherein the gate terminal receives the second feedback voltage VFB2, and the source terminal is coupled to the fourth voltage-stabilizing node NR 4. The fifth resistor R5 is coupled between the supply voltage VDD and the sixth voltage regulator normally-closed transistor MR 6. The second current source IC2 draws a second current I2 from the fourth stable node NR4 to ground.

The seventh voltage-stabilizing normally-closed transistor MR7 includes a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the fifth voltage-stabilizing node NR5, the source terminal is coupled to the ground terminal, and the drain terminal is coupled to the sixth voltage-stabilizing node NR 6. The sixth resistor R6 is coupled to the supply voltage VDD and a sixth regulated node NR 6.

The eighth voltage-stabilizing normally-closed transistor MR8 includes a gate terminal coupled to the sixth voltage-stabilizing node NR6, a source terminal generating the low voltage VL, and a drain terminal supplied by the supply voltage VDD.

The second voltage divider D2 divides the low voltage VL by a second coefficient to generate a second feedback voltage VFB 2. According to an embodiment of the present invention, the second voltage divider D2 includes two resistors connected in series, such that the second coefficient is determined by the ratio of the resistances of the two resistors connected in series.

According to an embodiment of the present invention, the second voltage regulator 800 is configured to maintain the second feedback voltage VFB2 equal to the reference voltage VREF such that the low voltage VL is equal to the reference voltage VREF multiplied by a second coefficient determined by the second voltage divider D2.

According to an embodiment of the present invention, the second voltage regulator 800 further includes a second clamp circuit CL 2. The second clamp circuit CL2 is used to clamp the cross-voltage between the gate terminal and the source terminal of the eighth normally-closed voltage regulator transistor MR8, so that the cross-voltage between the gate terminal and the source terminal of the eighth normally-closed voltage regulator transistor MR8 is lower than the breakdown voltage of the eighth normally-closed voltage regulator transistor MR 8.

According to some embodiments of the present invention, the second clamp circuit CL2 may include a plurality of serially connected diodes or a plurality of serially connected diode-coupled transistors, such that the voltage across the gate terminal to the source terminal of the eighth normally-closed voltage regulator transistor MR8 does not exceed the forward-conducting voltage of the serially connected diodes or the serially connected diode-coupled transistors.

FIG. 9 is a circuit diagram of the under-voltage-lockout circuit of FIG. 3 according to an embodiment of the present invention. As shown in fig. 9, the under-voltage locking circuit 900 includes a third voltage divider D3, a fifth normally-open transistor MD5, a fifteenth normally-closed transistor ME15, a sixteenth normally-closed transistor ME16, an under-voltage resistor RX, a seventeenth normally-closed transistor ME17, an eighteenth normally-closed transistor ME18, a nineteenth normally-closed transistor ME19, a twentieth normally-closed transistor ME20, and a twenty-first normally-closed transistor ME 21.

The third voltage divider D3 divides the supply voltage VDD by a third coefficient to generate a divided voltage VDV. According to an embodiment of the present invention, the third voltage divider D3 is composed of a plurality of resistors connected in series. According to another embodiment of the present invention, the third voltage divider D3 is composed of a plurality of diodes or a plurality of diode-coupled transistors connected in series.

The fifth normally-on transistor MD5 includes a source terminal, a gate terminal, and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the first under-voltage node NU1, and the drain terminal is powered by the low voltage VL.

The fifteenth normally-closed transistor ME15 includes a source terminal coupled to the ground terminal, a gate terminal receiving the divided voltage VDV, and a drain terminal coupled to the first under-voltage node NU 1.

The sixteenth normally-closed transistor ME16 includes a source terminal coupled to the second under-voltage node NU2, a gate terminal coupled to the first under-voltage node NU1, and a drain terminal coupled to the third under-voltage node NU 3. The undervoltage resistor RX is operatively coupled between the low voltage VL and a third undervoltage node NU 3.

The seventeenth normally-closed transistor ME17 includes a source terminal coupled to the ground, a gate terminal coupled to the first under-voltage node NU1, and a drain terminal coupled to the second under-voltage node NU 2.

The eighteenth normally-closed transistor ME18 includes a source terminal coupled to the second under-voltage node NU2, a gate terminal coupled to the third under-voltage node NU3, and a drain terminal coupled to the fourth under-voltage node NU 4.

The nineteenth normally-closed transistor ME19 includes a source terminal coupled to the under-voltage-locked node NUVLO, a gate terminal coupled to the fourth under-voltage node NU4, and a drain terminal supplied by the low voltage VL.

The twentieth normally-closed transistor ME20 includes a source terminal coupled to the ground terminal, a gate terminal coupled to the third under-voltage node NU3, and a drain terminal coupled to the under-voltage lockout node NUVLO. The SUVLO signal is generated at the NUVLO node.

The twenty-first normally-closed transistor ME21 includes a source terminal coupled to the ground terminal, a gate terminal coupled to the under-voltage-locked node NUVLO, and a drain terminal coupled to the control signal SC. The twenty-first normally-closed transistor ME21 pulls the control signal SC down to ground level according to the under-voltage lockout signal SUVLO.

According to an embodiment of the present invention, assuming that the third coefficient generated by the third voltage divider D3 is 2/7, the threshold voltage of the fifteenth normally-closed transistor ME15 is 2V, and the under-voltage-lockout signal SUVLO is at a low logic level when the supply voltage VDD exceeds 7V. Thus, the control signal SC drives the driver 323 of fig. 3 to trigger the power transistor 10 to draw the power current IP. The numerical values set forth above are for illustrative purposes only and are not intended to be limiting in any way.

Fig. 10 is a block diagram illustrating a power circuit according to another embodiment of the invention. The power circuit 1000 is another embodiment of the power circuit 200 in fig. 2, wherein the power circuit 100 includes a power transistor 10 and a driving circuit 1020. According to an embodiment of the present invention, the power transistor 10 is a gan transistor.

As shown in fig. 10, the driving circuit 1020 includes a second voltage regulator 1022, a driver 1023, and an under-voltage lockout circuit 1024. Comparing fig. 10 with fig. 3, the driver 1023 of fig. 10 is powered by the supply voltage VDD and the low voltage VL generated by the second voltage regulator 1022. In other words, the high voltage VH of fig. 2 is directly supplied by the supply voltage VDD of fig. 10. According to an embodiment of the present invention, the second voltage regulator 1022 corresponds to the second voltage regulator 322 of FIG. 3, and the under-voltage-locking circuit 1024 corresponds to the under-voltage-locking circuit 324 of FIG. 3. According to an embodiment of the invention, the under-voltage lockout circuit 900 of FIG. 9 is shown as the under-voltage lockout circuit 1024 of FIG. 10.

Fig. 11 is a circuit diagram of the driver of fig. 10 according to an embodiment of the invention. As shown in fig. 11, the driver 1100 includes an upper bridge transistor MHS, a lower bridge transistor MLS, an upper bridge driver 1110, and an inverter INV, wherein the upper bridge driver 1110 includes a differential amplifier 1111.

The differential amplifier 1111 includes a positive input node NIP, a negative input node NIN, and an output node NO. The positive input node NIP receives the control signal SC, and the negative input node NIN is coupled to the driving node ND. The differential amplifier 1111 compares the control signal SC of the positive input node NIP with the driving voltage VD of the driving node ND and generates the upper bridge voltage VHS at the output node NO such that the upper bridge transistor MHS is fully turned on according to the upper bridge voltage VHS. When the upper bridge transistor MHS is fully turned on, the driving voltage VD is equal to the low voltage VL.

Fig. 12 is a circuit diagram illustrating the driver of fig. 11 according to an embodiment of the present invention. As shown in fig. 12, the driver 1200 includes an upper bridge transistor MHS, a lower bridge transistor MLS, an upper bridge driver 1210, and an inverter INV, wherein the upper bridge driver 1210 includes a differential amplifier 1211. In comparison between fig. 12 and fig. 10, the differential amplifier 1211 corresponds to the differential amplifier 1011.

The differential amplifier 1211 includes a first amplifier normally-closed transistor MA1, a seventh resistor R7, a second amplifier normally-closed transistor MA2, an eighth resistor R8, an amplifier current source IA1, a third amplifier normally-closed transistor MA3, a ninth resistor R9, a fourth amplifier normally-closed transistor MA4, and a fifth amplifier normally-closed transistor MA 5.

The first amplifier normally-off transistor MA1 includes a gate terminal receiving the control signal SC, a gate terminal coupled to the first amplifier node NA1, and a drain terminal coupled to the second amplifier node NA 2. The seventh resistor R7 is coupled between the supply voltage VDD and the second amplifier node NA 2.

The second amplifier normally-off transistor MA2 includes a gate terminal coupled to the driving node ND, a gate terminal coupled to the first amplifier node NA1, and a drain terminal. The eighth resistor R8 is coupled to the supply voltage VDD and the drain terminal of the second amplifier normally-off transistor MA 2. The amplifier current source IA1 draws the bias current IB from the first amplifier node NA1 to ground.

The third amplifier normally-off transistor MA3 includes a gate terminal coupled to the second amplifier node NA2, a gate terminal coupled to ground, and a drain terminal coupled to the third amplifier node NA 3. The ninth resistor R9 is coupled to the supply voltage VDD and the third amplifier node NA 3.

The fourth amplifier normally-off transistor MA4 includes a gate terminal coupled to the third amplifier node NA3, a source terminal coupled to the amplifier node NO, and a drain terminal powered by the supply voltage VDD. The third amplifier node NA3 is coupled to the upper bridge node NH.

The fifth amplifier normally-off transistor MA5 includes a source terminal, a gate terminal and a drain terminal, wherein the gate terminal receives the inverted control signal SCB, the source terminal is coupled to the ground terminal, and the drain terminal is coupled to the output node NO of the differential amplifier 1211.

According to an embodiment of the present invention, the differential amplifier 1211 further includes a third clamp circuit CL 3. The third clamp circuit CL3 is used to clamp the cross voltage between the gate terminal and the source terminal of the fourth amplifier normally-closed transistor MA4 to be lower than the breakdown voltage of the fourth amplifier normally-closed transistor MA 4. Therefore, the fourth amplifier normally-off transistor MA4 is protected from exceeding the breakdown voltage by the third clamp circuit CL 3.

According to some embodiments of the present invention, the third clamp circuit CL3 may include a plurality of serially connected diodes or a plurality of serially coupled diodes, such that the voltage across the gate terminal and the source terminal of the fourth amplifier normally-closed transistor MA4 does not exceed the forward conduction voltage of the plurality of serially connected diodes or the plurality of serially coupled diodes.

According to an embodiment of the present invention, the control signal SC is at a high voltage level, and the driving voltage VD is at a low voltage level with respect to the control signal SC. The first amplifier normally-off transistor MA1 pulls down the voltage of the second amplifier node NA2 so that the third amplifier normally-off transistor MA3 is non-conductive and the ninth resistor R9 pulls up the third amplifier node NA3 to the supply voltage VDD.

Next, the voltage of the third amplifier node NA3 turns on the fourth amplifier normally-off transistor MA4, and the reverse control signal SCB does not turn on the fifth amplifier normally-off transistor MA 5. Therefore, the differential amplifier 1211 outputs the supply voltage VDD at the output node NO, turning on the upper bridge transistor MHS.

According to another embodiment of the present invention, the control signal SC is at a low voltage level. Since the inverted control signal SCB is at a high voltage level when the control signal SC is at a low voltage level, the fifth amplifier normally-off transistor MA5 is turned on, and the output node NO of the differential amplifier 1211 is pulled down to the ground. Therefore, the inverted control signal SCB does not turn on the upper bridge transistor MHS and turns on the lower bridge transistor MLS.

Fig. 13 is a circuit diagram showing the driver of fig. 11 according to another embodiment of the present invention. As shown in fig. 13, the driver 1300 includes an upper bridge driver 1310 including a differential amplifier 1311, and a first predriver 1320.

The differential amplifier 1311 is the same as the differential amplifier 1211 of fig. 12, according to an embodiment of the invention. The first pre-driver 1320 generates the first internal signal SI1 at the first internal node according to the control signal SC and the inverted control signal SCB, so as to enhance the driving capability of the control signal SC. The first predriver 1320 includes a sixth amplifier normally-closed transistor MA6, a sixth normally-open transistor MD6, and a seventh amplifier normally-closed transistor MA 7.

The sixth amplifier normally-closed transistor MA6 includes a source terminal coupled to the first internal node NI1, a gate terminal receiving the inverted control signal SCB generated by the inverter INV, and a drain terminal supplied with the low voltage VL.

The sixth normally-on transistor MD6 includes a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the first internal node NI1, and the drain terminal is powered by the low voltage VL. According to an embodiment of the present invention, the sixth normally-on transistor MD6 is used to improve the current driving capability from the low voltage VL to the first internal node NI 1.

The seventh amplifier normally-off transistor MA7 includes a source terminal coupled to the ground terminal, a gate terminal receiving the control signal SC, and a drain terminal coupled to the first node N1.

Fig. 14 is a circuit diagram showing the driver of fig. 11 according to another embodiment of the present invention. As shown in fig. 14, the driver 1400 includes an upper bridge driver 1410, a first predriver 1420, a second predriver 1430, and a third predriver 1440, wherein the upper bridge driver 1410 includes a differential amplifier 1411. According to an embodiment of the invention, the upper bridge driver 1410 corresponds to the upper bridge driver 1210 of fig. 12, and the differential amplifier 1411 corresponds to the differential amplifier 1211 of fig. 12. According to an embodiment of the present invention, the first predriver 1420, the second predriver 1430 and the third predriver 1440 are used for improving the driving capability of the control signal SC.

According to another embodiment of the present invention, the first predriver 1420 corresponds to the first predriver 1320 of fig. 13. The second pre-driver 1430 generates the second internal signal SI2 at the second internal node NI2 according to the third internal signal SI3 and the control signal SC. As shown in fig. 14, the second pre-driver 1430 includes an eighth amplifier normally-closed transistor MA8, a seventh normally-open transistor MD7, and a ninth amplifier normally-closed transistor MA 9.

The eighth amplifier normally-closed transistor MA8 includes a source terminal coupled to the second internal node NI2, a gate terminal receiving the control signal SC, and a drain terminal supplied by the low voltage VL.

The seventh normally-on transistor MD7 includes a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the second internal node NI2, and the drain terminal is powered by the low voltage VL. According to an embodiment of the present invention, the first normally-on transistor MD7 is used to provide the low voltage VL to the second internal node NI2, and the eighth amplifier normally-off transistor MA8 is used to increase the speed at which the voltage of the second internal node NI2 reaches the low voltage VL.

The ninth amplifier normally-off transistor MA9 includes a source terminal coupled to the ground terminal, a gate terminal coupled to the third internal node NI3 for receiving the third internal signal SI3, and a drain terminal coupled to the second internal node NI 2.

The third pre-driver 1440 generates the third internal signal SI3 at the third internal node NI3 according to the control signal SC and the inverted control signal SCB. As shown in fig. 14, the third preamplifier 1440 includes a tenth amplifier normally-closed transistor MA10, an eighth normally-open transistor MD8, and an eleventh amplifier normally-closed transistor MA 11.

The tenth amplifier normally-closed transistor MA10 includes a source terminal coupled to the third internal node NI3, a gate terminal receiving the inverted control signal SCB generated by the inverter INV, and a drain terminal supplied with the low voltage VL.

The eighth normally-on transistor MD8 includes a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the third internal node NI3, and the drain terminal is powered by the low voltage VL. According to an embodiment of the present invention, the eighth normally-on transistor MD8 is used to improve the current driving capability from the low voltage VL to the third internal node NI 3.

The eleventh amplifier normally-off transistor MA11 includes a source terminal coupled to the ground terminal, a gate terminal receiving the control signal SC, and a drain terminal coupled to the third internal node NI 3.

According to another embodiment of the present invention, the driver 1400 of fig. 14 is further connected in series with any even number of predrivers same as the first predriver, the second predriver and/or the third predriver of fig. 13 and fig. 14, so as to enhance the driving capability of the control signal SC.

In comparison between fig. 3 to 6 and fig. 10 to 14, the first regulator 321 in fig. 3 is moved to the upper bridge driver, and the first predriver, the second predriver and/or the third predriver shown in fig. 5 and 6 can be simplified to the first predriver, the second predriver and/or the third predriver shown in fig. 13 and 14.

What has been described above is a general characterization of the embodiments. Those skilled in the art should readily appreciate that they can readily use the present disclosure as a basis for designing or modifying other structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that the same may be used without departing from the spirit and scope of the present invention and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the invention. The illustrative method represents exemplary steps only, and the steps are not necessarily performed in the order represented. Additional, alternative, permuted and/or eliminated steps may be added, substituted, permuted and/or modified as appropriate and consistent with the spirit and scope of the disclosed embodiments.

Claims

1. A power circuit, comprising:

the power transistor is used for drawing a power current to a grounding end according to a driving voltage of a driving node; and

a driver circuit, comprising:

a driver, comprising:

an upper bridge transistor for providing a low voltage to the driving node according to an upper bridge voltage of an upper bridge node;

a lower bridge transistor coupling the driving node to the ground terminal according to a control signal; and

an upper bridge driver including a plurality of N-type transistors and generating a control signal according to the control signal,

providing a high voltage to the upper bridge node, wherein the high voltage exceeds a gate operating voltage of the plurality of N-type transistors of the driving circuit.

2. The power circuit of claim 1 wherein said power transistor is a gallium nitride transistor.

3. The power circuit of claim 1, wherein said driver circuit further comprises:

a second voltage stabilizer for reducing a supply voltage to the low voltage.

4. The power circuit of claim 3, wherein said drive circuit further comprises:

a first pre-driver for generating a first internal signal at a first internal node according to the control signal and an inverse of the control signal, wherein the upper bridge driver provides the high voltage to the upper bridge node according to the control signal and the first internal signal.

5. The power circuit of claim 4, wherein said driver circuit further comprises:

a first voltage regulator for stepping down the supply voltage to the high voltage, wherein the low voltage is lower than the high voltage.

6. The power circuit of claim 5, wherein said first voltage regulator comprises:

a first voltage-stabilizing normally-closed transistor, including source terminal, grid terminal and drain terminal, in which the grid terminal is used for receiving a reference voltage, the source terminal is coupled to a first voltage-stabilizing node, and the drain terminal is coupled to the above-mentioned second voltage-stabilizing node;

a first resistor coupled between the supply voltage and the second regulated node;

a second voltage-stabilizing normally-closed transistor, including source terminal, grid terminal and drain terminal, in which the grid terminal receives a first feedback voltage, and the source terminal is coupled to the above-mentioned first voltage-stabilizing node;

a second resistor coupled between the supply voltage and a drain terminal of the second voltage regulator transistor;

a first current source for drawing a first current from the first voltage regulation node to the ground terminal;

a third voltage-stabilizing normally-closed transistor, including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the second voltage-stabilizing node, the source terminal is coupled to the ground terminal, and the drain terminal is coupled to a third voltage-stabilizing node;

a third resistor coupled between the supply voltage and the third regulated node;

a fourth voltage-stabilizing normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the third voltage-stabilizing node, the source terminal generates the high voltage, and the drain terminal is powered by the supply voltage; and

a first voltage divider divides the high voltage by a first coefficient to generate the first feedback voltage.

7. The power circuit of claim 6 wherein said first voltage regulator further comprises:

a first clamping circuit for clamping the cross voltage between the gate terminal and the source terminal of the fourth voltage-stabilizing normally-closed transistor to be lower than the breakdown voltage of the fourth voltage-stabilizing normally-closed transistor.

8. The power circuit of claim 5, wherein said upper bridge driver comprises:

a first normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the upper bridge node, the gate terminal receives the control signal, and the drain terminal is supplied with power by a high voltage;

a first normally-on transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the upper bridge node, and the drain terminal is powered by the high voltage; and

and a second normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal receives the first internal signal, and the drain terminal is coupled to the upper bridge node.

9. The power circuit of claim 4 wherein said first predriver comprises:

a third normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the first internal node, the gate terminal is coupled to a first node, and the drain terminal is powered by the low voltage;

a fourth normally-closed transistor, including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal receives the control signal, and the drain terminal is coupled to the first internal node;

a fifth normally-off transistor comprising a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the first node, the gate terminal receives the inverse of the control signal, and the drain terminal is powered by the high voltage;

a second normally-on transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the first node, and the drain terminal is powered by the high voltage; and

a sixth normally-closed transistor, including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal receives the control signal, and the drain terminal is coupled to the first node.

10. The power circuit of claim 4 wherein said driver further comprises:

a second predriver for generating a second internal signal at a second internal node according to a third internal signal and the control signal; and

a third predriver for generating a third internal signal at a third internal node according to the control signal and the inverse of the control signal;

the first pre-driver generates the first internal signal according to the second internal signal and the third internal signal.

11. The power circuit of claim 10 wherein said second predriver comprises:

a seventh normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the second internal node, the gate terminal is coupled to a second node, and the drain terminal is powered by the low voltage;

an eighth normally-closed transistor, including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal receives the third internal signal, and the drain terminal is coupled to the second internal signal;

a ninth normally-closed transistor comprising a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the second node, the gate terminal receives the third internal signal, and the drain terminal is supplied with power by the high voltage;

a third normally-on transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the second node, and the drain terminal is powered by the high voltage; and

a tenth normally-closed transistor, including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal receives the third internal signal, and the drain terminal is coupled to the second node.

12. The power circuit of claim 11 wherein said third predriver comprises:

an eleventh normally-closed transistor comprising a source terminal, a gate terminal, and a drain terminal, wherein the source terminal is coupled to the third internal node, the gate terminal is coupled to a third node, and the drain terminal is powered by the low voltage;

a twelfth normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal receives the control signal, and the drain terminal is coupled to the third internal node;

a thirteenth normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the third node, the gate terminal receives the inverse of the control signal, and the drain terminal is powered by the high voltage;

a fourth normally-on transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the third node, and the drain terminal is powered by the high voltage; and

a fourteenth normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal receives the control signal, and the drain terminal is coupled to the third node.

13. The power circuit of claim 4 wherein said high voltage is equal to said supply voltage.

14. The power circuit of claim 13, wherein said upper bridge driver comprises:

a differential amplifier including a positive input node receiving the control signal, a negative input node coupled to the driving node, and an output node coupled to the upper bridge node.

15. The power circuit of claim 14, wherein said differential amplifier comprises:

a first amplifier normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal receives the control signal, the source terminal is coupled to a first amplifier node, and the drain terminal is coupled to a second amplifier node;

a seventh resistor coupled between the supply voltage and the second amplifier node;

a second amplifier normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the driving node, and the source terminal is coupled to the first amplifier node;

an eighth resistor coupled between the supply voltage and a drain terminal of the second amplifier normally-off transistor;

an amplifier current source for drawing a bias current from the first amplifier node to the ground terminal;

a third amplifier normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the second amplifier node, the source terminal is coupled to the ground terminal, and the drain terminal is coupled to a third amplifier node;

a ninth amplifier normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the third amplifier node, and the source terminal is coupled to the output node; and

a fifth amplifier normally-closed transistor, including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal receives the first internal signal, the source terminal is coupled to the ground terminal, and the drain terminal is coupled to the output node of the differential amplifier.

16. The power circuit of claim 15 wherein said differential amplifier further comprises:

a third clamping circuit for clamping the cross voltage between the gate terminal and the source terminal of a fourth amplifier normally-closed transistor.

17. The power circuit of claim 14 wherein said first predriver comprises:

a sixth amplifier normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the first internal node, the gate terminal receives the inverse of the control signal, and the drain terminal is supplied with power from the low voltage;

a sixth amplifier normally-on transistor comprising a source terminal, a gate terminal, and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the first internal node, and the drain terminal is powered by the low voltage; and

a seventh amplifier normally-closed transistor, which includes a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal receives the control signal, and the drain terminal is coupled to the first internal node.

18. The power circuit of claim 14 wherein said driver further comprises:

19. The power circuit of claim 18, wherein said second predriver comprises:

an eighth amplifier normally-closed transistor comprising a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the second internal node, the gate terminal receives the control signal, and the drain terminal is powered by the low voltage;

a seventh amplifier normally-on transistor comprising a source terminal, a gate terminal, and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the second internal node, and the drain terminal is powered by the low voltage; and

a ninth amplifier normally-closed transistor, including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal receives the third internal signal, and the drain terminal is coupled to the second internal node.

20. The power circuit of claim 19 wherein said third predriver comprises:

a tenth amplifier normally-closed transistor comprising a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the third internal node, the gate terminal receives the inverse of the control signal, and the drain terminal is supplied with power by the low voltage;

an eighth amplifier normally-on transistor comprising a source terminal, a gate terminal, and a drain terminal, wherein the source terminal and the gate terminal are both coupled to the third internal node, and the drain terminal is powered by the low voltage; and

an eleventh amplifier normally-closed transistor, including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal receives the control signal, and the drain terminal is coupled to the third internal node.

21. The power circuit of claim 3, wherein said second voltage regulator comprises:

a fifth voltage-stabilizing normally-closed transistor, including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal receives a reference voltage, the source terminal is coupled to a fourth voltage-stabilizing node, and the drain terminal is coupled to the fifth voltage-stabilizing node;

a fourth resistor coupled between the supply voltage and the second regulated node;

a sixth voltage-stabilizing normally-closed transistor, including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal receives a second feedback voltage, and the source terminal is coupled to the fourth voltage-stabilizing node;

a fifth resistor coupled between the supply voltage and a drain terminal of the sixth voltage regulator transistor;

a second current source for drawing a second current from the fourth voltage-stabilizing node to the ground terminal;

a seventh voltage-stabilizing normally-closed transistor, including a source terminal, a gate terminal and a drain terminal, wherein the gate terminal is coupled to the fifth voltage-stabilizing node, the source terminal is coupled to the ground terminal, and the drain terminal is coupled to a sixth voltage-stabilizing node;

a sixth resistor coupled between the supply voltage and the sixth regulated node;

an eighth voltage-stabilizing normally-closed transistor including a source terminal, a gate terminal, and a drain terminal, wherein the gate terminal is coupled to the sixth voltage-stabilizing node, the source terminal generates the low voltage, and the drain terminal is supplied with power by the supply voltage; and

a second resistor divider divides the low voltage by a second coefficient to generate the second feedback voltage.

22. The power circuit of claim 21 wherein said second voltage regulator further comprises:

a second clamping circuit for clamping the cross voltage between the gate terminal and the source terminal of the eighth voltage-stabilizing normally-closed transistor, which is smaller than the breakdown voltage of the eighth voltage-stabilizing normally-closed transistor.

23. The power circuit of claim 3, wherein said drive circuit further comprises:

an under-voltage locking circuit powered by the low voltage and pulling down the control signal to the ground when the supply voltage is lower than a threshold value.

24. The power circuit of claim 23, wherein the under-voltage-lockout circuit comprises:

a third voltage divider for dividing the supply voltage to generate a divided voltage;

a fifth normally-on transistor comprising a source terminal, a gate terminal and a drain terminal, wherein the source terminal and the gate terminal are both coupled to a first under-voltage node, and the drain terminal is powered by the low voltage;

a fifteenth normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal receives the divided voltage, and the drain terminal is coupled to the first under-voltage node;

a sixteenth normally-closed transistor comprising a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to a second under-voltage node, the gate terminal is coupled to the first under-voltage node, and the drain terminal is coupled to a third under-voltage node;

an undervoltage resistor coupled between the low voltage and a third undervoltage node;

a seventeenth normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal is coupled to the first under-voltage node, and the drain terminal is coupled to the second under-voltage node;

an eighteenth normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the second under-voltage node, the gate terminal is coupled to the third under-voltage node, and the drain terminal is coupled to a fourth under-voltage node;

a nineteenth normally-closed transistor comprising a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to an under-voltage-locked node, the gate terminal is coupled to the fourth under-voltage node, and the drain terminal is powered by the low voltage;

a second normally-off transistor comprising a source terminal, a gate terminal, and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal is coupled to the third under-voltage node, and the drain terminal is coupled to the under-voltage-locked node, wherein an under-voltage-locked signal is generated at the under-voltage-locked node; and

and a twenty-first normally-closed transistor including a source terminal, a gate terminal and a drain terminal, wherein the source terminal is coupled to the ground terminal, the gate terminal is coupled to the under-voltage-locked node, and the drain terminal is coupled to the control signal, wherein the twenty-first normally-closed transistor pulls down the control signal to the ground terminal according to the under-voltage-locked signal.

25. A driving circuit for driving a power transistor, wherein the power transistor draws a power current to a ground terminal according to a driving voltage of a driving node, the driving circuit comprising:

a driver, comprising:

a lower bridge transistor coupling the driving node to the ground terminal according to a control signal;

an upper bridge driver includes a plurality of N-type transistors for providing a high voltage to the upper bridge node according to the control signal, wherein the high voltage exceeds a gate operating voltage of the plurality of N-type transistors.

26. The driving circuit as claimed in claim 25, wherein the power transistor is a gan transistor.

27. The driver circuit of claim 25, wherein said driver circuit further comprises:

a second voltage stabilizer for reducing a supply voltage to the low voltage.

28. The driver circuit of claim 27, wherein said driver circuit further comprises:

29. The drive circuit of claim 28, further comprising:

30. The driver circuit of claim 29, wherein said first voltage regulator comprises:

31. The driver circuit of claim 30, wherein said first voltage regulator further comprises:

32. The driver circuit of claim 29, wherein said upper bridge driver comprises:

33. The driver circuit of claim 28, wherein said first predriver comprises:

34. The drive circuit of claim 28, further comprising:

35. The driver circuit of claim 34, wherein said second predriver comprises:

36. The driver circuit of claim 35, wherein said third predriver comprises:

37. The driving circuit of claim 28, wherein said high voltage is equal to said supply voltage.

38. The driver circuit of claim 37, wherein said upper bridge driver comprises:

39. The drive circuit of claim 38, wherein said differential amplifier comprises:

40. The driver circuit of claim 39, wherein said differential amplifier further comprises:

41. The driver circuit of claim 38, wherein said first predriver comprises:

42. The drive circuit of claim 38, further comprising:

43. The driver circuit of claim 42, wherein said second predriver comprises:

44. The driver circuit of claim 43, wherein said third predriver comprises:

45. The driver circuit as claimed in claim 27, wherein said second voltage regulator comprises:

46. The driver circuit of claim 45, wherein said second voltage regulator further comprises:

47. The drive circuit of claim 27, further comprising:

48. The driving circuit of claim 47, wherein the under-voltage-lockout circuit comprises: