CN111081668A - Pad structure, chip and method thereof - Google Patents

Pad structure, chip and method thereof Download PDF

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Publication number
CN111081668A
CN111081668A CN201911408534.7A CN201911408534A CN111081668A CN 111081668 A CN111081668 A CN 111081668A CN 201911408534 A CN201911408534 A CN 201911408534A CN 111081668 A CN111081668 A CN 111081668A
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metal layer
chip
silicon
bonding pad
pad
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CN201911408534.7A
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Chinese (zh)
Inventor
马树永
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Weixin Technology Shaoxing Co Ltd
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Weixin Technology Shaoxing Co Ltd
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Priority to CN201911408534.7A priority Critical patent/CN111081668A/en
Publication of CN111081668A publication Critical patent/CN111081668A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a bonding pad structure, a chip and a forming method thereof, wherein the bonding pad structure is characterized by comprising a front metal layer, a back metal layer and a bonding pad, wherein the front metal layer and the back metal layer are respectively positioned on the front surface and the back surface of a chip silicon wafer, and the bonding pad is formed on the front surface of the back metal layer. According to the invention, because the pad design is realized by using few metal layers, the parasitic capacitance of the pad is greatly reduced by 80% at most, so that the high-speed IO design can be realized, and the IO working speed is increased; meanwhile, because the pad design is realized by using few metal layers, the path from the chip device to the pad is obviously shortened, the discharge path is shorter during electrostatic discharge (ESD), the resistance is smaller, and the ESD protection capability can be obviously improved.

Description

Pad structure, chip and method thereof
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a bonding pad structure, a chip and a method thereof.
Background
When an integrated circuit (chip) is packaged, a bare die (chip) and an external packaging tube shell need to be connected through a bonding wire, a bonding pad (bonding pad) is designed on the die, and a bare metal layer is arranged on the bonding pad, so that metal contact can be formed between the bonding wire and the die, metal interconnection conduction electric signals are formed, the IO pad of the chip is connected with a pin of the packaging tube shell, the bonding pad needs to be connected with a bottom layer device in the chip, and the bonding pad is designed by adopting the highest layer metal in the common technology.
In the conventional technology, an integrated circuit device is formed on a chip silicon wafer (wafer/die), the device is connected to a first metal layer through a contact hole, the first metal layer is connected to a second metal layer through a first via hole, and sequentially upward, and finally connected to a top metal layer through an Nth metal layer/Nth via hole to form an integral structure of a bonding pad, the top metal layer in the bonding pad has an exposed metal window, and the bonding pad of the chip can be connected to a packaging tube shell through routing packaging on the window. In current integrated circuit technology, the top metal layer usually reaches more than 5 layers, even more than 10 layers.
Since the integrated circuit process usually has more than 5 or even more than 10 layers of top metal, and the pad structure includes all metal layers, the number of metal layers is especially large, the total area is very large, and the parasitic capacitance is especially large. For high-speed IO design, because the signal working speed is high, the IO pad parasitic capacitance is required to be very small, and the high-speed IO design can be realized, so that the traditional IO pad structure has the limitation of further promotion of the IO working speed due to more metal layers and large parasitic capacitance.
Disclosure of Invention
Accordingly, the present invention is directed to a pad structure, a chip and a method thereof.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the embodiment of the invention provides a bonding pad structure which comprises a front metal layer, a back metal layer and a bonding pad, wherein the front metal layer and the back metal layer are respectively positioned on the front surface and the back surface of a chip silicon wafer, and the bonding pad is formed on the front surface of the back metal layer.
In the scheme, the lower side of the front metal layer is connected with a chip silicon chip through a plurality of contact holes; the back of the back metal layer is connected with the contact hole through the silicon through hole.
In the above scheme, the front metal layer is composed of at least one metal layer.
In the scheme, one part of the contact hole on the lower side of the front metal layer is connected with a chip device on a chip silicon wafer, and the other part of the contact hole is connected with a silicon through hole.
In the scheme, the silicon through hole longitudinally penetrates through the chip silicon wafer.
In the above scheme, the through silicon vias are uniformly distributed in the region of the chip silicon wafer corresponding to the bonding pad, or distributed around the region of the chip silicon wafer corresponding to the bonding pad.
In the scheme, the total number of the silicon through holes corresponding to the bonding pad is 50-2000, and the side length or the diameter is 50nm-1 um.
An embodiment of the present invention provides a chip, which includes the pad structure according to any one of the above schemes.
The embodiment of the invention provides a forming method of a bonding pad structure, which comprises the following steps:
step 1: after the processing technology of a silicon chip device of a chip silicon chip is finished, etching a cavity at the position where a contact hole needs to be formed through an etching technology, and then forming the contact hole at the corresponding position of the silicon chip device and a bonding pad through a metal deposition technology;
step 2: etching a hollow groove at the position of the front side of the silicon chip device where the front side metal layer is required to be formed by an etching process, and then forming the front side metal layer by a metal deposition process;
and step 3: forming a cavity on the chip silicon wafer at the corresponding position of the bonding pad through an etching process, and then forming a silicon through hole through a metal deposition process;
and 4, step 4: etching a hollow groove at a position of the back of the silicon chip device where a back metal layer is required to be formed by an etching process, and then forming the back metal layer by a metal deposition process;
and 5: and forming a hollow hole through an etching process, and then forming a bonding pad on the back metal layer through a metal deposition process.
In the above scheme, when the front metal layer is at least two metal layers, the metal layer at the lowest layer in the front metal layer is firstly processed, the through hole corresponding to the metal layer is then processed, the adjacent upper metal layer is then processed, and the remaining metal layers are sequentially processed according to the sequence.
Compared with the prior art, the invention realizes the pad design by using few metal layers, so the parasitic capacitance of the pad is greatly reduced by 80 percent at most, thereby realizing the high-speed IO design and improving the IO working speed; meanwhile, because the pad design is realized by using few metal layers, the path from the chip device to the pad is obviously shortened, the discharge path is shorter during electrostatic discharge (ESD), the resistance is smaller, and the ESD protection capability can be obviously improved.
Drawings
Fig. 1 is a schematic structural diagram of a pad structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a first arrangement of through-silicon vias in a pad structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a second arrangement of through-silicon vias in a pad structure according to an embodiment of the invention;
fig. 4 is a flowchart of a method for forming a pad structure according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The embodiment of the invention provides a pad structure, as shown in fig. 1, comprising a front metal layer 1, a back metal layer 2 and a pad 3, wherein the front metal layer 1 and the back metal layer 2 are respectively positioned on the front and the back of a chip silicon chip 4, and the pad 3 is formed on the front of the back metal layer 2; according to the invention, because the pad design is realized by using few metal layers, the parasitic capacitance of the pad 3 is greatly reduced by 80% at most, so that the high-speed IO design can be realized, and the IO working speed is increased; meanwhile, because the pad design is realized by using few metal layers, the path from the chip device to the pad is obviously shortened, the discharge path is shorter during electrostatic discharge (ESD), the resistance is smaller, and the ESD protection capability can be obviously improved.
The lower side of the front metal layer 1 is connected with a chip silicon chip 4 through a plurality of contact holes 5; the back surface of the back metal layer 2 is connected with the contact hole 5 through a through silicon via 6.
The front metal layer 1 is composed of at least one metal layer.
One part of the contact holes 5 on the lower side of the front metal layer 1 is connected with chip devices 41 on a chip silicon wafer 4, and the other part of the contact holes is connected with silicon through holes 6.
The through silicon via 6 longitudinally penetrates through the chip silicon wafer 4.
The through silicon vias 6 are uniformly distributed on the chip silicon wafer 4 in the region corresponding to the bonding pads 3 as shown in fig. 2, or distributed around the region corresponding to the bonding pads 3 on the chip silicon wafer 4 as shown in fig. 3.
The total number of the silicon through holes 6 corresponding to the bonding pad 3 is 50-2000, and the side length or the diameter is 50nm-1 um.
The embodiment of the invention also provides a chip, which comprises a front metal layer 1, a back metal layer 2, a bonding pad 3 and a chip silicon chip 4; the front metal layer 1 is positioned on the front surface of the chip silicon wafer 4, and the lower side of the front metal layer is connected with the chip silicon wafer 4 through a plurality of contact holes 5; the back metal layer 2 is positioned on the back of the chip silicon chip 4, and the back of the back metal layer is connected with the contact hole 5 through a silicon through hole 6; the front side of the back metal layer 2 forms a pad 3.
The front metal layer 1 consists of at least one metal layer and is used for meeting the requirements of larger power supply and higher electrostatic protection;
specifically, the front metal layer 1 may adopt a combination of a first metal layer and a second metal layer, or a first metal layer and a third metal layer, or a first metal layer, a second metal layer and a fourth metal layer in various forms to meet different power supply requirements and electrostatic protection requirements.
One part of the contact holes 5 on the lower side of the front metal layer 1 is connected with chip devices 41 on a chip silicon wafer 4, and the other part of the contact holes is connected with silicon through holes 6.
The through silicon via 6 longitudinally penetrates through the chip silicon wafer 4.
The through silicon via 6 penetrates through the chip silicon wafer 4 longitudinally, is exposed from the back of the chip silicon wafer 4, is connected to the back metal layer 2, directly forms a bonding pad on the back metal layer 2, and is packaged to the packaging tube shell through routing.
The through silicon vias 6 are uniformly distributed on the chip silicon wafer 4 in the region corresponding to the bonding pads 3 as shown in fig. 2, or distributed around the region corresponding to the bonding pads 3 on the chip silicon wafer 4 as shown in fig. 3.
The total number of the silicon through holes 6 corresponding to the bonding pad 3 is 50-2000, and the side length or the diameter is 50nm-1 um.
An embodiment of the present invention further provides a method for forming a pad structure, as shown in fig. 4, the method is implemented by the following steps:
step 101: after the processing technology of the silicon wafer device 41 of the chip silicon wafer 4 is finished, the contact hole 5 of the silicon wafer device 41 and the corresponding position of the bonding pad 3 is processed;
specifically, a cavity is first etched at a position where a contact hole needs to be formed through an etching process, and then the contact hole 5 is formed through a metal deposition process.
The contact hole 5 is formed of copper, aluminum, or tungsten and an alloy thereof.
Step 102: processing a front metal layer 1 on a contact hole 5 corresponding to the silicon wafer device 41;
specifically, first, a cavity is etched at a position where the front metal layer 1 needs to be formed by an etching process, and then the front metal layer 1 is formed by a metal deposition process.
The front metal layer 1 is formed of copper, aluminum or tungsten and alloys thereof.
When the front metal layer 1 is at least two metal layers, firstly processing the metal layer at the lowest layer in the front metal layer 1, then processing the through hole corresponding to the metal layer, then processing the adjacent upper metal layer, and sequentially processing the rest metal layers according to the sequence.
Step 103: processing a silicon through hole 6 on the chip silicon chip 4 at the position corresponding to the bonding pad 3;
specifically, a cavity is formed at a position corresponding to the through-silicon via 6 by an etching process, and then the through-silicon via 6 is formed by a metal deposition process.
The through silicon vias 6 are formed of copper, aluminum or tungsten and alloys thereof.
Step 104: processing a back metal layer 2 on the back of the chip silicon wafer 4;
specifically, a hollow groove is etched at a position where a back metal layer 2 needs to be formed on the back of the silicon wafer device 41 through an etching process, and then the back metal layer 2 is formed through a metal deposition process;
step 105: and etching the back metal layer 2 to form a bonding pad 3.
Specifically, a cavity is formed through an etching process, and then the bonding pad 3 is formed through a metal deposition process; the pad 3 is formed of aluminum and its alloy.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims (10)

1. The bonding pad structure is characterized by comprising a front metal layer, a back metal layer and a bonding pad, wherein the front metal layer and the back metal layer are respectively positioned on the front side and the back side of a chip silicon wafer, and the bonding pad is formed on the front side of the back metal layer.
2. The pad structure of claim 1, wherein the underside of the front side metal layer is connected to a chip die through a plurality of contact holes; the back of the back metal layer is connected with the contact hole through the silicon through hole.
3. Pad structure in accordance with claim 1 or 2 characterized in that the front side metal layer consists of at least one metal layer.
4. The pad structure of claim 3, wherein a portion of the contact holes on the underside of the front side metal layer are connected to chip devices on a chip die and another portion are connected to the through silicon vias.
5. The pad structure of claim 4, wherein the silicon via extends longitudinally through a chip silicon die.
6. The pad structure of claim 5, wherein the through silicon vias are uniformly distributed on the chip silicon in the region corresponding to the pads or distributed around the region corresponding to the pads.
7. The pad structure of claim 6, wherein the total number of the through silicon vias corresponding to the pad is 50-2000, and the side length or the diameter is 50nm-1 um.
8. A chip comprising a pad structure according to any one of claims 1-7.
9. A forming method of a bonding pad structure is characterized in that the method comprises the following steps:
step 1: after the processing technology of a silicon chip device of a chip silicon chip is finished, etching a cavity at the position where a contact hole needs to be formed through an etching technology, and then forming the contact hole at the corresponding position of the silicon chip device and a bonding pad through a metal deposition technology;
step 2: etching a hollow groove at the position of the front side of the silicon chip device where the front side metal layer is required to be formed by an etching process, and then forming the front side metal layer by a metal deposition process;
and step 3: forming a cavity on the chip silicon wafer at the corresponding position of the bonding pad through an etching process, and then forming a silicon through hole through a metal deposition process;
and 4, step 4: etching a hollow groove at a position of the back of the silicon chip device where a back metal layer is required to be formed by an etching process, and then forming the back metal layer by a metal deposition process;
and 5: and forming a hollow hole through an etching process, and then forming a bonding pad on the back metal layer through a metal deposition process.
10. The method of claim 9, wherein when the front metal layer is at least two metal layers, the lowest metal layer of the front metal layer is processed, the through hole corresponding to the metal layer is processed, and then the next upper metal layer is processed, and the remaining metal layers are processed sequentially according to the above order.
CN201911408534.7A 2019-12-31 2019-12-31 Pad structure, chip and method thereof Pending CN111081668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
CN201911408534.7A CN111081668A (en) 2019-12-31 2019-12-31 Pad structure, chip and method thereof

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CN111081668A true CN111081668A (en) 2020-04-28

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030160293A1 (en) * 2002-02-26 2003-08-28 International Business Machines Corporation Method of connecting core I/O pins to backside chip I/O pads
US20090014888A1 (en) * 2007-07-12 2009-01-15 Min-Hyung Lee Semiconductor chip, method of fabricating the same and stack package having the same
CN101582412A (en) * 2008-05-12 2009-11-18 台湾积体电路制造股份有限公司 I/O pad structure
US20120329277A1 (en) * 2009-03-05 2012-12-27 International Business Machines Corporation Two-sided semiconductor structure
CN103258787A (en) * 2012-02-15 2013-08-21 三星电子株式会社 Method for fabricating semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030160293A1 (en) * 2002-02-26 2003-08-28 International Business Machines Corporation Method of connecting core I/O pins to backside chip I/O pads
US20090014888A1 (en) * 2007-07-12 2009-01-15 Min-Hyung Lee Semiconductor chip, method of fabricating the same and stack package having the same
CN101582412A (en) * 2008-05-12 2009-11-18 台湾积体电路制造股份有限公司 I/O pad structure
US20120329277A1 (en) * 2009-03-05 2012-12-27 International Business Machines Corporation Two-sided semiconductor structure
CN103258787A (en) * 2012-02-15 2013-08-21 三星电子株式会社 Method for fabricating semiconductor device

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Application publication date: 20200428