CN111063679A - Layout circuit board of multi-device parallel power module - Google Patents

Layout circuit board of multi-device parallel power module Download PDF

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Publication number
CN111063679A
CN111063679A CN202010008671.8A CN202010008671A CN111063679A CN 111063679 A CN111063679 A CN 111063679A CN 202010008671 A CN202010008671 A CN 202010008671A CN 111063679 A CN111063679 A CN 111063679A
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silicon carbide
parallel
lotus
module
power module
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赵斌
柯俊吉
张浩然
赵志斌
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North China Electric Power University
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North China Electric Power University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Inverter Devices (AREA)

Abstract

The invention discloses a layout circuit board of a multi-device parallel power module. In the layout circuit board of the multi-device parallel power module, a first lotus-shaped BNC interface (comprising the load positive output terminal and the load negative output terminal) is positioned in the center of the PCB, and a plurality of parallel silicon carbide devices in the silicon carbide device parallel module are circumferentially arranged by taking the first lotus-shaped BNC interface as the circle center; the multiple parallel decoupling capacitors in the decoupling capacitor parallel module adopt a circumferential layout by taking the first lotus-shaped BNC interface as a circle center, so that the arrangement positions of parallel devices are optimized, parasitic parameters of a circuit are matched, the distribution difference of stray inductance of the circuit is reduced, the current coupling effect is eliminated, the transient current imbalance of the multi-device parallel power module can be changed, and the current equalizing characteristic of a better parallel silicon carbide device is realized.

Description

Layout circuit board of multi-device parallel power module
Technical Field
The invention relates to the technical field of multi-device parallel current sharing, in particular to a layout circuit board of a multi-device parallel power module.
Background
With the ever-increasing demands on efficiency, power density, reliability and maintenance, high-capacity converters are becoming increasingly popular. The technology of silicon carbide majority carrier devices is gradually maturing, can eliminate the limitation of silicon material device switching technology, and is gradually applied to high-density and high-efficiency power converters. The current rating of a single commercial silicon carbide chip is typically limited to tens of amps due to a tradeoff between current rating and chip cost, and the limited current capacity creates challenges for high current applications of silicon carbide devices. To improve current capability, multiple device power modules in parallel are often employed. In a multi-device parallel power module, the current distribution between the parallel chips is uniform because the unbalanced current between the devices causes the power module to be thermally unbalanced and weak. Transient current imbalance is mainly caused by mismatching of device parameters and circuit parameters, a traditional silicon carbide parallel power module adopts a direct copper layout mode, and transient current imbalance is aggravated by a current coupling effect.
Disclosure of Invention
The invention aims to provide a layout circuit board of a multi-device parallel power module, which aims to solve the problem that transient current imbalance is aggravated due to the current coupling effect existing in a direct copper layout mode adopted by a traditional silicon carbide parallel power module.
In order to achieve the purpose, the invention provides the following scheme:
a layout circuit board for a multi-device parallel power module, comprising: the multi-device parallel power module comprises a PCB and the multi-device parallel power module positioned on the PCB; the multi-device parallel power module includes: the device comprises a silicon carbide device parallel module, a load positive electrode output terminal, a load negative electrode output terminal, a grid electrode driving signal terminal, an auxiliary source electrode driving signal terminal, a drain electrode power collecting terminal, a source electrode power collecting terminal and a decoupling capacitor parallel module; the silicon carbide device parallel module comprises a plurality of directly parallel silicon carbide devices; the decoupling capacitor parallel module comprises a plurality of decoupling capacitors directly connected in parallel;
the load positive output terminal is respectively connected with drain power terminals of the silicon carbide devices and positive terminals of the decoupling capacitors; the load negative electrode output terminal is respectively connected with the source electrode power terminals of the silicon carbide devices and the negative electrode terminals of the decoupling capacitors; the load positive output terminal and the load negative output terminal are led out through a first lotus-shaped BNC interface; the first lotus-shaped BNC interface is positioned in the center of the PCB; the silicon carbide devices are arranged in a circumferential manner by taking the first lotus-shaped BNC interface as a circle center; the decoupling capacitors are circumferentially distributed by taking the first lotus-shaped BNC interface as a circle center;
the gate drive signal terminals are respectively connected with the respective gate signal terminals of the plurality of silicon carbide devices; the auxiliary source electrode driving signal terminals are respectively connected with the auxiliary source electrode signal terminals of the silicon carbide devices; the grid electrode driving signal terminal and the auxiliary source electrode signal terminal are led out through a second lotus-shaped BNC interface; the second lotus-shaped BNC interface is arranged next to the first lotus-shaped BNC interface;
the drain power collecting terminal is connected with the load positive electrode output terminal; the source power collecting terminal is connected with the load negative electrode output terminal; the drain power collecting terminal and the source power collecting terminal are arranged on the periphery of the PCB.
Optionally, when the number N of the silicon carbide devices directly connected in parallel in the silicon carbide device parallel module is not greater than 8, the PCB is regular N-sided or circular.
Optionally, when the number N of the silicon carbide devices directly connected in parallel in the silicon carbide device parallel module is greater than 8, the PCB board is circular.
Optionally, the distances between the pin end of each silicon carbide device in the silicon carbide device parallel module and the first lotus-shaped BNC interface are equal; the angle interval between two adjacent silicon carbide devices is 360 degrees/N; and N is the number of the silicon carbide devices directly connected in parallel in the silicon carbide device parallel module.
Optionally, the pin end of each silicon carbide device faces a side away from the first lotus-shaped BNC interface.
Optionally, distances between a positive terminal of each decoupling capacitor in the decoupling capacitor parallel module and the first lotus-shaped BNC interface are equal; the angle interval between two adjacent decoupling capacitors is 360 degrees/M; m is the number of the decoupling capacitors directly connected in parallel in the decoupling capacitor parallel module.
Optionally, the positive terminal of each decoupling capacitor faces to a side close to the first lotus-shaped BNC interface; the negative terminal of each decoupling capacitor faces to the side away from the first lotus-shaped BNC interface.
Optionally, a circumference enclosed by the decoupling capacitors is located at a circumference periphery enclosed by the silicon carbide devices.
Optionally, the first lotus-shaped BNC interface and the second lotus-shaped BNC interface are separated by 5 mm.
Optionally, the number N of the silicon carbide devices directly connected in parallel in the silicon carbide device parallel module is 5; the number M of the decoupling capacitors directly connected in parallel in the decoupling capacitor parallel module is 20; the PCB is in a regular pentagon shape.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides a layout circuit board of a multi-device parallel power module, wherein in the layout circuit board of the multi-device parallel power module, a first lotus-shaped BNC interface (comprising a load anode output terminal 8 and a load cathode output terminal 7) is positioned at the center of a PCB (printed circuit board) 19, and a plurality of parallel silicon carbide devices in a silicon carbide device parallel module adopt circumferential layout by taking the first lotus-shaped BNC interface as the circle center; the multiple parallel decoupling capacitors in the decoupling capacitor parallel module adopt a circumferential layout by taking the first lotus-shaped BNC interface as a circle center, so that the arrangement positions of parallel devices are optimized, parasitic parameters of a circuit are matched, the distribution difference of stray inductance of the circuit is reduced, the current coupling effect is eliminated, the transient current imbalance of the multi-device parallel power module can be changed, and the current equalizing characteristic of a better parallel silicon carbide device is realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings provided by the present invention without any creative effort.
Fig. 1 is a schematic structural diagram of a layout circuit board of a multi-device parallel power module according to an embodiment of the present invention;
fig. 2 is a schematic circuit connection diagram of a multi-device parallel power module according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a layout principle of a multi-device parallel power module according to an embodiment of the present invention;
the numbers in the figures are respectively: a drain power sink terminal 1, a first silicon carbide device 2 (MOS 1 in FIG. 2), a second silicon carbide device 3 (MOS 2 in FIG. 2), an auxiliary source drive signal terminal 4 (SS 1 in FIG. 2), a gate drive signal terminal 5 (G1 in FIG. 2), a third silicon carbide device 6 (MOS 3 in FIG. 2), a load negative output terminal 7 (DC- "in FIG. 2), a load positive output terminal 8 (DC + in FIG. 2), a fourth silicon carbide device 9 (MOS 4 in FIG. 2), a fifth silicon carbide device 10 (MOS 5 in FIG. 2), a decoupling capacitor 11, a source power sink terminal 12, a drain power terminal 13 (D in fig. 2) of the silicon carbide device, a source power terminal 14 (S in fig. 2), an auxiliary source signal terminal 15 (SS in fig. 2), a gate signal terminal 16 (G in fig. 2), a positive terminal 17, a negative terminal 18 of the decoupling capacitor, and a PCB 19.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a layout circuit board of a multi-device parallel power module, which aims to solve the problem that transient current imbalance is aggravated due to the current coupling effect existing in a direct copper layout mode adopted by a traditional silicon carbide parallel power module.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Fig. 1 is a schematic structural diagram of a layout circuit board of a multi-device parallel power module according to an embodiment of the present invention; fig. 2 is a schematic circuit connection diagram of a multi-device parallel power module according to an embodiment of the present invention. Referring to fig. 1 and 2, the layout circuit board of the multi-device parallel power module provided by the present invention includes: a PCB board 19 and the multi-device parallel power module on the PCB board 19. The multi-device parallel power module specifically comprises: a parallel module of silicon carbide devices, a load positive output terminal 8 (DC + in fig. 2), a load negative output terminal 7 (DC-infig. 2), a gate drive signal terminal 5 (G1 in fig. 2), an auxiliary source drive signal terminal 4 (SS 1 in fig. 2), a drain power sink terminal 1, a source power sink terminal 12, and a decoupling capacitor parallel module. The silicon carbide device parallel module comprises a plurality of directly parallel silicon carbide devices; the decoupling capacitor parallel module comprises a plurality of decoupling capacitors directly connected in parallel. As shown in fig. 1 and fig. 2, in the embodiment of the present invention, the silicon carbide device parallel module includes five directly parallel silicon carbide devices, which are a first silicon carbide device 2 (MOS 1 in fig. 2), a second silicon carbide device 3 (MOS 2 in fig. 2), a third silicon carbide device 6 (MOS 3 in fig. 2), a fourth silicon carbide device 9 (MOS 4 in fig. 2), and a fifth silicon carbide device 10 (MOS 5 in fig. 2); the decoupling capacitor parallel module comprises 20 decoupling capacitors 11 (C1-C20 in FIG. 2) directly connected in parallel.
The load positive output terminal 8 (DC + in fig. 2) is connected to the drain power terminal (D in fig. 2) of each of the plurality of silicon carbide devices and the positive terminal of each of the plurality of decoupling capacitors, respectively. The load negative output terminal 7 (DC-) is connected to the source power terminal (S in fig. 2) of each of the plurality of silicon carbide devices and the negative terminal of each of the plurality of decoupling capacitors. The load positive output terminal 8 (DC + in FIG. 2) and the load negative output terminal 7 (DC-) in FIG. 2 are led out through a first lotus-shaped BNC interface (BCN 1 in FIG. 2). Specifically, the load positive output terminal 8 (DC +) is connected to the interface No. 1 of the first lotus-shaped BNC interface (BCN 1 in fig. 2), and the load negative output terminal 7 (DC-) is connected to the interface No. 2 of the first lotus-shaped BNC interface (BCN 1 in fig. 2).
As shown in fig. 1, the first lotus-shaped BNC interface (including the load positive output terminal 8 and the load negative output terminal 7) is located at the center of the PCB board 19. And the silicon carbide devices adopt a circumferential layout by taking the first lotus-shaped BNC interface as a circle center. The decoupling capacitors are arranged in a circumferential mode by taking the first lotus-shaped BNC interface as a circle center. I.e. the centre of the circumferential layout coincides with the centre of the PCB board 19.
As shown in fig. 1 and 2, the gate drive signal terminals 5 (G1 in fig. 2) are respectively connected to the gate signal terminals (G in fig. 2) of the respective silicon carbide devices; the auxiliary source drive signal terminals 4 (SS 1 in fig. 2) are connected to respective auxiliary source signal terminals (SS in fig. 2) of the plurality of silicon carbide devices. The gate drive signal terminal 5 (G1 in fig. 2) and the auxiliary source signal terminal 4 (SS 1 in fig. 2) are led out through a second lotus-shaped BNC interface (BCNGS 1 in fig. 2). As shown in fig. 2, the second lotus-shaped BNC interface (comprising the gate drive signal terminal 5 and the auxiliary source drive signal terminal 4) is arranged next to the first lotus-shaped BNC interface. Preferably, the first lotus-shaped BNC connector and the second lotus-shaped BNC connector are spaced by 5 mm.
The drain power collecting terminal 1 is connected with the load positive electrode output terminal 8; the source power collecting terminal 12 is connected to the load negative electrode output terminal 7. The drain power collecting terminal 1 and the source power collecting terminal 12 are arranged on the periphery of the PCB board 19.
In order to facilitate the circuit design on the PCB 19, when the number N of the silicon carbide devices directly connected in parallel in the silicon carbide device parallel module is not greater than 8, the PCB 19 is shaped as a regular N-polygon or a circle. When the number N of the silicon carbide devices directly connected in parallel in the silicon carbide device parallel module is greater than 8, the shape of the PCB board 19 is circular.
The pin terminals (including the drain power terminal 13, the source power terminal 14, the auxiliary source signal terminal 15 and the gate signal terminal 16) of each silicon carbide device in the silicon carbide device parallel module are all equidistant from the first lotus-shaped BNC interface. The angle interval between two adjacent silicon carbide devices is 360 degrees/N; and N is the number of the silicon carbide devices directly connected in parallel in the silicon carbide device parallel module. Preferably, the pin end of each of the silicon carbide devices faces a side away from the first lotus-shaped BNC interface.
The distances between the positive terminal 17 of each decoupling capacitor 11 in the decoupling capacitor parallel module and the first lotus-shaped BNC interface are equal. The angle interval between two adjacent decoupling capacitors 11 is 360 °/M; m is the number of the decoupling capacitors 11 directly connected in parallel in the decoupling capacitor parallel module. Preferably, the positive terminal 17 of each decoupling capacitor 11 faces to a side close to the first lotus-shaped BNC interface; the negative terminal 18 of each decoupling capacitor 11 faces away from the first lotus-shaped BNC interface. The circumference enclosed by the decoupling capacitors is positioned at the circumference periphery enclosed by the silicon carbide devices.
In the embodiment of the present invention, as shown in fig. 1, the number N of the silicon carbide devices directly connected in parallel in the silicon carbide device parallel module is 5, and the shape of the PCB 19 is a regular pentagon. Five directly parallel silicon carbide devices in the silicon carbide device parallel module are arranged in a circumferential mode, the angle interval between every two adjacent silicon carbide devices is 72 degrees, and the interval distance is the same. The number M of the decoupling capacitors directly connected in parallel in the decoupling capacitor parallel module is 20; twenty decoupling capacitors 11 directly connected in parallel in the decoupling capacitor parallel module are arranged in a circle, and the interval between two adjacent decoupling capacitors is 18 degrees, and the interval distance is the same. Since the center of the circumferential layout coincides with the center of the pentagonal PCB 19, the circle formed by the five silicon carbide devices and the circle formed by the twenty decoupling capacitor units 11 are concentric circles.
The drain power terminals 13 of the five silicon carbide devices are connected with the load anode output terminal 8 at the same time, and the drain power terminals 13 of the five silicon carbide devices are equal to the load anode output terminal 8 in length because the five silicon carbide devices adopt a circumferential layout by taking the first lotus-shaped BNC interface as a circle center.
The source power terminals 14 of the five silicon carbide devices are connected with the load cathode output terminal 7 at the same time, and the connecting lines of the source power terminal 14 of each silicon carbide device and the load cathode output terminal 7 are equal in length because the five silicon carbide devices adopt a circumferential layout by taking the first lotus-shaped BNC interface as a circle center.
The gate signal terminals 16 of the five silicon carbide devices are connected with the gate drive signal terminal 5 at the same time, and since the five silicon carbide devices adopt a circumferential layout with the first lotus-shaped BNC interface as a center, and the second lotus-shaped BNC interface is adjacent to the first lotus-shaped BNC interface, the connection length of the gate signal terminal 16 of each silicon carbide device and the gate drive signal terminal 5 is substantially equal.
The auxiliary source signal terminals 15 of the five silicon carbide devices are connected with the auxiliary source driving signal terminal 4 at the same time, and because the five silicon carbide devices adopt a circumferential layout with the first lotus-shaped BNC interface as a center of a circle and the second lotus-shaped BNC interface is adjacent to the first lotus-shaped BNC interface, the connection length of the auxiliary source signal terminal 15 and the auxiliary source driving signal terminal 4 of each silicon carbide device is also basically equal.
Therefore, the invention ensures the symmetry of the power loop and the driving loop of the parallel devices by adopting the three-dimensional circumferential layout of the plurality of parallel silicon carbide devices, reduces the dispersion and the inconsistency of the stray inductance of the main power loop between the devices, eliminates the current coupling effect between the parallel devices and improves the uniformity of current distribution. The symmetry mainly means that five silicon carbide devices connected in parallel are symmetrically distributed about the center of a regular pentagon, so that the lengths of connecting lines between the drain electrode of each silicon carbide device and the anode of a load are equal, the lengths of connecting lines between the source electrode of each silicon carbide device and the cathode of the load are equal, and the specific connecting lines can be realized by adopting a multilayer board design. Specifically, the multilayer board is designed by adopting six layers of PCB boards, and the electrical connection of different layers is realized by punching holes on the PCB boards. Wherein the connections of the driving source (G) and the auxiliary source (SS) of the silicon carbide device are routed in two layers of the PCB.
In the invention, the connecting line length of the grid 16 and the grid driving signal terminal 5 of each parallel silicon carbide power device is basically equal, and the connecting line length of the auxiliary source 15 and the auxiliary source driving signal terminal 4 of each parallel silicon carbide power device is basically equal, so that the lead wire inductance of the driving loop of each silicon carbide device is designed to be the same, and the delay difference of the driving signals can be eliminated. The design of a multilayer PCB (printed Circuit Board) is adopted to lay copper in a large area, the symmetry of the layout of the grid signal terminal 16 and the auxiliary source signal terminal 15 of the parallel device can be ensured, the consistency of stray inductance of a driving circuit is improved, the delay difference of driving signals is reduced, and the synchronism of switches is ensured.
The parallel devices in the silicon carbide device parallel module and the decoupling capacitor parallel module are in three-dimensional circumferential layout, so that the arrangement positions of the parallel devices are optimized, the parasitic parameters of the circuit are matched, the distribution difference of stray inductance of the circuit is reduced, the current coupling effect is eliminated, the transient current imbalance of a multi-device parallel power module can be changed, and the current sharing characteristic of the parallel silicon carbide devices is better.
Fig. 3 is a schematic diagram of a layout principle of a multi-device parallel power module according to an embodiment of the present invention, as shown in fig. 3, UDCThe power supply is a direct-current voltage source and is used for supplying power to a power loop of a multi-device parallel power module (power module for short). The right-hand dashed line in fig. 3 represents the power loop and the left-hand dashed line represents the drive loop. CDCThe bus capacitor is used for maintaining voltage stability. L is a load inductance; and D is a freewheeling diode used for freewheeling when the silicon carbide device is turned off. L isdIs the drain stray inductance, VdriveThe grid driving power supply is used for supplying power to the driving loop. RgIs a driving resistor; MOS1 is a first silicon carbide device 2, Ls1Is a source electrode of itBulk and lead inductances, Lsx1An auxiliary source lead inductance for it; MOS2 is a second silicon carbide device 3, Ls2Is its source stray inductance and lead inductance, Lsx2An auxiliary source lead inductance for it; MOS3 is a third silicon carbide device 6, Ls3Is its source stray inductance and lead inductance, Lsx3An auxiliary source lead inductance for it; MOS4 is a fourth silicon carbide device 9, Ls4Is its source stray inductance and lead inductance, Lsx4An auxiliary source lead inductance for it; MOS5 is a fifth silicon carbide device 10, Ls5Is its source stray inductance and lead inductance, Lsx5An auxiliary source lead inductance for it; l isssIs a source lead inductance. The following derivation proves the layout principle of the parallel modules of the silicon carbide devices:
drain current i of silicon carbide deviceDCan be expressed by the following expression:
iD＝gfs(VGS-Vth)
wherein g isfsIs transconductance of silicon carbide devices, VGSIs the gate-source voltage, VthIs the threshold voltage. VGSThe position in the driving loop can be expressed by the following expression:
Figure BDA0002356295000000081
wherein iGIs the gate drive loop current, LXSRepresenting the auxiliary source stray inductance.
Because the current of the driving loop is very small and can be ignored, the threshold voltages of different silicon carbide devices are close, and the unbalanced current of the parallel devices is mainly influenced by VGSOf two silicon carbide devices, V ofGSThe difference of (d) can be expressed by the following expression:
VGS1-VGS2＝(VG1-VS1)-(VG2-VS2)＝VS2-VS1
wherein VGS1、VGS2Respectively representing the gate-source voltages, V, of two parallel silicon carbide devicesG1、VG2Respectively representing the gate voltages, V, of two parallel silicon carbide devicesS1、VS2Respectively, the source voltages of two parallel silicon carbide devices.
From this it can be seen that VGSThe difference in (c) is mainly due to the difference in source voltages, and the unbalanced current of two parallel silicon carbide devices can be expressed by the following expression:
Figure BDA0002356295000000091
wherein iD2、iD1Respectively representing the drain currents, L, of two parallel silicon carbide devicesbIs the source stray inductance, L, of the silicon carbide device MOS112Is the source lead inductance between two parallel silicon carbide devices MOS1 and MOS 2. When multiple devices are connected in parallel, the source leads of the two silicon carbide devices are inductively coupled with the current of other devices, so that the unbalanced current of the parallel devices is increased.
The multi-device parallel power module adopts the three-dimensional circumferential layout on the PCB, and ensures that the lead lengths of five directly parallel silicon carbide devices in the power module are the same, so that the source lead inductances are the same, and the V of the five directly parallel silicon carbide devicesGSThe difference can be expressed by the following expression:
Figure BDA0002356295000000092
Figure BDA0002356295000000093
Figure BDA0002356295000000094
Figure BDA0002356295000000095
Figure BDA0002356295000000096
wherein VS1、VS2、VS3、VS4、VS5Source voltages of five parallel silicon carbide devices MOS1, MOS2, MOS3, MOS4 and MOS5 respectively; l isS1～LS5The source stray inductance and the lead inductance of five parallel silicon carbide devices MOS 1-MOS 5 are respectively; i.e. iD1～iD5Drain currents of five parallel silicon carbide devices MOS 1-MOS 5.
The unbalanced currents of five direct parallel silicon carbide devices MOS 1-MOS 5 obtained by the above formula can be expressed by the following expression:
Figure BDA0002356295000000101
Figure BDA0002356295000000102
Figure BDA0002356295000000103
Figure BDA0002356295000000104
Figure BDA0002356295000000105
the matrix form can be expressed as:
Figure BDA0002356295000000106
wherein iD12＝iD1-iD2，iD23＝iD2-iD3，iD34＝iD3-iD4，iD45＝iD4-iD5，iD51＝iD5-iD1。
The invention relates to a multi-device parallel power moduleThe layout circuit board adopts a three-dimensional circumferential layout of five direct parallel silicon carbide devices, and the unbalanced current of MOS1 and MOS2 only consists of LS1、LS2And iD1、iD2It is determined that the unbalanced current of MOS2 and MOS3 is only formed by LS2、LS3And iD2、iD3It is determined that the unbalanced current of MOS3 and MOS4 is only formed by LS3、LS4And iD3、iD4It is determined that the unbalanced current of MOS4 and MOS5 is only formed by LS4、LS5And iD4、iD5It is determined that the unbalanced current of MOS5 and MOS1 is only formed by LS5、LS1And iD5、iD1And (6) determining. That is to say, after the layout mode of the multi-device parallel power module is adopted, the unbalanced current between two parallel devices has no coupling item, and the unbalanced current is reduced, so that the three-dimensional layout mode can eliminate the current coupling effect, reduce the unbalanced current between the parallel devices, and realize the better current sharing characteristic of the parallel silicon carbide devices.
Of course, the above description of the layout principle is not limited to the embodiments of the present invention, the above embodiments and the drawings are only used to illustrate the technical solution of the present invention and are not meant to be limiting, when there are n devices connected in parallel, the angle between the two devices is
Figure BDA0002356295000000111
The current coupling effect can be eliminated by adopting the layout mode of the invention, and the unbalanced current among the parallel devices can be represented by the following matrix:
Figure BDA0002356295000000112
wherein iD(n-2)(n-1)＝iD(n-2)-iD(n-1)，iDnIs the drain current of the nth parallel device.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention disclosed herein should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
The principles and embodiments of the present invention have been described herein using specific examples, which are presented solely to aid in the understanding of the apparatus and its core concepts; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.

Claims (10)

1. A layout circuit board of a multi-device parallel power module, comprising: the multi-device parallel power module comprises a PCB and the multi-device parallel power module positioned on the PCB; the multi-device parallel power module includes: the device comprises a silicon carbide device parallel module, a load positive electrode output terminal, a load negative electrode output terminal, a grid electrode driving signal terminal, an auxiliary source electrode driving signal terminal, a drain electrode power collecting terminal, a source electrode power collecting terminal and a decoupling capacitor parallel module; the silicon carbide device parallel module comprises a plurality of directly parallel silicon carbide devices; the decoupling capacitor parallel module comprises a plurality of decoupling capacitors directly connected in parallel;
the load positive output terminal is respectively connected with drain power terminals of the silicon carbide devices and positive terminals of the decoupling capacitors; the load negative electrode output terminal is respectively connected with the source electrode power terminals of the silicon carbide devices and the negative electrode terminals of the decoupling capacitors; the load positive output terminal and the load negative output terminal are led out through a first lotus-shaped BNC interface; the first lotus-shaped BNC interface is positioned in the center of the PCB; the silicon carbide devices are arranged in a circumferential manner by taking the first lotus-shaped BNC interface as a circle center; the decoupling capacitors are circumferentially distributed by taking the first lotus-shaped BNC interface as a circle center;
the gate drive signal terminals are respectively connected with the respective gate signal terminals of the plurality of silicon carbide devices; the auxiliary source electrode driving signal terminals are respectively connected with the auxiliary source electrode signal terminals of the silicon carbide devices; the grid electrode driving signal terminal and the auxiliary source electrode signal terminal are led out through a second lotus-shaped BNC interface; the second lotus-shaped BNC interface is arranged next to the first lotus-shaped BNC interface;
the drain power collecting terminal is connected with the load positive electrode output terminal; the source power collecting terminal is connected with the load negative electrode output terminal; the drain power collecting terminal and the source power collecting terminal are arranged on the periphery of the PCB.
2. The layout circuit board of the multi-device parallel power module of claim 1, wherein when the number N of the silicon carbide devices directly connected in parallel in the silicon carbide device parallel module is less than or equal to 8, the PCB board is in a shape of a regular N-sided polygon or a circle.
3. The layout circuit board of a multi-device parallel power module of claim 1, wherein the shape of the PCB board is circular when the number N >8 of the silicon carbide devices directly connected in parallel in the silicon carbide device parallel module.
4. The layout circuit board of a multi-device parallel power module of claim 1, wherein the pin terminals of each of the silicon carbide devices in the silicon carbide device parallel module are all equidistant from the first lotus-shaped BNC interface; the angle interval between two adjacent silicon carbide devices is 360 degrees/N; and N is the number of the silicon carbide devices directly connected in parallel in the silicon carbide device parallel module.
5. The layout circuit board of a multi-device parallel power module of claim 4, wherein a pin end of each of the silicon carbide devices faces a side away from the first lotus-shaped BNC interface.
6. The layout circuit board of multi-device parallel power module of claim 1, wherein the positive polarity terminal of each decoupling capacitor in the decoupling capacitor parallel module is equidistant from the first lotus-shaped BNC interface; the angle interval between two adjacent decoupling capacitors is 360 degrees/M; m is the number of the decoupling capacitors directly connected in parallel in the decoupling capacitor parallel module.
7. The layout circuit board of a multi-device parallel power module of claim 6, wherein a positive polarity terminal of each said decoupling capacitor faces a side proximate to said first lotus-shaped BNC interface; the negative terminal of each decoupling capacitor faces to the side away from the first lotus-shaped BNC interface.
8. The layout circuit board of a multi-device parallel power module of claim 1, wherein a circumference enclosed by a plurality of said decoupling capacitors is located at a periphery of a circumference enclosed by a plurality of said silicon carbide devices.
9. The layout circuit board of a multi-device parallel power module of claim 1, wherein the first and second lotus-shaped BNC interfaces are separated by 5 mm.
10. The layout circuit board of a multi-device parallel power module according to claim 1, wherein the number N of the silicon carbide devices directly connected in parallel in the silicon carbide device parallel module is 5; the number M of the decoupling capacitors directly connected in parallel in the decoupling capacitor parallel module is 20; the PCB is in a regular pentagon shape.
CN202010008671.8A 2020-01-06 2020-01-06 Layout circuit board of multi-device parallel power module Pending CN111063679A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113030608A (en) * 2021-02-24 2021-06-25 华北电力大学 Power device flow equalizing characteristic evaluation experimental device
CN113162020A (en) * 2021-04-20 2021-07-23 核工业西南物理研究院 Current equalizing circuit structure with a large number of capacitors connected in parallel and power supply of ball-and-socket device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113030608A (en) * 2021-02-24 2021-06-25 华北电力大学 Power device flow equalizing characteristic evaluation experimental device
CN113030608B (en) * 2021-02-24 2022-02-08 华北电力大学 Power device flow equalizing characteristic evaluation experimental device
CN113162020A (en) * 2021-04-20 2021-07-23 核工业西南物理研究院 Current equalizing circuit structure with a large number of capacitors connected in parallel and power supply of ball-and-socket device
CN113162020B (en) * 2021-04-20 2022-10-18 核工业西南物理研究院 Current equalizing circuit structure with a large number of capacitors connected in parallel and power supply of ball-and-socket device

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