CN111061671B

CN111061671B - SPI transmission control method, sending equipment and receiving equipment

Info

Publication number: CN111061671B
Application number: CN201911279094.XA
Authority: CN
Inventors: 杨帆; 刘萌; 田世甦; 张波; 吴忠洁
Original assignee: Shanghai Mindmotion Microelectronics Co ltd
Current assignee: Shanghai Mindmotion Microelectronics Co ltd
Priority date: 2019-12-13
Filing date: 2019-12-13
Publication date: 2021-08-17
Anticipated expiration: 2039-12-13
Also published as: CN111061671A

Abstract

The invention provides an SPI transmission control method, sending equipment and receiving equipment, wherein the method comprises the following steps: writing data to be sent into a sending register through a processor; when the written data to be sent are sequentially arranged from left to right in a digit ordering mode from high digits to low digits and the digit sending mode is that low-digit data are transmitted in advance, writing the data to be sent into a sending queue; when the written data to be sent are sequentially arranged from left to right in a digit ordering mode from high to low and the digit sending mode is that high-order data are transmitted in the front, data conversion is carried out on the written data to be sent, and the data to be sent after the data conversion is written into a sending queue; and transmitting the data to be transmitted in the transmission queue byte by byte. The invention realizes the functions of adjustable transmission digit and prior transmission of high data digit by configuring the bit width of the register and carrying out data conversion.

Description

SPI transmission control method, sending equipment and receiving equipment

Technical Field

The present invention relates to the field of data transmission technologies, and in particular, to an SPI transmission control method, a transmitting device, and a receiving device.

Background

SPI (Serial Peripheral Interface), a high speed, full duplex communication bus, is a Serial Peripheral port. It uses three buses and one or more chip select lines for data transfer between master and slave devices. The three buses are SCLK (Serial Clock), MOSI (Master Output/Slave Input), MISO (Master Input/Slave Output), and nss (Slave select) for the Master to select and communicate with a Slave device on the bus.

However, data transmission is carried out through an analog SPI device at present, and the problems of complexity and difficult time sequence control of software programming GPIO analog clocks and data are easy to occur. The existing hardware SPI equipment carries out data transmission, the transmission digit cannot be adjusted, and the function of high-order preceding transmission cannot be realized.

Disclosure of Invention

In order to enable a client to use the SPI transmission control method more intelligently and individually, the invention aims to provide the SPI transmission control method, the sending equipment and the receiving equipment, and realize the functions of adjustable transmission digit and prior transmission of high-order data by configuring the bit width of a sending shift register or a receiving shift register and carrying out data conversion.

The technical scheme provided by the invention is as follows:

the invention provides an SPI transmission control method, which is applied to a sending end and comprises the following steps:

writing data to be sent into a sending register through a processor;

when the written data to be sent are sequentially arranged from left to right in a digit ordering mode from high to low and the digit sending mode is that low-order data are transmitted in advance, writing the data to be sent into a sending buffer;

when the written data to be sent are sequentially arranged from left to right in a digit ordering mode from high to low and the digit sending mode is that high-order data are transmitted in the front, data conversion is carried out on the written data to be sent through a sending data control module, and the data to be sent after the data conversion is written into a sending buffer;

and transmitting the data to be transmitted in the transmission buffer byte by byte.

Further, the data conversion of the written data to be transmitted by the transmission data control module includes:

exchanging high and low bits of the data to be sent;

and sequentially carrying out data displacement on the data after the high and low bit interchange, so that the highest bit of the data after the high and low bit interchange is moved to the highest bit of the sending conversion register, and the lowest bit of the data after the high and low bit interchange is moved to the lowest bit of the sending conversion register.

Further, the sending the data to be sent in the sending buffer byte by byte includes the steps of:

transmitting the data to be transmitted with the digit sequencing mode matched with the digit transmission mode to the SPI output pin byte by byte under the control of a clock signal and a digit counter;

and transmitting the data to be transmitted, which is matched with the digit ordering mode and the digit transmitting mode, through an SPI output pin until the transmission is finished.

Further, the transmitting the data to be transmitted, which is matched with the bit number sending mode in the bit number ordering mode, to the SPI output pin byte by byte under the control of the clock signal and the bit number counter includes the steps of:

when a clock signal is received, enabling to send first bit data of one byte in the data to be sent, wherein the bit ordering mode is matched with the bit sending mode, and updating the value of a sending byte number counter when the value of the sending bit number counter is equal to a preset value until the value of the sending byte number counter is equal to the number of calculated bytes; and the number of bytes is calculated according to the number of bits of the data to be sent.

The invention also provides an SPI transmission control method, which is applied to a receiving end and comprises the following steps:

receiving data and writing the received data into a receive register;

when the bit ordering mode of the written received data is that the high bits and the low bits are sequentially arranged from left to right and the bit receiving mode is that the low bits are transmitted in front, reading the received data by a processor;

and when the bit ordering mode of the written received data is that the high bits are sequentially arranged from left to right from the high bits to the low bits, and the bit receiving mode is that the high bits are transmitted in front, performing data conversion on the written received data, and reading the data subjected to the data conversion by a processor.

Further, the data conversion of the written received data includes the steps of:

exchanging high and low bits of the written received data;

and sequentially carrying out data displacement on the data after the high and low bit interchange, so that the highest bit of the data after the high and low bit interchange is moved to the highest bit of the receiving conversion register, and the lowest bit of the data after the high and low bit interchange is moved to the lowest bit of the receiving conversion register.

Further, the receiving the data and writing the received data into the receiving register includes the steps of:

receiving data through an SPI receiving port and transmitting the data to a receiving shift register;

and writing the data in the receiving displacement register into the receiving register byte by byte until the data receiving is completed.

Further, the writing the data in the receiving shift register into the receiving register byte by byte until the data receiving is completed includes the steps of:

enabling to receive first bit data of one byte in the received data, and updating the value of the received byte number counter when the value of the received byte number counter is equal to a preset value until the value of the received byte number counter is equal to the calculated byte number; the number of bytes is calculated according to the number of bits of the received data.

The invention also provides a sending device, which is characterized by comprising a processor, a memory and a computer program stored in the memory and capable of running on the processor, wherein the processor is used for executing the computer program stored in the memory to realize the operation executed by the SPI transmission control method.

Compared with the prior art, the SPI transmission control method, the sending equipment and the receiving equipment have the advantages that:

the invention realizes the functions of adjustable transmission digit and prior transmission of high-order data by configuring the bit width of the sending shift register or the receiving shift register and carrying out data conversion.

Drawings

The above features, technical features, advantages and implementations of an SPI transmission control method, a transmitting device and a receiving device will be further described in the following preferred embodiments in a clearly understandable manner with reference to the accompanying drawings.

FIG. 1 is a flow chart of one embodiment of a method for controlling SPI transmission in accordance with the present invention;

fig. 2 is a flowchart of another embodiment of an SPI transmission control method of the present invention;

FIG. 3 is a flow chart of another embodiment of a method for controlling SPI transmission of the present invention;

FIG. 4 is a schematic diagram of the structure of the SPI device of the present invention;

fig. 5 is a schematic diagram of the operation of the write pointer at the transmitting end of the SPI transmission control method of the present invention;

fig. 6 is a schematic diagram of the operation of the read pointer at the transmitting end of the SPI transmission control method according to the present invention;

fig. 7 is a flow chart of a count of a transmission bit counter of an SPI transmission control method of the present invention;

FIG. 8 is a flow chart of counting a byte counter of the SPI transmission control method according to the present invention;

fig. 9 is a flow chart of a group of data transmission count of an SPI transmission control method of the present invention;

fig. 10 is a flowchart of another embodiment of an SPI transmission control method of the present invention;

fig. 11 is a flowchart of another embodiment of an SPI transmission control method of the present invention;

fig. 12 is a flowchart of another embodiment of an SPI transmission control method of the present invention;

FIG. 13 is a diagram illustrating the operation of the write pointer at the receiving end of the SPI transmission control method according to the present invention;

FIG. 14 is a schematic diagram illustrating the operation of the read pointer at the receiving end of the SPI transmission control method according to the present invention;

fig. 15 is a schematic diagram of a data transmission waveform of an embodiment of an SPI transmission control method of the present invention;

fig. 16 is a diagram illustrating a data transmission waveform according to another embodiment of another SPI transmission control method according to the present invention.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

In particular implementations, the mobile clients described in embodiments of the present application include, but are not limited to, other portable devices such as mobile phones, laptops, or tablets having touch-sensitive surfaces (e.g., touch screen displays and/or touch pads).

The mobile client supports various applications, such as one or more of the following: a drawing application, a presentation application, a network creation application, a word processing application, a disc burning application, a spreadsheet application, a gaming application, a telephone application, a video conferencing application, an email application, an instant messaging application, an exercise support application, a photo management application, a digital camera application, a digital video camera application, a Web browsing application, a digital music player application, and/or a digital video player application.

In addition, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not intended to indicate or imply relative importance.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.

Fig. 1 shows an implementation flowchart of an SPI transmission control method of the present invention, which is applied to a transmitting end, and the SPI transmission control method includes the following steps:

s111, writing data to be sent into a sending register through a processor;

s112, when the bit ordering mode of the written data to be sent is that the high bit and the low bit are sequentially arranged from left to right and the bit sending mode is that the low bit data is transmitted in the front, writing the data to be sent into a sending buffer;

s113, when the written data to be sent have a digit ordering mode of high-order to low-order in sequence from left to right and a digit sending mode of high-order data is transmitted in front, performing data conversion on the written data to be sent through a sending data control module, and writing the data to be sent after the data conversion into a sending buffer;

s114 transmits the data to be transmitted in the transmission buffer byte by byte.

Fig. 2 shows an implementation flowchart of an SPI transmission control method of the present invention, which is applied to a transmitting end, and the SPI transmission control method includes the following steps:

s121, writing data to be sent into a sending register through a processor;

s122, when the bit ordering mode of the written data to be sent is that the high bits to the low bits are sequentially arranged from left to right, and the bit sending mode is that the low bits are transmitted in advance, writing the data to be sent into a sending buffer;

s123, when the bit ordering mode of the written data to be sent is from high to low and is sequentially ordered from left to right, and the bit sending mode is that high bit data is transmitted in advance, exchanging high and low bits of the data to be sent;

s124, sequentially carrying out data displacement on the data subjected to the high-low bit interchange, so that the highest bit of the data subjected to the high-low bit interchange is moved to the highest bit of the sending conversion register, and the lowest bit of the data subjected to the high-low bit interchange is moved to the lowest bit of the sending conversion register;

s125, writing the data to be transmitted after data conversion into a transmission buffer;

s126 transmits the data to be transmitted in the transmission buffer byte by byte.

Fig. 3 shows an implementation flowchart of an SPI transmission control method of the present invention, which is applied to a transmitting end, and the SPI transmission control method includes the following steps:

s131, writing data to be sent into a sending register through a processor;

s132, when the bit ordering mode of the written data to be sent is that the high bit and the low bit are sequentially arranged from left to right, and the bit sending mode is that the low bit data is transmitted in advance, writing the data to be sent into a sending buffer;

s133, when the bit ordering mode of the written data to be sent is that the high bits to the low bits are sequentially arranged from left to right and the bit sending mode is that the high bits are transmitted in the front, the written data to be sent is subjected to data conversion through the sending data control module, and the data to be sent after the data conversion is written into the sending buffer;

s134, transmitting the data to be transmitted with the bit ordering mode matched with the bit transmitting mode to an SPI output pin byte by byte under the control of a clock signal and a bit counter;

and S135, transmitting the data to be transmitted in the bit ordering mode and the bit transmission mode matched through the SPI output pin until the transmission is finished.

Specifically, as shown in fig. 4, the SPI device shown in fig. 4 can be used as a data transmitting end or a data receiving end. During sending, a CPU (i.e., the processor of the present invention) writes data into a sending register (32-bit wide), if the data is transmitted with low bits before, the data is directly sent into a sending buffer (i.e., tx _ fifo _ ctl shown in fig. 4) to occupy 4 address spaces, if the data is transmitted with high bits before, the data is sent into the sending buffer after high-low bit interchange and shift operations in a sending data control module, the writing and reading of the data in the sending buffer are controlled by a write/read pointer, then, according to the number of bits of the sent data, the number of bytes is calculated, such as 22 bits sent, i.e., 3 bytes, the data in the sending buffer is read byte by byte and sent into a sending shift register (8-bit wide), and finally, the data is sent to an SPI output pin (i.e., SPI _ out shown in fig. 4) in serial under the restriction of clock beats and a bit counter; if SPI is the master mode, can produce the synchronous clock, if is the slave mode, can only receive the clock passively; the presented effects are: it is set to transmit N bits of data, N clock cycles on the SPI clock pin (i.e., SPI _ mclk shown in fig. 4), and N bits of data on the SPI output pin.

With tx _ data _ ctl data translation, exemplary: the pre-transmitted original data, i.e. the data to be transmitted according to the present invention, is shown in table 1 below:

0

bit21

bit20

.

bit1

bit0

TABLE 1

If the high-order data is transmitted in the front, the data to be transmitted is subjected to high-order and low-order interchange, and the interchanged data to be transmitted is shown in the following table 2:

bit0

bit1

.

bit20

bit21

0

TABLE 2

The following table 3 shows the following steps of shifting the data in table 2, and placing the highest bit of the data to be transmitted to the lowest bit of the temporary storage register to obtain data to be transmitted after data conversion:

0

bit0

bit1

.

bit20

bit21

TABLE 3

And then the tx _ data _ ctl module writes the data to be transmitted after data conversion into a transmission buffer, and since the data are transmitted from the lowest bit, the first transmitted data after the above processing is bit21, and then bit20 … bit0, so that the function of transmitting the high-bit data before transmission is realized.

And during sending, controlling a read-write pointer:

one address space in the sending buffer is 8bit wide, the sending register is 32bit wide, so that the once-written data occupies 4 address spaces, and the once-written pointer wp (write point) writes + 4; i.e. the first set of data is in address 0-address 3 space, the second set of data is placed in address 4-address 7 space, and so on, the wp maximum depends on the size of the transmit buffer space; reading the data in the sending buffer and sending the data to a sending shift register for sending, wherein the sending shift register has 8bit wide, so that the data is read once, and a reading pointer rp (readpoint) + 1; the number of reads is determined by the number of transmission bits set, exemplary: 22-bit data is sent, the number of bytes is 3, so that the sending of a group of data is completed by reading for 3 times; the value of rp then jumps to the first address of the next set of data. Illustratively, if 3 bytes of data are sent, the write pointer operation is shown in FIG. 5, and if 3 bytes of data are sent, the read pointer operation is shown in FIG. 6. Data is sent to the transmission shift register under the control of the write/read pointer, and then the data to be sent in the transmission shift register is enabled to send the data to be sent to the SPI _ out (namely the SPI output pin of the invention) in series under the limitation of a clock beat and a digit counter.

Preferably, under the control of a clock signal and a bit number counter, transmitting data to be transmitted, which is matched with the bit number transmission mode in a bit number ordering mode, to the SPI output pin byte by byte includes the steps of:

when a clock signal is received, enabling a first bit data of one byte in the data to be sent, wherein the transmission bit ordering mode is matched with the bit sending mode, and updating the value of a transmission byte number counter when the value of the transmission bit number counter is equal to a preset value until the value of the transmission byte number counter is equal to the calculated byte number; the number of bytes is calculated according to the number of bits of the data to be sent.

In the following, the whole transmission process is briefly described as follows:

as shown in fig. 7, which is a flow chart of the counting of the transmission bit number counter, tran _ en is set to 1 when a transmission edge arrives, i.e. transmission is enabled, according to the configured working mode; the transmission is sent according to bytes, when resetting, the initial value of a bit counter is 8, when tran _ en is equal to 1, the first bit in one byte is started to be sent, the value of txcnt is reduced by 1, when the value of txcnt is equal to the value of (txstop +1), txlast is set to be 1, the last bit in one byte is sent, then txcnt is restored to the initial value, and the next byte is started to be sent.

As shown in fig. 8, which is a flow chart of counting of a byte number counter, a group of data includes 1-4 bytes, and when the last byte is sent, if the last bit of the byte is also sent, the whole group of data is sent completely. When txlast is 1, it indicates that all bits of a byte have been sent, at this time, txbyte _ cnt is added by 1, when txbyte _ cnt is equal to byte _ num, txbyte _ last is set to 1, the last byte data is sent, and then txbyte _ cnt recovers the initial value to start the sending of the next group of data; the byte _ num value is calculated from the set number of transmission bits.

Fig. 9 is a flow chart illustrating a transmission count of a set of data, including the steps of:

step 1: a configuration digit counter, which writes in the digits to be sent and calculates to obtain a byte _ num value; after the reset action is finished, loading the sending bit value into an ext _ txcnt register;

step 2: judging the value of ext _ txcnt, if ext _ txcnt > is 8, going to step 3; if ext _ txcnt <8, go to step 5;

and step 3: if ext _ txcnt > is 8, txstop is 0, when tran _ en is 1, the first bit of a byte is started to be sent, a bit is sent, the value of txcnt is reduced by 1, when the value of txstop is reduced to (txstop +1), txlast is 1, the last bit of a byte is sent completely, and then txbyte _ cnt +1 and ext _ txcnt-8 are obtained;

and 4, step 4: judging the value of the ext _ txcnt after subtracting 8 again, if the value is still larger than 8, returning to the step 3, and if the value is smaller than 8, going to the step 5;

and 5: judging the value size of ext _ txcnt, if ext _ txcnt <8, txstop is 8-ext _ txcnt, when tran _ en is 1, starting to send the first bit of a byte, sending a bit, and subtracting 1 from txcnt, when the value is subtracted to (txstop +1), txlast is 1, if txbyte _ last is 1 at the moment, the last bit of the last byte of a group of data is completely sent, namely a group of data is completely sent.

The invention can realize the arbitrary setting of the bit number of the SPI sending data between 1 bit and 32bit by configuring the bit width of the sending register and the sending shift register, supports the prior transmission of high/low bits of data by data conversion, has more free application, is suitable for the occasion of sending N-bit control pulse, and avoids the problems of complexity and difficult time sequence control of software programming GPIO analog clock and data.

Fig. 10 shows a flowchart of an implementation of an SPI transmission control method of the present invention, which is applied to a receiving end, and the SPI transmission control method includes the following steps:

s211 receiving data and writing the received data into a receiving register;

s212, when the bit ordering mode of the written received data is that the high bit and the low bit are sequentially arranged from left to right and the bit receiving mode is that the low bit is transmitted in front, reading the received data through the processor;

and S213, when the bit ordering mode of the written received data is that the high bit is arranged to the low bit and the bit receiving mode is that the high bit is transmitted in front, performing data conversion on the written received data, and reading the data subjected to the data conversion by the processor.

Fig. 11 shows a flowchart of an implementation of an SPI transmission control method of the present invention, which is applied to a receiving end, and the SPI transmission control method includes the following steps:

s221 receives data and writes the received data into a receiving register;

s222, when the bit ordering mode of the written received data is that the high bits and the low bits are sequentially arranged from left to right and the bit receiving mode is that the low bits are transmitted in front, reading the received data through a processor;

s223, when the bit ordering mode of the written received data is that the high bit and the low bit are sequentially arranged from left to right, and the bit receiving mode is that the high bit data is transmitted in advance, the written received data is exchanged with the low bit;

s224, sequentially carrying out data displacement on the data after the high and low bit interchange, so that the highest bit of the data after the high and low bit interchange is moved to the highest bit of the receiving conversion register, and the lowest bit of the data after the high and low bit interchange is moved to the lowest bit of the receiving conversion register;

s225 reads the data after data conversion by the processor.

Fig. 12 shows a flowchart of an implementation of an SPI transmission control method of the present invention, which is applied to a receiving end, and the SPI transmission control method includes the following steps:

s231, receiving data through the SPI receiving port and transmitting the data to the receiving shift register;

s232, writing the data in the receiving shift register into the receiving register byte by byte until the data receiving is finished;

s233, when the bit ordering mode of the written received data is from high to low is from left to right, the received data is read by the processor;

s234, when the bit ordering mode of the written received data is that the high bits to the low bits are sequentially arranged from left to right, and the bit receiving mode is that the high bits are transmitted in advance, the written received data is exchanged with the low bits;

s235 sequentially carrying out data displacement on the data subjected to the high-low bit interchange, so that the highest bit of the data subjected to the high-low bit interchange is moved to the highest bit of the receiving conversion register, and the lowest bit of the data subjected to the high-low bit interchange is moved to the lowest bit of the receiving conversion register;

s236 reads the data subjected to the data conversion by the processor.

Specifically, during receiving, data on a pin is sent to a receiving shift register, then written into a receiving buffer (namely rx _ fifo _ ctl shown in fig. 4) under the control of a write/read pointer, received for 3 times if 3 bytes of data are sent, and then sent to an rx _ data _ ctl module for data conversion, and if low bits are transmitted before, the data are directly sent to an RXREG to wait for being read by a CPU; if the high bit is transmitted before, the data is transmitted to RXRG after high bit and low bit interchange and shift, and waits for the reading of CPU. If the receiving end is the SPI architecture as shown in fig. 4, N-bit data transmission and reception under the SPI protocol can be implemented.

Through the data conversion of the rx _ data _ ctl module, the conversion mode is the same as that of the tx _ data _ ctl module, and the high and low bits are interchanged and shifted. Illustratively, the received raw data, i.e., the data received by the present invention, is as shown in table 1 below:

data received through the SPI _ in (i.e., the SPI reception port of the present invention) and written into rx _ fifo _ ctl is as shown in table 4 below:

0

bit0

bit1

.

bit20

bit21

TABLE 4

If the high order data is transmitted before, the received data is exchanged between high order and low order, and the received data after the exchange is as shown in the following table 5:

bit21

bit20

.

bit1

bit0

0

TABLE 5

Data shifting is performed on the data in table 5, the highest bit of the received data is placed to the lowest bit of the temporary storage register, and the received data after data conversion is obtained as shown in table 6 below, and the received data after data conversion has the same format as the data sent by the sending end and is then sent to RXREG:

0

bit21

bit20

.

bit1

bit0

TABLE 6

During receiving, the read-write pointer is controlled in such a way that a receiving shift register is 8-bit wide, after receiving a byte of data, the received data is written into rx _ fifo _ ctl to occupy an address space, the received data is put into an address 0, then wp +1 is carried out, the number of times of writing is determined by the number of bytes obtained by the data bit, if the number of bytes is 3, the receiving of one group of data is finished after 3 times of writing, and then the wp pointer jumps to the first address of the next group of data; after the data are received, the data are sent to an RXRG register, the CPU is waited for reading, the RXRG register is 32 bits, so that the data are read once, 4 address space data are read, and the rp pointer +4, because the rx _ fifo _ ctl is cleared when being reset, the numerical value in the address space which is not written is 0, and the numerical value is not influenced when being read.

Illustratively, if 3 bytes of data are received, the write pointer operation is shown in FIG. 13, and if 3 bytes of data are received, the read pointer operation is shown in FIG. 14. Data is written to rx _ fifo _ ctl under write/read pointer control.

Preferably, the writing the data in the receiving shift register into the receiving register byte by byte until the data receiving is completed includes the steps of:

The invention can realize the arbitrary setting of the digit of the SPI received data between 1 bit and 32bit by configuring the bit width of the receiving register and the receiving shift register, supports the forward transmission of the high/low digit of the data by data conversion, has more free application, is suitable for the occasion of receiving N-digit control pulse, and avoids the problems of complexity and difficult time sequence control of software programming GPIO analog clock and data.

For example, as shown in fig. 15, the transmitting end transmits 6-bit data:

ext _ txcnt is 0x6, i.e., 6bit, and when ext _ txcnt <8, txstop is 8-ext _ txcnt; when tran _ en is equal to 1, txcnt is equal to txcnt-1, and when the txcnt value is 1+ txstop, txlast is set to 1, because 6 bits are transmitted, byte _ num is equal to txbyte _ cnt is equal to 0, txbyte _ last is always 1, and when txbyte _ last and txlast are both 1, that is, the last bit of the last byte is transmitted, a group of data transmission ends, and tip is equal to 0.

For example, as shown in fig. 16, the transmitting end sends 22-bit data:

when ext _ txcnt is 0x16, that is, 22bit, and ext _ txcnt > is 8, txstop is 0; when tran _ en is 1, txcnt-1, when the value is txcnt value 1+ txstop, txlast is set to 1, when txlast is 1, txbyte _ cnt +1, when txbyte _ cnt is byte _ num, txbyte _ last is set to 1; when ext _ txcnt <8, txstop is 8-ext _ txcnt, and when txcnt is (1+ txstop), txlast is set to 1, and when txbyte _ last and txlast are both 1, transmission ends, tip is 0.

In some application scenes, signals with specified digits, such as control signals or RGB signals, need to be transmitted and received, a novel SPI module is used, the mode of simulating clocks and signals through a software programming GPIO port can be replaced, an SPI working mode, a transmitting and receiving digit counter and a high/low digit selection control bit are configured, namely N-period clock signals can be output on an SPI clock pin, and N-digit data can be output through an SPI data pin; if the same SPI module is arranged on the slave device, the communication of multi-bit data can be realized under the same configuration, and the data transmission rate is improved.

It will be apparent to those skilled in the art that, for convenience and brevity of description, the foregoing division of program modules is merely exemplary, and in practice, the above distribution of functions may be performed by different program modules, that is, the internal structure of the apparatus may be divided into different program units or modules to perform all or part of the above-described functions. Each program module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one processing unit, and the integrated unit may be implemented in a form of hardware, or may be implemented in a form of software program unit. In addition, the specific names of the program modules are only used for distinguishing the program modules from one another, and are not used for limiting the protection scope of the application.

The above only illustrates that the sender performs data transmission, and the receiver performs data reception according to the same principle as the sender performs data transmission, each reception operation is completed in rxsample _ en (set at 1 when the receiving edge arrives according to the configuration of the operating mode), and the number of bits to be received by the receiving bit counter is configured, so that all bits are received, and the reception of a group of data is finished.

In one embodiment of the invention, a transmitting device comprises a processor and a memory, wherein the memory is used for storing a computer program; and a processor, configured to execute the computer program stored in the memory, and implement the SPI transmission control method in any one of the corresponding method embodiments of fig. 1-10.

The sending device can be a desktop computer, a notebook, a palm computer, a tablet computer, a mobile phone, a man-machine interaction screen and the like. The sending device may include, but is not limited to, a processor, a memory. Those skilled in the art will appreciate that the figures are merely examples of a sending device and do not constitute a limitation of a sending device and may include more or less components than those shown, or combine certain components, or different components, such as: the sending device may also include input/output ports, display devices, network access devices, communication buses, communication ports, and the like. A communication port and a communication bus, and may further include an input/output port, wherein the processor, the memory, the input/output port and the communication port are in communication with each other via the communication bus. The memory stores a computer program, and the processor is configured to execute the computer program stored in the memory to implement the SPI transmission control method in any one of the corresponding method embodiments of fig. 1 to 10.

In one embodiment of the invention, a receiving device comprises a processor and a memory, wherein the memory is used for storing a computer program; and a processor, configured to execute the computer program stored in the memory, and implement the SPI transmission control method in any one of the corresponding method embodiments of fig. 11 to 14.

The receiving device can be a desktop computer, a notebook, a palm computer, a tablet computer, a mobile phone, a man-machine interaction screen and the like. The receiving device may include, but is not limited to, a processor, a memory. Those skilled in the art will appreciate that the figures are merely examples of a receiving device and do not constitute a limitation of a receiving device and may include more or fewer components than those shown, or some components may be combined, or different components, such as: the receiving device may also include input/output ports, display devices, network access devices, communication buses, communication ports, and the like. A communication port and a communication bus, and may further include an input/output port, wherein the processor, the memory, the input/output port and the communication port are in communication with each other via the communication bus. The memory stores a computer program, and the processor is configured to execute the computer program stored in the memory to implement the SPI transmission control method in any one of the corresponding method embodiments of fig. 11 to 14.

The Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory may be an internal storage unit of the terminal device, such as: hard disk or memory of the terminal device. The memory may also be an external storage device of the terminal device, such as: the terminal equipment is provided with a plug-in hard disk, an intelligent memory Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) and the like. Further, the memory may also include both an internal storage unit and an external storage device of the terminal device. The memory is used for storing the computer program and other programs and data required by the terminal device. The memory may also be used to temporarily store data that has been output or is to be output.

A communication bus is a circuit that connects the described elements and enables transmission between the elements. For example, the processor receives commands from other elements through the communication bus, decrypts the received commands, and performs calculations or data processing according to the decrypted commands. The memory may include program modules such as a kernel (kernel), middleware (middleware), an Application Programming Interface (API), and applications. The program modules may be comprised of software, firmware or hardware, or at least two of the same. The input/output port forwards commands or data entered by a user through the input/output port (e.g., sensor, keyboard, touch screen). The communication port connects the terminal equipment with other network equipment, user equipment and a network. For example, the communication port may be connected to a network by wire or wirelessly to connect to external other network devices or user devices. The wireless communication may include at least one of: wireless fidelity (WiFi), Bluetooth (BT), Near Field Communication (NFC), Global Positioning Satellite (GPS) and cellular communications, among others. The wired communication may include at least one of: universal Serial Bus (USB), high-definition multimedia port (HDMI), asynchronous transfer standard port (RS-232), and the like. The network may be a telecommunications network and a communications network. The communication network may be a computer network, the internet of things, a telephone network. The terminal device may be connected to the network via a communication port, and a protocol used by the terminal device to communicate with other network devices may be supported by at least one of an application, an application programming port (API), middleware, a kernel, and a communication port.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or recited in detail in a certain embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some ports, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated modules/units may be stored in a storage medium if they are implemented in the form of software functional units and sold or used as separate products. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by sending instructions to relevant hardware through a computer program, where the computer program may be stored in a storage medium, and when the computer program is executed by a processor, the steps of the method embodiments may be implemented. Wherein the computer program may be in source code form, object code form, an executable file or some intermediate form, etc. The storage medium may include: any entity or device capable of carrying the computer program, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signal, telecommunication signal, software distribution medium, etc. It should be noted that the content of the storage medium may be increased or decreased as appropriate according to the requirements of legislation and patent practice in the jurisdiction, for example: in certain jurisdictions, in accordance with legislation and patent practice, computer-readable storage media do not include electrical carrier signals and telecommunications signals.

It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A SPI transmission control method is characterized in that the method is applied to a sending end and comprises the following steps:

writing data to be sent into a sending register through a processor; the transmission register is 32bit wide;

when the written data to be sent are sequentially arranged from left to right in a digit ordering mode from high to low and the digit sending mode is that low-order data are transmitted in advance, writing the data to be sent into a sending buffer; the sending buffer occupies 4 address spaces, and each address space is 8 bits wide;

transmitting the data to be transmitted in the transmission buffer byte by byte;

the method for transmitting the data to be transmitted in the transmission buffer byte by byte comprises the following steps:

transmitting the data to be transmitted with the digit sequencing mode matched with the digit transmission mode to an SPI output pin byte by byte under the control of a clock signal and a digit counter;

transmitting the data to be transmitted with the bit ordering mode matched with the bit transmitting mode to the SPI output pin byte by byte under the control of a clock signal and a bit counter specifically comprises the following steps:

under the control of a write/read pointer, transmitting data in a transmission buffer to a transmission shift register with 8bit width, and under the limitation of clock beat and a bit counter, serially transmitting the data to be transmitted to an SPI output pin;

transmitting the data to be transmitted, which is matched with the digit ordering mode and the digit transmitting mode, through an SPI output pin until the transmission is finished;

transmitting the data to be transmitted with the bit ordering mode matched with the bit transmitting mode through an SPI output pin until the transmission is completed, wherein the data to be transmitted comprises the following steps:

when a clock signal is received, enabling to send first bit data of one byte in the data to be sent, wherein the bit ordering mode is matched with the bit sending mode, and updating the value of a sending byte number counter when the value of the sending bit number counter is equal to a preset value until the value of the sending byte number counter is equal to the number of calculated bytes; the number of bytes is calculated according to the number of bits of the data to be sent;

the data conversion of the written data to be sent by the data sending control module comprises the following steps:

exchanging high and low bits of the data to be sent;

2. A SPI transmission control method is characterized in that the method is applied to a receiving end and comprises the following steps:

receiving data and writing the received data into a receive register; the receive register is 32bit wide;

the receiving data and writing the received data to the receive register includes the steps of:

receiving data through an SPI receiving port and transmitting the data to a receiving shift register; the receiving shift register is 8bit wide;

writing the data in the receiving shift register into the receiving register byte by byte until the data receiving is completed;

the writing the data in the receiving shift register into the receiving register byte by byte specifically includes:

under the control of the write/read pointer, writing the data in the receiving shift register into the receiving buffer and then sending the data to the receiving register;

the step of writing the data in the receiving shift register into the receiving buffer and then sending the data to the receiving register under the control of the write/read pointer comprises the following steps:

enabling to receive first bit data of one byte in the received data, and updating the value of the received byte number counter when the value of the received byte number counter is equal to a preset value until the value of the received byte number counter is equal to the calculated byte number; the number of bytes is calculated according to the number of bits of the received data;

when the bit ordering mode of the written received data is that the high bits are sequentially arranged from left to right from the high bits to the low bits, and the bit receiving mode is that the high bits are transmitted in front, the written received data is subjected to data conversion through the received data control module, and the data subjected to data conversion is read through the processor;

the data conversion of the written reception data includes the steps of:

exchanging high and low bits of the written received data;

3. A transmission apparatus comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, the processor being configured to execute the computer program stored in the memory to implement the operation performed by the SPI transmission control method according to claim 1.

4. A transmission apparatus comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, the processor being configured to execute the computer program stored in the memory to implement the operation performed by the SPI transmission control method according to claim 2.