CN103794244B - A kind of phase transition storage reading circuit based on SPI interface and method - Google Patents
A kind of phase transition storage reading circuit based on SPI interface and method Download PDFInfo
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Abstract
The present invention provides a kind of phase transition storage reading circuit based on SPI interface and method, including: address register receives external address by turn；When (LSB+A) position receives address, pre-read 2M+ABit data also latches；When LSB bit receives address, from 2M+APosition pre-reads data decodes out 2MPosition target data also latches, and OPADD is from increasing signal simultaneously；Move behind address, if (LSB+A) bit register overturns, then read next group data, otherwise, it is not read inside described phase transition storage；Output data, and export next address from increasing signal.The data that may need the address being read all are read in advance by the present invention by carrying previous or several clock cycle, the most again by the data of corresponding destination address are exported by true address decoding, the phase transition storage internal actual reading time can be increased, thus improve the message transmission rate of phase transition storage based on SPI interface, and then improve the final performance of chip.
Description
Technical field
The present invention relates to microelectronics domain, particularly relate to a kind of phase transition storage reading circuit based on SPI interface
And method.
Background technology
Phase transition storage (Phase Change Memory, PCM, PCRAM) is generally referred to as based on certain chalcogenide compound
The random access memory of thin film.It is a kind of novel nonvolatile semiconductor memory, utilizes the phase transformation being worked into nano-scale
The material resistance states different when polycrystalline state (material is low resistive state) is from amorphous state (material is high-impedance state) is to realize number
According to storage.Owing to its operation voltage is low, reading speed is fast, can write wiping speed be significantly faster than flash memory with bit manipulation, and tired
Characteristic is more excellent, it is possible to the circulation realizing more than one hundred million times is erasable, and manufacturing process is simple and compatible with the most ripe CMOS technology, energy
Enough it is easy to be contracted to its memory element less size, is considered most possibly to substitute flash memory in the near future
(Flash) main flow nonvolatile memory is become.
The full name of SPI interface is " Serial Peripheral Interface ", means serial peripheral interface, is
First Motorola defines in its MC68HCXX series processors.SPI interface is mainly used in EEPROM, FLASH, in real time
Clock, a/d converter, also between digital signal processor and digital signal decoder.SPI interface is as a kind of synchronous serial
Data transmission interface, its hardware is actually two simple shift registers, enables signal what main device produced from device
With under shift pulse, step-by-step is transmitted, high-order front, and low level is rear, for full-duplex communication, data transmission bauds on the whole than
I2C bus wants fast, and speed can reach a few Mbps.
In prior art, the reading method of phase transition storage based on SPI interface is as follows:
It is illustrated in figure 1 1K bits phase transition storage reading method sequential chart based on SPI interface in prior art, receives
After the reading instruction of main frame, memorizer reads data under the shift pulse SP of main frame controls, and depends in the forward position of shift pulse SP
Secondary accept the destination address that main frame sends, receiving last destination address position A<0>time, memory inside starts to read
Operation, and start to start the data that output storage is read by turn at the tailing edge of same shift pulse SP, thus complete to read behaviour
Make.In this process, memory inside carries out the forward position being limited in shift pulse SP actual time of read operation and arrives tailing edge
In half period, the especially forward position of first shift pulse SP is only half of external clock SCK to the half period of tailing edge
Cycle.But, phase transition storage is as a kind of high density non-volatility memorizer, and its readout time is by bit line parasitic capacitance
Impact, the scale of memory array is the biggest, and its bitline length is the longest, and ghost effect is more serious, and its readout time also can increase, and enters
And limit the data transmission bauds of SPI interface.
Therefore, it is achieved improve the data transmission bauds of SPI interface on the premise of identical phase transition storage core capabilities, to base
Phase transition storage reading method in SPI interface is optimized, and then the final performance improving chip becomes people in the art
Member's problem demanding prompt solution.
Summary of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of phase transformation based on SPI interface
Memory readout circuit and method, being used for solving in prior art phase transition storage because of bit line parasitic capacitance affects SPI interface number
Problem according to transmission speed.
For achieving the above object and other relevant purposes, the present invention provides a kind of phase transition storage based on SPI interface to read
Going out circuit, described phase transition storage reading circuit based on SPI interface at least includes:
N bit address depositor, 2M+APosition pre-reads data latch, address decoder and 2 is read in A positionMPosition output data register
Device；Described N bit address depositor, needs the address information of operation for latching phase transition storage；
Described 2M+APosition pre-reads data latch is connected to described N bit address depositor and address decoder is read in described A position,
When described N bit address depositor sends the first control signal, described 2M+APosition pre-reads data latch starts to pre-read and latch can
The 2 of energy addressM+ABit data, reads the decoded signal of address decoder output from 2 further according to described A positionM+APosition pre-reads data selects
Take 2MPosition target data, and after completing data decimation, send shifting behind the address of the signal described N bit address depositor of control；
Described A position is read address decoder and is connected to described N bit address depositor, when described N bit address depositor sends the
During two control signals, described A position is read address decoder and is started decoding, and decoded signal is exported to described 2M+APosition pre-reads data
Latch；
Described 2MPosition output data register is connected to described 2M+APosition pre-reads data latch, for latching 2 selectedM
Position target data.
Preferably, the lowest order of described N bit address depositor is LSB bit, and highest order is MSB position.
Preferably, the method for the data acquisition of described N bit address depositor series connection input, input sequence from a high position to low
Position.
Preferably, described phase transition storage has N bit address, M-bit data width, and phase transition storage capacity is 2M+N。
For achieving the above object and other relevant purposes, the present invention provides a kind of phase transition storage based on SPI interface to read
Going out method, described phase transition storage reading method based on SPI interface comprises the following steps:
Step one: phase transition storage receives reading instruction, enters read mode, and N bit address depositor starts to receive by turn
The address of outside input；
Step 2: when (LSB+A) position of described N bit address depositor receives external address, described phase transition storage
Inside starts to read by N-1 position to determined by A bit address 2M+APosition pre-reads data, and it is latched in 2M+APosition pre-reads data lock
In storage, wherein M is data width；
Step 3: when the LSB bit of described N bit address depositor receives external address, A position is read address decoder and is started
Decoding, by the control of decoded signal from 2M+APosition pre-reads data chooses 2MPosition target data also exports to 2MPosition output data are posted
Storage, and OPADD is from increasing signal, target data passes through described 2MPosition output data register output phase transition storage；
Step 4: after described N bit address depositor receives address increasing signal certainly, the ground in described N bit address depositor
Location adds 1；
Step 5: after the address in described N bit address depositor adds 1, if (LSB+A) bit register overturns, then
Start inside described phase transition storage to read by N-1 position to determined by A bit address 2M+ABit data, and it is latched in described
2M+AIn the pre-reads data latch of position；Otherwise, it is not read inside described phase transition storage；
Step 6: read the decoded signal of address decoder according to described A position, by 2MPosition target data output is to described 2MPosition
Output data register, and export next address from increasing signal.
Preferably, reading instruction described in step one is external strobe signal.
Preferably, described phase transition storage is read data manipulation for the first time and is started from receiving A bit address, reading afterwards
Any moment before can extremely exporting next data byte after the increment operator of address according to operation completes.
As it has been described above, the phase transition storage reading circuit based on SPI interface of the present invention and method, there is following useful effect
Really: the present invention provide phase transition storage reading circuit based on SPI interface and method, by carry previous or several time
The data that may need the address being read all are read by the clock cycle in advance, the most again by decoding true address
By the data output of corresponding destination address, the phase transition storage internal actual reading time can be increased, thus improve and connect based on SPI
The message transmission rate of the phase transition storage of mouth, and then improve the final performance of chip.
Accompanying drawing explanation
Fig. 1 is shown as 1K bits phase transition storage reading method sequential based on SPI interface of the prior art signal
Figure.
Fig. 2 is shown as the phase transition storage reading circuit schematic diagram based on SPI interface of the present invention.
Fig. 3 is shown as the phase transition storage reading method schematic diagram based on SPI interface of the present invention.
Fig. 4 and Fig. 5 is shown as 1K bits phase transition storage reading method sequential based on the SPI interface signal of the present invention
Figure.
Element numbers explanation
1 phase transition storage reading circuit based on SPI interface
11 N bit address depositors
12 2M+APosition pre-reads data latch
Address decoder is read in 13 A positions
14 2MPosition output data register
The figure place of N address register
M data width
A reads address decoder figure place
SCK external clock
CS_ gating signal
SI input signal
SO output signal
SP shift pulse
Detailed description of the invention
Below by way of specific instantiation, embodiments of the present invention being described, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also be by the most different concrete realities
The mode of executing is carried out or applies, the every details in this specification can also based on different viewpoints and application, without departing from
Various modification or change is carried out under the spirit of the present invention.
Refer to Fig. 2～Fig. 5.It should be noted that the diagram provided in the present embodiment illustrates this most in a schematic way
The basic conception of invention, the most graphic in package count time only display with relevant assembly in the present invention rather than is implemented according to reality
Mesh, shape and size are drawn, and during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its
Assembly layout kenel is likely to increasingly complex.
As in figure 2 it is shown, the present invention provides a kind of phase transition storage reading circuit 1 based on SPI interface, described based on SPI
The phase transition storage reading circuit 1 of interface at least includes:
N bit address depositor 11,2M+APosition pre-reads data latch 12, address decoder 13 and 2 is read in A positionMPosition output number
According to depositor 14.
Described N bit address depositor 11, needs the address information of operation for latching phase transition storage；Described N bit address
The lowest order of depositor is LSB bit, and N position is MSB position；The method of the data acquisition series connection input of described N bit address depositor,
Input sequence is from a high position to low level.
Wherein N is address size；Figure place N of address register can be set according to actual needs, in the present embodiment,
Address size N is set as 7, i.e. N=7, and address bit is respectively A<0>～A<6>, totally 7 bit address, lowest order LSB is A<0>, the highest
Position MSB be A<6>, the input sequence of address is followed successively by A<6>, A<5>, A<4>... A<0>.
Described 2M+APosition pre-reads data latch 12 is connected to described N bit address depositor 11 and address decoding is read in described A position
Device 13, when described N bit address depositor 11 sends the first control signal, described 2M+APosition pre-reads data latch 12 starts pre-
Read and latch the 2 of possible addressM+ABit data, reads the decoded signal of address decoder 13 output from 2 further according to described A positionM+APosition
Pre-reads data is chosen 2MPosition target data, and after completing data decimation, send the signal described N bit address depositor 11 of control
Address after move.
In the present embodiment, data width M is set as 3, and described A position is read address decoder 13 and is set as 1.Such as Fig. 2 institute
Showing, when the A<1>position of 7 bit address depositors 11 receives external address, N bit address depositor 11 sends the first control signal
16 pre-reads data latch 12 are made to start to pre-read and latch 16 bit data of possible address, further according to 1 reading address decoder
The decoded signal of 13 outputs chooses 8 target datas from 16 pre-reads data, and sends signal control after completing data decimation
Move after making the address of described 7 bit address depositors 11.
Described A position is read address decoder 13 and is connected to described N bit address depositor 11, when described N bit address depositor 11
When sending the second control signal, described A position is read address decoder 13 and is started decoding, and decoded signal is exported to described 2M+APosition
Pre-reads data latch 12.
In the present embodiment, it is 1 reading address decoder that address decoding circuitry 13 is read in described A position, when 7 bit address decoders
When the A<0>position of 11 receives external address, 1 reading address decoder 13 starts decoding, selects 8 from 16 pre-reads data
Position target data.
Described 2MPosition output data register 14 is connected to described 2M+APosition pre-reads data latch 12, chooses for latch
2 gone outMPosition target data.
In the present embodiment, described 2MPosition output data register 14 is 8 output data register, is used for latching target
8 target datas of address.
Described phase transition storage has N bit address, M-bit data width, and phase transition storage capacity is 2M+N.Described phase transformation is deposited
Reservoir can be random capacity, and it reads address decoder figure place and data width can also be set as arbitrarily meeting application requirement
Value, in the present embodiment, the address size N of described phase transition storage is set as 7, and data width M is set as 3, phase change memory
Device capacity is 1K bits.
As shown in Fig. 3～Fig. 5, the present invention also provides for a kind of phase transition storage reading method based on SPI interface, described base
Phase transition storage reading method in SPI interface comprises the following steps:
Step one: phase transition storage receives reading instruction, enters read mode, and N bit address depositor starts to receive by turn
The address of outside input.
Described reading instruction is external strobe signal CS_, and as shown in Figures 4 and 5, when gating signal CS_ is low, phase transformation is deposited
Reservoir enters read mode.
In the present embodiment, 7 bit address depositors selected by address register, and address bit is respectively A<0>～A<6>, totally 7
Address, lowest order LSB is A<0>, highest order MSB is A<6>；The input sequence of address is followed successively by A<6>, A<5>, A<4>... A<
0>。
Step 2: when (LSB+A) position of described N bit address depositor receives external address, described phase transition storage
Inside starts to read by N-1 position to determined by A bit address 2M+APosition pre-reads data, and it is latched in 2M+APosition pre-reads data lock
In storage, wherein M is data width；
In the present embodiment, A is set as 1, and target data width M is set as 3；Lowest order LSB is the 0th, i.e. A<0>position,
Pre-reads data latch is 16.As shown in Figures 4 and 5, as the 1st A<1 of 7 bit address depositors>receive external address
Time, the forward position of first shift pulse SP comes, and system reads the 1st shift pulse SP, and the inside of phase transition storage starts
Read the 6th 16 pre-reads data determined to the 1st bit address, and these 16 pre-reads data are latched in 16 pre-reads data locks
In storage.
Step 3: when the LSB bit of described N bit address depositor receives external address, A position is read address decoder and is started
Decoding, by the control of decoded signal from 2M+APosition pre-reads data chooses 2MPosition target data also exports to 2MPosition output data are posted
Storage, and OPADD is from increasing signal, target data passes through described 2MPosition output data register output phase transition storage.
In the present embodiment, reading address decoder is 1 reading address decoder, and output data storage is that 8 bit data are deposited
Reservoir.As it is shown on figure 3, as the lowest order LSB(A<0>position of 7 bit address depositors) when receiving external address, read address for 1 and translate
Code device receives instruction and starts to decode address, 1 reading address decoder by 8 bit data corresponding to destination address from 16
Translating in the pre-reads data of position, 8 target datas export from 16 pre-reads data latch to 8 output data register,
OPADD is from increasing signal simultaneously, and 8 target datas are by described 8 output data register output phase transition storages.
Step 4: after described N bit address depositor 11 receives address increasing signal certainly, in described N bit address depositor
Address adds 1, moves 1 after destination address.
Step 5: after the address in described N bit address depositor adds 1, if (LSB+A) bit register overturns, then
Start inside described phase transition storage to read by N-1 position to determined by A bit address 2M+ABit data, and it is latched in described
2M+AIn the pre-reads data latch of position；Otherwise, it is not read inside described phase transition storage.
In the present embodiment, after the address in 7 bit address depositors of phase transition storage increases 1, if A<1>bit register
Overturn, then as it is shown in figure 5, start inside phase transition storage to read by the 6th to 16 figure places determined by the 1st bit address
According to, and be latched in 16 pre-reads data latch, i.e. during phase transition storage exports the 1st 8 target datas, the
2 shift pulses produce, and the forward position of described 2nd shift pulse starts to read next group data, and shifts arteries and veins at described 2nd
Tailing edge (namely the A<0>position of the 2nd group address receives external address) the output data of punching；Otherwise, the most as shown in Figure 4,16
Pre-reads data is by A<6>to A<1>6 bit address determine, after the address of 7 bit address depositors increases 1, A<1>position turns over
Turn, i.e. determine that the address of 16 pre-reads data does not changes, be not read inside phase transition storage, connect at A<0>position
Receive after external address the data of output still for front 8 destination addresses once decoding gained, until A after address increases 1 next time <
1 > depositor occurs upset just to produce the 2nd shift pulse, carries out the reading of next group data.
Step 6: read the decoded signal of address decoder 13 according to described A position, by 2MPosition target data output is to described 2M
Position output data register 14, and export next address from increasing signal.
After the increment operator of address, regardless of whether read next group data, all open after A<0>position receives external address
Open 1 reading address decoder, export 8 target datas, and export next address from increasing signal, and so forth.
Described phase transition storage is read data manipulation for the first time and is started from receiving A bit address, reading data manipulation afterwards
Any moment before can extremely exporting next data byte after the increment operator of address completes.In the present embodiment, for the first time
The operation of reading data starts from A<1>position and receives address external signal, and reading data manipulation afterwards starts from next data
Byte exports front 3 clock cycle.
By above operational approach, phase transition storage reading method based on SPI interface with in prior art is compared (such as figure
Shown in 1), the first time actual reading time within phase transition storage is increased to 1.5 displacements by 0.5 shift pulse SP time
The pulse SP time, before reading data time afterwards extremely exports next data byte after also can being set in address increment operator
Any moment completes, and data read time is greatly increased, thus improves the data transmission speed of phase transition storage based on SPI interface
Rate, and then improve the final performance of chip.
In sum, the present invention provide phase transition storage reading circuit based on SPI interface and method by advance one
The data that may need the address being read all are read by individual or several clock cycle in advance, pass through the most again
To true address decoding by the data output of corresponding destination address, the phase transition storage internal actual reading time can be increased, from
And improve the message transmission rate of phase transition storage based on SPI interface, and then improve the final performance of chip.So, this
Bright effectively overcome various shortcoming of the prior art and have high industrial utilization.
The principle of above-described embodiment only illustrative present invention and effect thereof, not for limiting the present invention.Any ripe
Above-described embodiment all can be modified under the spirit and the scope of the present invention or change by the personage knowing this technology.Cause
This, have usually intellectual such as complete with institute under technological thought without departing from disclosed spirit in art
All equivalences become are modified or change, and must be contained by the claim of the present invention.
Claims (7)
1. a phase transition storage reading circuit based on SPI interface, it is characterised in that described phase transformation based on SPI interface is deposited
Reservoir reading circuit at least includes:
N bit address depositor, 2M+APosition pre-reads data latch, address decoder and 2 is read in A positionMPosition output data register；
Described N bit address depositor, needs the address information of operation for latching phase transition storage；
Described 2M+APosition pre-reads data latch is connected to described N bit address depositor and address decoder is read in described A position, works as institute
State N bit address depositor when sending the first control signal, described 2M+APosition pre-reads data latch starts to pre-read and latch possibly
The 2 of locationM+ABit data, reads the decoded signal of address decoder output from 2 further according to described A positionM+APosition pre-reads data chooses 2M
Position target data, and after completing data decimation, send shifting behind the address of the signal described N bit address depositor of control, wherein, can
Can address be the address that possible need to be read；
Described A position is read address decoder and is connected to described N bit address depositor, when described N bit address depositor sends the second control
During signal processed, described A position is read address decoder and is started decoding, and decoded signal is exported to described 2M+APosition pre-reads data latches
Device；
Described 2MPosition output data register is connected to described 2M+APosition pre-reads data latch, for latching 2 selectedMPosition mesh
Mark data.
Phase transition storage reading circuit based on SPI interface the most according to claim 1, it is characterised in that: ground, described N position
The lowest order of location depositor is LSB bit, and highest order is MSB position.
Phase transition storage reading circuit based on SPI interface the most according to claim 1, it is characterised in that: ground, described N position
The data acquisition of the location depositor method of series connection input, input sequence is from a high position to low level.
Phase transition storage reading circuit based on SPI interface the most according to claim 1, it is characterised in that: described phase transformation
Memorizer has N bit address, M-bit data width, and phase transition storage capacity is 2M+N。
5. a phase transition storage reading method based on SPI interface, it is characterised in that described phase transformation based on SPI interface is deposited
Reservoir reading method comprises the following steps:
Step one: phase transition storage receives reading instruction, enters read mode, and N bit address depositor starts to receive by turn outside
The address of input；
Step 2: when (LSB+A) position of described N bit address depositor receives external address, inside described phase transition storage
Start to read by N-1 position to determined by A bit address 2M+APosition pre-reads data, and it is latched in 2M+APosition pre-reads data latch
In, wherein M is data width；
Step 3: when the LSB bit of described N bit address depositor receives external address, A position is read address decoder and is started to translate
Code, by the control of decoded signal from 2M+APosition pre-reads data chooses 2MPosition target data also exports to 2MPosition output data register
Device, and OPADD is from increasing signal, target data passes through described 2MPosition output data register output phase transition storage；
Step 4: after described N bit address depositor receives address increasing signal certainly, the address in described N bit address depositor adds
1, carry out the reading of next group data；
Step 5: after the address in described N bit address depositor adds 1, if (LSB+A) bit register overturns, then described
Start inside phase transition storage to read by N-1 position to determined by A bit address 2M+ABit data, and it is latched in described 2M+APosition
In pre-reads data latch；Otherwise, it is not read inside described phase transition storage；
Step 6: read the decoded signal of address decoder according to described A position, by 2MPosition target data output is to described 2MPosition output
Data register, and export next address from increasing signal.
Phase transition storage reading method based on SPI interface the most according to claim 5, it is characterised in that: in step one
Described reading instruction is external strobe signal.
Phase transition storage reading method based on SPI interface the most according to claim 5, it is characterised in that: described phase transformation
Memorizer is read data manipulation for the first time and is started from receiving A bit address, and reading data manipulation afterwards can be in address from increasing behaviour
Any moment before extremely exporting next data byte after work completes.
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| US7788438B2 (en) * | 2006-10-13 | 2010-08-31 | Macronix International Co., Ltd. | Multi-input/output serial peripheral interface and method for data transmission |
| CN110289037B (en) * | 2019-06-26 | 2021-04-13 | 中国科学院上海微系统与信息技术研究所 | Nonvolatile memory read circuit and read method |
| CN112445742A (en) * | 2019-09-04 | 2021-03-05 | 北京君正集成电路股份有限公司 | Method for automatically identifying address width |
| CN111061671B (en) * | 2019-12-13 | 2021-08-17 | 上海灵动微电子股份有限公司 | SPI transmission control method, sending equipment and receiving equipment |
| CN115954024B (en) * | 2023-03-14 | 2023-06-02 | 长鑫存储技术有限公司 | Decoder and decoding method thereof |
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| US20070097760A1 (en) * | 2005-11-03 | 2007-05-03 | Trinh Stephen T | Compact column redundancy CAM architecture for concurrent read and write operations in multi-segment memory arrays |
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