CN111044886B - DDR2/3 PHY BIST data channel test vector generation method - Google Patents
DDR2/3 PHY BIST data channel test vector generation method Download PDFInfo
- Publication number
- CN111044886B CN111044886B CN201911252691.3A CN201911252691A CN111044886B CN 111044886 B CN111044886 B CN 111044886B CN 201911252691 A CN201911252691 A CN 201911252691A CN 111044886 B CN111044886 B CN 111044886B
- Authority
- CN
- China
- Prior art keywords
- data
- bit
- test
- phy
- test vector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3187—Built-in tests
Abstract
The invention discloses a DDR2/3 PHY BIST data channel test vector generation method, which comprises the following steps: (1) selecting an LFSR structure, and driving the LFSR structure to generate a pseudo-random number by using a low-frequency clock; (2) interleaving and selecting a shift register value in an LFSR structure as test data; (3) and combining the test data to construct a final test vector. The invention has simple structure and easy realization, reduces the BIST operation frequency and reduces the power consumption under the condition of meeting the test requirement.
Description
Technical Field
The invention belongs to the technical field of integrated circuit testability design, and relates to a method for generating DDR2/3 PHY BIST data channel test vectors.
Background
The purpose of integrated circuit testing is to detect defects generated during manufacturing, and built-in self test (BIST) is an important method for design for testability. The BIST test principle is that test vectors are generated inside a circuit, and test results are analyzed and judged. Pseudo-random test generation is a popular test generation method in BIST technology.
And the DDR2/3 PHY data channel test vector is transmitted to IO through the data transmitting channel and returned through the data receiving channel, and the returned result is compared with the initial test vector to complete the BIST function. The data channel signals are classified into three categories according to function, a data mask DM, data DQ, and a data strobe DQs. The DQS is square wave, DM and DQ data jump at DQS double edge, the speed is 2 times of DQS. The Linear Feedback Shift Register (LFSR) structure is a popular generation method for pseudo-random test data due to low hardware overhead and compact structure. In the prior art, a Linear Feedback Shift Register (LFSR) is generally used for generating DM and DQ test vectors, but the method has certain defects that the LFSR is directly used for generating the DM and DQ test vectors and high-speed clock pulses with the same frequency are required for driving, so that the BIST clock frequency is high, and the power consumption is large.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the method for generating the test vectors of the DDR2/3 PHY BIST data channel is simple in structure and easy to implement, and reduces the BIST operation frequency and power consumption under the condition of meeting the test requirement.
The technical solution of the invention is as follows:
a DDR2/3 PHY BIST data channel test vector generation method comprises the following steps:
(1) selecting an LFSR structure, and driving the LFSR structure to generate a pseudo-random number by using a low-frequency clock;
(2) interleaving and selecting a shift register value in an LFSR structure as test data;
(3) and combining the test data to construct a final test vector.
In the step (1), the number of shift registers in the LFSR structure is n +1, where n is determined by the bit width of the data channel and the clock relationship between the PHY and the DDR.
n is determined as follows:
wherein M is DQS frequency, and DQ frequency changed at DQS double edges is 2 × M; b is the data channel DQ bit width; the ratio of PHY to DDR grain clock frequencies is 1: and R, the LFSR structure clock frequency is M/R.
And R is 1 or 2.
In the step (2), values of n shift registers are selected from n +1 shift registers of the LFSR structure, and the values of the n shift registers are subjected to interleaving selection, so as to obtain test data allocated to each bit DQ, specifically, the following method is used:
the values of the n shift registers are randomly divided into 2 × R equal parts, each part has B bits of data, 2 × R parts of data are allocated to the DQs, and 2 × R test data are allocated to each bit of DQ.
In the step (3), the method for constructing the final DQ test vector is as follows:
and dividing the LSFR clock period into 2 multiplied by R intervals by using DLL in PHY, setting a multi-path data selector for each bit DQ, selecting one data from each interval by the multi-path data selector to be output to a corresponding bit of DQ, sequentially outputting the 2 multiplied by R data to the corresponding bit of DQ in the 2 multiplied by R intervals to obtain a test vector of each bit DQ, and outputting the distributed test vector by each bit DQ in one LSFR clock period.
And selecting 2 × R × W shift registers from the selected n shift registers, wherein W is DM bit wide, and each bit DM is allocated with 2 × R test data.
In the step (3), the method for constructing the final DM test vector is as follows:
and dividing the LSFR clock period into 2 multiplied by R intervals by using DLL in PHY, setting a multipath data selector for each DM, selecting one data in each interval by the multipath data selector and outputting the data to the corresponding DM bit, sequentially outputting the 2 multiplied by R data to the corresponding DM bit in the 2 multiplied by R intervals to obtain the test vector of each DM bit, and outputting the distributed test vector by each DM bit in one LSFR clock period.
In the step (3), a clock signal 2 times clk is used as the final test vector of DQS and DQSn, where clk is the clock driving the LFSR structure.
Compared with the prior art, the invention has the beneficial effects that:
the invention utilizes the low-frequency clock to drive the LFSR structure to generate the pseudo-random test data, and realizes the high-frequency pseudo-random test vector by skillfully interweaving and combining the existing data. The invention has simple structure and easy realization, reduces the BIST operation frequency and reduces the power consumption under the condition of meeting the test requirement.
Drawings
FIG. 1 is a flow chart of test vector construction according to the present invention;
FIG. 2 is a diagram of a test vector hardware generation module;
FIG. 3 is a test vector simulation waveform diagram for a code implementation.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings and specific embodiments:
as shown in fig. 1, the method of the present invention comprises the steps of:
(1) and selecting an LFSR structure, and driving the LFSR structure to generate pseudo random numbers by using a low-frequency clock, wherein the number of shift registers in the LFSR structure is n +1, and n is determined by the bit width of a data channel and the clock relationship between the PHY and the DDR.
A typical LFSR is feedback connected by n shift registers, several exclusive or gates. The number n of shift registers is determined by the data channel bit width and the clock relationship between the PHY and the DDR. The feedback coefficient of each register is determined by its primitive polynomial to generate a maximum length sequence. The operating state of an LFSR is close to an exhaustive test vector generator, since it can be any 2 except in the case of a register with all 0 statesn-cycling between 1 different states. In addition, the invention adds the n +1 th register, which can make the rest registers have all 0 states and complement 2 statesnSeed state, can be from 2 during testingnAnd selecting part of the middle state as a test vector. The LFSR has a simple structure and low hardware overhead.
n is determined as follows:
wherein M is DQS frequency, and DQ frequency changed at DQS double edges is 2 × M; b is the data channel DQ bit width; the ratio of PHY to DDR grain clock frequencies is 1: and R, the LFSR structure clock frequency is M/R. And R is 1 or 2.
(2) The shift register values in the LFSR structure are interleaved as test data.
Selecting values of n shift registers from n +1 shift registers of an LFSR structure, and performing interleaving selection on the values of the n shift registers to obtain test data distributed to each bit DQ, wherein the specific method is as follows:
the values of the n shift registers are randomly divided into 2 × R equal parts, each part has B bits of data, 2 × R parts of data are allocated to the DQs, and 2 × R test data are allocated to each bit of DQ.
(3) And combining the test data to construct a final test vector.
And dividing the LSFR clock period into 2 multiplied by R intervals by using DLL in PHY, setting a multiplexer for each bit DQ, selecting one data by the multiplexer in each interval and outputting the data to a bit corresponding to DQ, sequentially outputting the 2 multiplied by R data to the bit corresponding to DQ in the 2 multiplied by R intervals to obtain a test vector of each bit DQ, and outputting the distributed test vector of each bit DQ in one LSFR clock period.
Example (b):
DDR2/3 PHY data channel hardware implementations group in units of one byte (8 bits) of DQ: the 8-bit DQ signal, the 1-bit data mask DM, the differential data strobe DQs, and DQSn, together 11-bit signals, form a group of cells. If the data DQ is 64bits wide, 8 sets of the above units are required. Because each group of units are independent in logic function and hardware implementation, the test vectors keep signals in the group uncorrelated, and the groups can be multiplexed with each other. So we only need to implement one of the units.
And the ratio of PHY to DDR particle clock frequency is 1: 2 is for example DQ [7:0]Then 32-bit linear feedback shift registers are needed to be combined in an interleaving manner, in order to cover all the cases (including all 0) of the registers as much as possible, 33-bit linear feedback shift registers are selected to generate random numbers, and the feedback-connected exclusive-or gates are of an external connection type, as shown in fig. 2. In the embodiment, the LFSR is formed by externally connecting exclusive-OR gates to the 1 st shift register by using the 1 st, 15 th, 17 th and 33 th shift registers and feeding back the signals to the 1 st shift register, and the reset state is the 33 rd position 1 and the other 32 th position 0. 32 shift registers can be generated with a length of 232According to the requirement of test coverage rate, selecting partial sequence as test data.
Through step 2, each bit of DQ signal is randomly assigned to 4 shift register values. The operation of equally dividing the LSFR clock cycle into 4 intervals may be accomplished by a DDR2/3 PHY internal clock module that generates clock signals clk and clk _90, where clk is the clock driving the LFSR, connected to the shift register; clk _90 is a clock with a 90 ° phase lag of clk, and is coupled with clk to the 1-out-of-4 data selector. Taking DQ [0] as an example, clk and clk _90 are connected to the control terminal of the 1-out-of-4 data selector, the 4 allocated shift register values are connected to the 4 data terminals, the output terminal is DQ [0] test vector, the DQ signals of other bits are similar to DQ [0], and the waveform of the test vector part finally formed is as shown in FIG. 3.
The test vector construction method of the data mask DM is the same as DQ. DQS and DQSn test vectors may use a clock frequency 2 times clk.
The invention utilizes an interleaving combination method to reduce the LFSR driving clock frequency, and the generated pseudo-random data is used as a test vector of a DDR PHY BIST data channel. The invention has simple structure and easy realization, reduces the BIST operation frequency and reduces the power consumption under the condition of meeting the test requirement.
The above description is only an exemplary embodiment of the present invention, but the scope of the present invention is not limited thereto.
Claims (7)
1. A DDR2/3 PHY BIST data channel test vector generation method is characterized by comprising the following steps:
(1) selecting an LFSR structure, and driving the LFSR structure to generate a pseudo-random number by using a low-frequency clock;
(2) interleaving and selecting a shift register value in an LFSR structure as test data;
selecting values of n shift registers from n +1 shift registers of an LFSR structure, and performing interleaving selection on the values of the n shift registers to obtain test data distributed to each bit DQ, wherein the specific method is as follows:
dividing the values of the n shift registers into 2 xR equal parts at random, wherein each part has B bit test data, 2 xR parts of test data are distributed to DQ, and each bit DQ is distributed with 2 xR test data;
n is determined as follows:
wherein M is DQS frequency, and DQ frequency changed at DQS double edges is 2 × M; b is the data channel DQ bit width; the ratio of PHY to DDR grain clock frequencies is 1: r, the LFSR structure clock frequency is M/R;
(3) and combining the test data to construct a final test vector.
2. The method of claim 1, wherein the DDR2/3 PHY BIST data lane test vector generation method comprises: in the step (1), the number of shift registers in the LFSR structure is n +1, where n is determined by the bit width of the data channel and the clock relationship between the PHY and the DDR.
3. The method of claim 1, wherein the DDR2/3 PHY BIST data lane test vector generation method comprises: and R is 1 or 2.
4. The method of claim 1, wherein the DDR2/3 PHY BIST data lane test vector generation method comprises: in the step (3), the method for constructing the final DQ test vector is as follows:
and dividing the LSFR clock period into 2 multiplied by R intervals by using DLL in PHY, setting a multi-path data selector for each bit DQ, selecting a test data by the multi-path data selector in each interval and outputting the test data to a bit corresponding to DQ, sequentially outputting the 2 multiplied by R test data to a bit corresponding to DQ in the 2 multiplied by R intervals to obtain a test vector of each bit DQ, and outputting the distributed test vector by each bit DQ in one LSFR clock period.
5. The method of claim 1, wherein the DDR2/3 PHY BIST data lane test vector generation method comprises: and selecting 2 multiplied by R multiplied by W shift registers from the selected n shift registers, wherein W is the DM bit width, each bit DM is allocated with 2 multiplied by R test data, and DM is a data mask.
6. The method of claim 5, wherein the DDR2/3 PHY BIST data lane test vector generation method comprises: in the step (3), the method for constructing the final DM test vector is as follows:
and dividing the LSFR clock period into 2 multiplied by R intervals by utilizing a DLL in the PHY, setting a multipath data selector for each bit of DM, selecting one test data in each interval by the multipath data selector to be output to a corresponding bit of DM, sequentially outputting the 2 multiplied by R test data to the corresponding bit of DM in the 2 multiplied by R intervals to obtain a test vector of each bit of DM, and outputting the distributed test vector by each bit of DM in one LSFR clock period.
7. The method of claim 1, wherein the DDR2/3 PHY BIST data lane test vector generation method comprises: in the step (3), a clock signal 2 times clk is used as the final test vector of DQS and DQSn, where clk is the clock driving the LFSR structure, and DQS and DQSn refer to differential data strobe pulses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911252691.3A CN111044886B (en) | 2019-12-09 | 2019-12-09 | DDR2/3 PHY BIST data channel test vector generation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911252691.3A CN111044886B (en) | 2019-12-09 | 2019-12-09 | DDR2/3 PHY BIST data channel test vector generation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111044886A CN111044886A (en) | 2020-04-21 |
| CN111044886B true CN111044886B (en) | 2022-05-13 |
Family
ID=70235268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911252691.3A Active CN111044886B (en) | 2019-12-09 | 2019-12-09 | DDR2/3 PHY BIST data channel test vector generation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111044886B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112422360A (en) * | 2020-10-14 | 2021-02-26 | 锐捷网络股份有限公司 | Message sampling method, device, equipment and medium |
| CN113030709B (en) * | 2021-04-06 | 2022-06-24 | 中国科学院上海微系统与信息技术研究所 | Superconducting high-frequency test system and method |
| CN113466675B (en) * | 2021-05-26 | 2022-06-21 | 中国电子科技集团公司第五十四研究所 | Test vector generation method |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0366757A1 (en) * | 1988-04-01 | 1990-05-09 | Digital Equipment Corp | Memory selftest method and apparatus. |
| CN1688021A (en) * | 2005-05-25 | 2005-10-26 | 威盛电子股份有限公司 | Chip capable of self-measuring and measuring method thereof |
| CN101087129A (en) * | 2007-07-10 | 2007-12-12 | 中国人民解放军国防科学技术大学 | Full-speed pseudo random sequence generator using half speed clock |
| CN101776730A (en) * | 2010-01-29 | 2010-07-14 | 西安交通大学 | Test graphic generator of integrated circuit and test method thereof |
| CN101933098A (en) * | 2007-09-18 | 2010-12-29 | 明导公司 | Fault diagnosis in a memory bist environment using a linear feedback shift register |
| CN201876522U (en) * | 2009-12-31 | 2011-06-22 | 杭州士兰微电子股份有限公司 | General test equipment |
| CN106024066A (en) * | 2016-05-06 | 2016-10-12 | 北京润科通用技术有限公司 | SRAM detection method and system |
| CN108234039A (en) * | 2017-12-05 | 2018-06-29 | 北京时代民芯科技有限公司 | A kind of direct expansion answering machine baseband processor on piece function self-sensing method and system |
| CN110136762A (en) * | 2018-02-09 | 2019-08-16 | 爱思开海力士有限公司 | Clock distribution circuit and semiconductor devices including it |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7083108B2 (en) * | 1998-07-10 | 2006-08-01 | Silverbrook Research Pty Ltd | Redundantly encoded data structure for encoding a surface |
-
2019
- 2019-12-09 CN CN201911252691.3A patent/CN111044886B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0366757A1 (en) * | 1988-04-01 | 1990-05-09 | Digital Equipment Corp | Memory selftest method and apparatus. |
| CN1688021A (en) * | 2005-05-25 | 2005-10-26 | 威盛电子股份有限公司 | Chip capable of self-measuring and measuring method thereof |
| CN101087129A (en) * | 2007-07-10 | 2007-12-12 | 中国人民解放军国防科学技术大学 | Full-speed pseudo random sequence generator using half speed clock |
| CN101933098A (en) * | 2007-09-18 | 2010-12-29 | 明导公司 | Fault diagnosis in a memory bist environment using a linear feedback shift register |
| CN201876522U (en) * | 2009-12-31 | 2011-06-22 | 杭州士兰微电子股份有限公司 | General test equipment |
| CN101776730A (en) * | 2010-01-29 | 2010-07-14 | 西安交通大学 | Test graphic generator of integrated circuit and test method thereof |
| CN106024066A (en) * | 2016-05-06 | 2016-10-12 | 北京润科通用技术有限公司 | SRAM detection method and system |
| CN108234039A (en) * | 2017-12-05 | 2018-06-29 | 北京时代民芯科技有限公司 | A kind of direct expansion answering machine baseband processor on piece function self-sensing method and system |
| CN110136762A (en) * | 2018-02-09 | 2019-08-16 | 爱思开海力士有限公司 | Clock distribution circuit and semiconductor devices including it |
Non-Patent Citations (2)
| Title |
|---|
| A high speed BIST architecture for DDR-SDRAM testing;SC Shen 等;《2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT’05)》;20051231;1-6 * |
| 一种新的低功耗内建自测法-线性反馈移位寄存器结构的更改;李 锐 等;《电子器件》;20020930;第25卷(第3期);245-249 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111044886A (en) | 2020-04-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111044886B (en) | DDR2/3 PHY BIST data channel test vector generation method | |
| US5369648A (en) | Built-in self-test circuit | |
| US5258986A (en) | Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories | |
| US6301190B1 (en) | Semiconductor memory device with a rapid packet data input, capable of operation check with low speed tester | |
| US4959832A (en) | Parallel pseudorandom pattern generator with varying phase shift | |
| US4974184A (en) | Maximum length pseudo-random test pattern generator via feedback network modification | |
| US7444559B2 (en) | Generation of memory test patterns for DLL calibration | |
| JPH03214809A (en) | Linear feedback shift register | |
| US20050207574A1 (en) | System and method for generating pseudorandom numbers | |
| US6553530B1 (en) | Integrated circuit devices that include self-test apparatus for testing a plurality of functional blocks and methods of testing same | |
| WO2003046925A2 (en) | Built-in self-testing for double data rate input/output interface | |
| US7308634B2 (en) | Systems and methods for LBIST testing using multiple functional subphases | |
| CN101614789B (en) | Test pattern generator of integrated circuit and test method thereof | |
| US6789220B1 (en) | Method and apparatus for vector processing | |
| CN101776730B (en) | Test graphic generator of integrated circuit and test method thereof | |
| US9043662B2 (en) | Double data rate memory physical interface high speed testing using self checking loopback | |
| CN101509954A (en) | Test graph builder of integrated circuit | |
| US20070168809A1 (en) | Systems and methods for LBIST testing using commonly controlled LBIST satellites | |
| EP0318140A2 (en) | Pseudo-random generator and check sum circuitry for VLSI chip | |
| US7406639B2 (en) | Scan chain partition for reducing power in shift mode | |
| US6269462B1 (en) | Selectable sense amplifier delay circuit and method | |
| US20040059976A1 (en) | Semiconductor integrated circuit device having a test circuit of a random access memory | |
| US20030233607A1 (en) | Random pattern weight control by pseudo random bit pattern generator initialization | |
| Bhandari et al. | A low power test pattern generator for minimizing switching activities and power consumption | |
| CN111044887B (en) | Method for generating test vectors of DDR2/3PHY BIST command channel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |