CN101614789B - Test pattern generator of integrated circuit and test method thereof - Google Patents

Abstract

The invention relates to the test field of integrated circuits and discloses a low power consumption test pattern generator of an integrated circuit and a test method thereof. The low power consumption test pattern generator of the integrated circuit is based on a restructurable Johnson counter; compared with a traditional test pattern generator, the low power consumption test pattern generator can ensure that a generated test sequence can simultaneously reduce the test pattern conversion times in a space domain and a time domain, has low test pattern generation frequency in the space domain and generates different single-input changed sequences to each scan chain in the time domain, thereby greatly lowering the power consumption of a combined logic circuit part of a tested integrated circuit and the scan power consumption of the scan chain.

Description

A kind of test graph builder of integrated circuit and method of testing thereof

Technical field

The present invention relates to the integrated circuit testing field, particularly a kind of low-power consumption test graph builder of integrated circuit (Reconfigurable Johnson-Linear Feedback Shift Register TPG is called for short RJ-LFSR type TPG) and method of testing thereof.The low-power consumption test graph builder of this integrated circuit is based on restructural Johnson counter (Reconfigurable Johnson Counter).

Background technology

The built-in self-test of integrated circuit (Built-in-Self Test; Abbreviation BIST) test graph builder (the Test Pattern Generator in the structure; Be called for short TPG) generally adopt linear feedback shift register (Linear Feedback Shift Register is called for short LFSR) to realize.The method of testing that present BIST structure and Scan Design combine can reduce testing complex degree and testing expense.Yet this method of testing can cause the saltus step of circuit-under-test internal node to increase, thereby increases testing power consumption.The increase of average power consumption or peak power can cause the decline of circuit yields and circuit lifetime, also can in circuit, form focus (hot-spot) simultaneously, and increases the difficulty of circuit performance checking.In order to reduce power consumption, people have carried out extensive studies and have proposed a series of solution.These schemes mainly can be divided into and reduce amount of test data and reduce circuit-under-test test pattern power consumption down, and the latter comprises through technology such as improvement TPG and test sequence design thereof, one-level gate, Static Compression and realizing.

Single-hop becomes (Single Input Change is called for short SIC) sequence is having good application prospects aspect the reduction testing power consumption.The SIC sequence can will be imported saltus step and be reduced to minimum, and then reduces internal circuit saltus step activity, and the shortcoming of existing method is that the SIC sequence generator can cause the increase of hardware spending and time-delay.

Summary of the invention

One object of the present invention is to provide a kind of low-power consumption test graph builder of integrated circuit, based on the linear feedback shift register of restructural Johnson counter, can under the situation that does not increase hardware spending, reduce the testing power consumption of integrated circuit simultaneously.

Another object of the present invention is to provide the method for testing of the low-power consumption test graph builder of said integrated circuit.

Technical scheme 1: a kind of low-power consumption test graph builder of integrated circuit comprises linear feedback shift register, linear phase shifter, Johnson counter, XOR gate network; The clock frequency of said linear feedback shift register is f ₁, formation sequence Q=[Q ₁Q ₂... Q _m], wherein m is a natural number; Output sequence S=[the S of said linear phase shifter ₁S ₂... S _mS _M+1... S _N], it is that the sequence extension that linear feedback shift register generates is formed for the N position, wherein N is a natural number, and the clock frequency of the said Johnson counter of N＞m is f ₂, its formation sequence J=[J ₁J ₂... J _l], wherein l is a natural number; N＞l; Said XOR gate network output cycle tests X=[X ₁X ₂... X _mX _M+1... X _N], [X wherein ₁X ₂... X _lX _L+1... X _N] be the cycle tests of the combinational logic circuit part of tested integrated circuit, [X ₁X ₂... X _l] be the scan chain list entries of tested integrated circuit; Said linear feedback shift register, linear phase shifter, Johnson counter and XOR gate network satisfy following logical relation:

(a) S=VQ wherein V be the transformation matrix of confirming according to the primitive polynomial of linear feedback shift register;

$\left(b\right),[X_1{\mathrm{<figure-callout\; id="2"\; label="X"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">X</figure-callout>}}_2...X_l]=[J_1{\mathrm{<figure-callout\; id="2"\; label="J"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">J</figure-callout>}}_2...J_l]\&CirclePlus;[S_1{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">S</figure-callout>}}_2...S_l]$

[X _l+1X _l+2...X _N]＝[S _l+1S _l+2...S _N]；

It is characterized in that,

Said Johnson counter is a restructural Johnson counter; Said restructural Johnson counter comprises l d type flip flop of head and the tail serial connection successively; One two input MUX, one two input AND, and TPG_MOD enables control end and Init enables control end; The input end of first d type flip flop of output terminal connection of MUX, its input end connect l d type flip flop respectively The output terminal of output terminal and AND; The Q output terminal of l d type flip flop and Init enable two input ends that control end is connected respectively to AND; TPG_MOD enables the selection output of control end control MUX; The Q output of l d type flip flop constitutes the formation sequence J=[J of restructural Johnson counter ₁J ₂... J _l].

Technical scheme 2: a kind of method of testing of low-power consumption test graph builder of integrated circuit, it is characterized in that, may further comprise the steps:

(1) TPG_MOD is enabled control end and be changed to high level, Init enables control end when being changed to low level, the output terminal of MUX gating AND, and the output of restructural Johnson counter is set to all-zero state, i.e. J=[00...0];

(2) clock frequency of linear feedback shift register operation is f ₁The CLK1 clock period, formation sequence Q=[Q ₁Q ₂... Q _m], and then linear phase shifter output sequence S=[S ₁S ₂... S _mS _M+1... S _N], wherein m is a natural number;

(3) TPG_MOD enables control end and is set to low level, and clock frequency of restructural Johnson counter operation is f ₂The CLK2 clock period, generate a Johnson sequence J=[J ₁J ₂... J _l];

(4) TPG_MOD enables control end and is set to high level, and Init enables control end and is set to high level, restructural Johnson counter looping shift register mode, and the corresponding CLK2 clock period is moved the 2l cycle successively, produces 2l Johnson sequence J=[J ₁J ₂... J _l], corresponding 2l Johnson sequence J=[J ₁J ₂... J _l], the XOR gate network is correspondingly exported 2l cycle tests X=[X ₁X ₂... X _lX _L+1... X _N];

(5) repeating step 3 and step 4 meet the demands until fault coverage or testing length.

The low-power consumption test graph builder of integrated circuit of the present invention is compared with traditional test graph builder; The cycle tests that is generated can reduce the resolution chart conversion times simultaneously in spatial domain and time domain; Low at spatial domain resolution chart generated frequency; In time domain every scan chain is generated single input change sequence inequality, thereby reduce combinational logic circuit part (the average and peak value) power consumption and the scanning power consumption (average and peak value) of tested integrated circuit greatly.Simultaneously, the bit wide m of the bit wide l of restructural Johnson counter of the present invention or kind electronic circuit is much smaller than the original input end number N of tested integrated circuit, so hardware spending is little, and testing length is short, and fault coverage is high.With traditional pseudorandom resolution chart device relatively, amount of test data is few, the testing hardware expense is suitable, but testing power consumption reduces greatly, can improve test mass and product yields effectively.

Description of drawings

Fig. 1 is the structural representation of RJ-LFSR;

Fig. 2 is a restructural Johnson counter structure synoptic diagram among the RJ-LFSR;

Sequential chart when Fig. 3 tests for using RJ-LFSR;

Fig. 4 is the RJ-LFSR logical organization synoptic diagram that is applied to the integrated circuit of 4 original inputs;

Fig. 5 plants subsequence ' 0000 ' generates the SIC sequence on time orientation contrast synoptic diagram in the logical organization shown in Figure 4; Among the figure: 1 is the seed sequencer; 101 is linear feedback shift register; 102 is linear phase shifter; 2 is restructural Johnson counter; 3 is the XOR gate network.

Embodiment

With reference to Fig. 1; RJ-LFSR mainly comprises: reconfigurable Johnson counter (ReconfigurableJohnson Counter) 2; Linear feedback shift register (LFSR) 101, linear phase shifter (Linear PhaseShifter) 102 and XOR gate network (XOR-Network) 3.

Seed sequencer (Seed Generator) 1 is made up of linear feedback shift register 101 and linear phase shifter 102 jointly, is used for producing kind of a subsequence.Wherein, the clock of linear feedback shift register 101 (CLK1) frequency f ₁, formation sequence Q=[Q ₁Q ₂... Q _m], m is a natural number; In the present invention, allow LFSR to be output as complete 0 state.Linear phase shifter 102 is with sequence Q=[Q ₁Q ₂... Q _m] logical extension is the output sequence S=[S of N position ₁S ₂... S _mS _M+1... S _N], promptly plant subsequence, and satisfy N＞m.

Satisfy following logical relation for linear phase shifter with N position bit wide and linear feedback shift register:

S＝VQ (1)

Wherein transformation matrix V confirms according to the corresponding primitive polynomial of LFSR.With cycle tests bit wide N=20 is example, and corresponding primitive polynomial is 1+x+x ¹⁵LFSR, its sequence Q and sequence S satisfy:

S ₁＝Q ₁

${\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">S</figure-callout>}}_2={\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="H2009100233960E00011.png,H2009100233960E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3\&CirclePlus;Q_6\&CirclePlus;Q_{10}\&CirclePlus;Q_{13}$

${\mathrm{<figure-callout\; id="3"\; label="S"\; filenames="H2009100233960E00011.png,H2009100233960E00021.png"\; state="\{\{state\}\}">S</figure-callout>}}_3={\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="H2009100233960E00013.png,H2009100233960E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1\&CirclePlus;{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2\&CirclePlus;Q_4\&CirclePlus;Q_5\&CirclePlus;Q_7\&CirclePlus;Q_9\&CirclePlus;Q_{11}\&CirclePlus;Q_{12}\&CirclePlus;Q_{14}$

$S_4=Q_8\&CirclePlus;Q_{15}$

S ₅＝Q ₂，S ₆＝Q ₃，S ₇＝Q ₄

S ₈＝0，S ₉＝Q ₅，S ₁₀＝Q ₆

S ₁₆＝0

S ₁₇＝Q ₁₂，S ₁₈＝Q ₁₃，S ₁₉＝Q ₁₄，S ₂₀＝Q ₁₅

Q wherein _i(i=1,2,3 ..., 15) expression LFSR i output.Can confirm corresponding transformation matrix V according to above-mentioned logical relation.

The clock of reconfigurable Johnson counter (CLK2) frequency f ₂, it generates Johnson sequence J=[J ₁J ₂... J _l], wherein l is a natural number; The output sequence of XOR gate network is the cycle tests X=[X of test graph builder output ₁X ₂... X _mX _M+1... X _N], [X wherein ₁X ₂... X _lX _L+1... X _N] be the cycle tests of the combinational logic circuit part of tested integrated circuit, [X ₁X ₂... X _l] be the scan chain list entries of tested integrated circuit.Wherein, linear phase shifter, restructural Johnson counter satisfy following logical relation with the XOR gate network:

$[X_1{\mathrm{<figure-callout\; id="2"\; label="X"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">X</figure-callout>}}_2...X_l]=[J_1{\mathrm{<figure-callout\; id="2"\; label="J"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">J</figure-callout>}}_2...J_l]\&CirclePlus;[S_1{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">S</figure-callout>}}_2...S_l]$

[X _l+1X _l+2...X _N]＝[S _l+1S _l+2...S _N] (2)

According to above-mentioned logical relation, CC forms the test graph builder of integrated circuit.

Under the integrated circuit self-test pattern, linear feedback shift register is formation sequence Q=[Q under the driving of clock CLK1 ₁Q ₂... Q _m], linear phase shifter expands to the kind subsequence S=[S of N position with it ₁S ₂... S _mS _M+1... S _N].The reconfigurable Johnson counter in l position formation sequence J=[J under the driving of clock CLK2 ₁J ₂... J _l].The XOR network comprises l two input XOR gates, is used for the low level output S=[S to linear phase shifter ₁S ₂... S _l] and the output [J of restructural Johnson counter ₁J ₂... J _l] the step-by-step XOR, obtain cycle tests X=[X ₁X ₂... X _lX _L+1... X _N].

Cycle tests is added to the original input end and the scan chain input end of the combinational logic circuit part (Combinational Logic) of tested integrated circuit respectively according to different test patterns; Obtain the output response from the original output terminal of tested integrated circuit and the output terminal of scan chain then; To export response and be connected to many input feature vectors register (multiple-input signature register; Be called for short MISR), finally by the output of MISR decision circuitry operate as normal whether as a result.

Under the test-per-clock pattern, cycle tests X=[X ₁X ₂... X _lX _L+1... X _N] be added to the original input end of the combinational logic circuit part (Combinational Logic) of tested integrated circuit.The bit wide N that plants subsequence equals the original input number of tested integrated circuit, and the bit wide l of Johnson counter can be much smaller than N.Clock CLK1 moves one-period, in corresponding clock CLK2 2N cycle of operation, can generate the SCI sequence that length is 2N in the time at clock CLK1 one-period.Under the test-per-scan pattern, sequence [X ₁X ₂... X _l] be added to the input end of scan chain SC1-SCl (Scan Chain, be called for short SC) respectively.The bit wide N that plants subsequence equals the original input number of circuit-under-test, and the bit wide l of restructural Johnson counter equals the scan chain number.

With reference to Fig. 2, restructural Johnson counter comprises l d type flip flop of head and the tail serial connection successively, one two input MUX, and one two input AND, and TPG_MOD enables control end and Init enables control end; The output terminal of MUX connects the input end of first d type flip flop, and its input end connects respectively and connects l d type flip flop

The output terminal of output terminal and AND; The Q output terminal and the Init of l d type flip flop enables two input ends that control end is connected AND; TPG_MOD enables the selection output of control end control MUX; The Q output of l d type flip flop constitutes the formation sequence J=[J of restructural Johnson counter ₁J ₂... J _l].TPG_MOD enables the output terminal that control end is the high-level strobe AND, output terminal of l d type flip flop of low level gating.

In restructural Johnson counter structure, be provided with that TPG_MOD enables control end and Init enables control end, can carry out initialization to restructural Johnson counter, and the mode of operation of circuit is set in test process.When TPG_MOD is a high level, when Init was low level, circuit working was in initialize mode, and restructural Johnson counter will be set to all-zero state, i.e. J=[00...0]; When TPG_MOD was low level, restructural Johnson counter works was under normal mode, and circuit working pattern and Init are irrelevant, and the corresponding every operation one-period of clock CLK2 just produces a Johnson sequence; When TPG_MOD is a high level, when Init was high level, the function of restructural Johnson counter was a circular shift register, and the corresponding clock CLK2 operation l cycle just produces l cycle tests.

With reference to Fig. 3, method of testing of the present invention, the low-power consumption test graph builder based on said integrated circuit may further comprise the steps:

(1) TPG_MOD is enabled control end and be changed to high level, Init enables control end when being changed to low level, the output terminal of MUX gating and logical circuit, and the output of restructural Johnson counter is set to all-zero state, i.e. J=[00...0];

(2) clock frequency of linear feedback shift register operation is f ₁The CLK1 clock period, formation sequence Q=[Q ₁Q ₂... Q _m], and then linear phase shifter output sequence S=[S ₁S ₂... S _lS _L+1... S _N];

(3) TPG_MOD enables control end and is set to low level, and circuit working pattern and Init are irrelevant, and clock frequency of restructural Johnson counter operation is f ₂The CLK2 clock period, generate a Johnson sequence J=[J ₁J ₂... J _l];

(4) TPG_MOD enables control end and is set to high level, and Init enables control end and is set to high level, and restructural Johnson counter is a circular shift register, and the corresponding CLK2 clock period is moved the 2l cycle successively, produces 2l Johnson sequence J=[J ₁J ₂... J _l], corresponding 2l Johnson sequence J=[J ₁J ₂... J _l] output 2l cycle tests X=[X of XOR gate network ₁X ₂... X _lX _L+1... X _N];

(5) repeating step (3) and step (4), the output 2Nl of XOR gate network cycle tests X=[X ₁X ₂... X _lX _L+1... X _N], under the test-per-clock pattern, [X ₁X ₂... X _lX _L+1... X _N] be the cycle tests of the combinational logic circuit part of tested integrated circuit; Under the test-per-scan pattern, [X ₁X ₂... X _l] be the scan chain list entries of tested integrated circuit.Perhaps repeating step (3) and step (4) meet the demands until fault coverage or testing length.

With reference to Fig. 4, be applied to the RJ-LFSR type TPG logical organization synoptic diagram of 4 bit wide integrated circuit.Select for use 1 linear feedback shift register (LFSR) 101 can produce 21 no repeating sequences, expand to 4 kind subsequence by linear phase shifter 102.

$\left[\begin{array}{c}{S}_1\\ S_2\\ S_3\\ S_4\end{array}\right]\left[\begin{array}{cccc}1& 0& 0& 0\\ 0& 0& 0& 0\\ 1& 0& 0& 0\\ 0& 0& 0& 0\end{array}\right]\left[Q_1\right]---\left(3\right)$

According to the logical relation of sequence Q shown in (3) formula and sequence S, structure linear phase shifter 102, linear phase shifter 102 expands to 24 kind subsequence ' 0000 ' and ' 0101 ' with 21 no repeating sequences ' 0 ' with ' 1 '.Plant Johnson sequence step-by-step XOR in XOR gate network (XOR-Network) 3 of subsequence S and 2 outputs of restructural Johnson counter, thereby obtain cycle tests X.

Under the test-per-clock pattern, LFSR moves a CLK1 cycle, and restructural Johnson counter works is in normal mode, and correspondence is moved 6 CLK2 cycles, thereby produces a SIC sequence.Kind of subsequence ' 0000 ' corresponding SIC sequence be 0000,1000,1100,1110,0110,0010}, and the SIC sequence of planting subsequence ' 0101 ' correspondence be 0101,1101,1001,1011,0011,0111}.Two kind subsequence common properties are given birth to 12 cycle testss of no repetition.

Under the test-per-scan pattern, corresponding each Johnson sequence, restructural Johnson counter is worked with the mode of circular shift register, thereby on time orientation, produces the SIC sequence for scan chain SC1-SC3.In conjunction with Fig. 5, explain that RJ-LFSR type TPG is the SIC sequence that seed generates with sequence ' 0000 ' on time orientation.With scan chain SC3 is example, and corresponding SIC sequence is [000_001_011_111_110_100].These SIC sequences are added on the scan chain of tested integrated circuit continuously, and the average input transition density that causes is 1/3.

For single scan chain, the average input transition density of l level restructural Johnson counter can be approximately:

$\frac{2(l-1)}{{\mathrm{<figure-callout\; id="2"\; label="l"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">l</figure-callout>}}^2}\&ap;\frac{2}{l}----\left(4\right)$

And for the original input end of tested integrated circuit, on average import transition density and be generally 1/2l ²The average input transition density that draws the combinational logic circuit part thus is:

$\frac{1+2(l-1)l}{{2l}^2(l+N)}\&ap;\frac{1}{l+N}---\left(5\right)$

By (4), (5) two formulas can be reached a conclusion theoretically, and RJ-LFSR can reduce the transition density of the original input end and the scan chain input end of tested integrated circuit simultaneously.

In the present embodiment, linear feedback shift register (LFSR) designs according to primitive polynomial; Simultaneously, in order to insert complete 0 figure, introduce a rejection gate in the feedback circuit of linear feedback shift register (LFSR), input is the output signal of all triggers of linear feedback shift register (LFSR); The feedback signal of the first order trigger of being confirmed by primitive polynomial and the output signal XOR of this rejection gate can obtain inserting the feedback signal of the LFSR of complete 0 figure.Between the resolution chart that generates, duplicate, according to the primitive polynomial design linear phase shifter of concrete LFSR.

The inventor is applied to RJ-LFSR type TPG of the present invention in the experiment of standard testing collector ISCAS ' 85 and ISCAS ' 89.For ISCAS ' 89 test set circuit, using the full scan design and designing the scan chain number is 20, and corresponding LFSR primitive polynomial is 1+x+x ¹⁵, linear phase shifter is realized according to following mode:

S ₁＝Q ₁

${\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">S</figure-callout>}}_2={\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="H2009100233960E00011.png,H2009100233960E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3\&CirclePlus;Q_6\&CirclePlus;Q_{10}\&CirclePlus;Q_{13}$

${\mathrm{<figure-callout\; id="3"\; label="S"\; filenames="H2009100233960E00011.png,H2009100233960E00021.png"\; state="\{\{state\}\}">S</figure-callout>}}_3={\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="H2009100233960E00013.png,H2009100233960E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1\&CirclePlus;{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2\&CirclePlus;Q_4\&CirclePlus;Q_5\&CirclePlus;Q_7\&CirclePlus;Q_9\&CirclePlus;Q_{11}\&CirclePlus;Q_{12}\&CirclePlus;Q_{14}$

$S_4=Q_8\&CirclePlus;Q_{15}$

S ₅＝Q ₂，S ₆＝Q ₃，S ₇＝Q ₄

S ₈＝0，S ₉＝Q ₅，S ₁₀＝Q ₆

S ₁₆＝0

S ₁₇＝Q ₁₂，S ₁₈＝Q ₁₃，S ₁₉＝Q ₁₄，S ₂₀＝Q ₁₅

Q wherein _i(i=1,2,3 ..., 15) expression LFSR i output.

Experiment obtains the power consumption data of RJ-LFSR type TPG and the TPG (abbreviating LFSR type TPG as) that adopts common LFSR shown in table 1, table 2.

Each item power consumption comparison sheet of table 1RJ-LFSR type TPG and LFSR type TPG

The total power consumption comparison sheet of table 2RJ-LFSR type TPG and LFSR type TPG

In the table 1,2: A represents RJ-LFSR type TPG, and B represents LFSR type TPG, and ratio data is benchmark with LFSR type TPG all, wherein Δ P _AvgThe number percent that expression RJ-LFSR type TPG test average power consumption descends, Δ P _PeakThe number percent that expression RJ-LFSR type TPG test peak power descends.The average test figure moves into power consumption and representes that RJ-LFSR type TPG is moving into the power consumption that descends in the scan chain process with the resolution chart serial, and average power consumption reduces 42.4%-47.2% in the scan chain, and combinational logic circuit part average power consumption reduces 67.8%-75.1%.The displacement power consumption considered that resolution chart moves into test response and shifted out the influence to the saltus step of circuit-under-test internal node, and the RJ-LFSR type TPG power consumption that can will be shifted reduces 23.8%-39.0%, and peak power reduces scope than 24.4%-52.3% greatly.Total power consumption has considered that resolution chart immigration, test response shift out and the power consumption of combinational logic circuit, and RJ-LFSR type TPG can reduce 25.4%-41.6% with average power consumption, and peak power reduces 16.2%-39.7%.In general, RJ-LFSR type TPG can significantly reduce average power consumption and peak power in the Scan Design test.

It is as shown in table 3 to test the comparing data that obtains RJ-LFSR type TPG and LFSR type TPG fault coverage and hardware spending.

Table 3:RJ-LFSR type TPG and LFSR type TPG fault coverage and hardware spending comparing data table

In the table 3: A represents RJ-LFSR type TPG, and B represents LFSR type TPG, and ratio data is a benchmark with LFSR type TPG all; Wherein SFC representes stuck-at fault coverage rate, N _pThe sequence length that expression RJ-LFSR type TPG generates.For the circuit among the standard testing collector ISCAS ' 85, RJ-LFSR type TPG can reach and be higher than the persistent fault coverage rate of LFSR type TPG.For the circuit among the standard testing collector ISCAS ' 89, RJ-LFSR type TPG can reach identical persistent fault coverage rate even less than the required resolution chart number of LFSR type TPG with approaching.Can draw RJ-LFSR type TPG thus can ignore the influence of testing length.

In the experiment among the LFSR type TPG d type flip flop comprise Q and

two output ports; And the d type flip flop in the restructural Johnson counter is reduced to a Q output port only arranged, and can reduce the hardware spending of RJ-LFSR type TPG like this.RJ-LFSR type TPG hardware spending is recently represented with its percentage with respect to standard testing collector area.For the circuit among the standard testing collector ISCAS ' 85, hardware spending changes greatly: RJ-LFSR type TPG hardware spending changes in the scope of 7.2%-98.0%, and the hardware spending of LFSR type TPG is between 13.6%-183.6%.For the circuit among the standard testing collector ISCAS ' 89, hardware spending changes less: RJ-LFSR type TPG hardware spending changes in the scope of 1.1%-6.8%, and the hardware spending of LFSR type TPG is between 0.7%-15.0%.

Experimental result shows that the cycle tests that RJ-LFSR type TPG is produced can effectively reduce resolution chart and move into power consumption and combinational logic power consumption, and it is to the basic not influence of testing length and hardware spending.

Claims (2)

1. the low-power consumption test graph builder of an integrated circuit comprises linear feedback shift register, linear phase shifter, Johnson counter, XOR gate network; The clock frequency of said linear feedback shift register is f ₁, formation sequence Q=[Q ₁Q ₂... Q _m], wherein m is a natural number; Output sequence S=[the S of said linear phase shifter ₁S ₂... S _mS _M+1... S _N], it is that the sequence extension that linear feedback shift register generates is formed for the N position, and wherein N is a natural number, and N＞m, and the clock frequency of said Johnson counter is f ₂, its formation sequence J=[J ₁J ₂... J _l], wherein l is a natural number; N＞l; Said XOR gate network output cycle tests X=[X ₁X ₂... X _mX _M+1... X _N], [X wherein ₁X ₂... X _lX _L+1... X _N] be the cycle tests of the combinational logic circuit part of tested integrated circuit, [X ₁X ₂... X _l] be the scan chain list entries of tested integrated circuit; Said linear feedback shift register, linear phase shifter, Johnson counter and XOR gate network satisfy following logical relation:

(a) S=VQ wherein V be the transformation matrix of confirming according to the primitive polynomial of linear feedback shift register;

$\left(b\right),[X_1{X}_2...X_l]=[J_1{J}_2...J_l]\&CirclePlus;[S_1{S}_2...S_l]$

[X _l+1X _l+2...X _N]＝[X _l+1S _l+2...S _N]；

It is characterized in that,

Said Johnson counter is a restructural Johnson counter; Said restructural Johnson counter comprises l d type flip flop of head and the tail serial connection successively; One two input MUX, one two input AND, and TPG_MOD enables control end and Init enables control end; The input end of first d type flip flop of output terminal connection of MUX, its input end connect l d type flip flop respectively

The output terminal of output terminal and AND; The Q output terminal of l d type flip flop and Init enable two input ends that control end is connected respectively to AND; TPG_MOD enables the selection output of control end control MUX; The Q output of l d type flip flop constitutes the formation sequence J=[J of restructural Johnson counter ₁J ₂... J _l].

2. the method for testing of the low-power consumption test graph builder of a kind of integrated circuit according to claim 1 is characterized in that, may further comprise the steps:

(1) TPG_MOD is enabled control end and be changed to high level, Init enables control end when being changed to low level, the output terminal of MUX gating AND, and the output of restructural Johnson counter is set to all-zero state, i.e. J=[00...0];

(2) clock frequency of linear feedback shift register operation is f ₁The CLK1 clock period, formation sequence Q=[Q ₁Q ₂... Q _m], and then linear phase shifter output sequence S=[S ₁S ₂... S _mS _M+1... S _N], wherein m is a natural number;

(3) TPG_MOD enables control end and is set to low level, and clock frequency of restructural Johnson counter operation is f ₂The CLK2 clock period, generate a Johnson sequence J=[J ₁J ₂... J _l];

(4) TPG_MOD enables control end and is set to high level, and Init enables control end and is set to high level, restructural Johnson counter looping shift register mode, and the corresponding CLK2 clock period is moved the 2l cycle successively, produces 2l Johnson sequence J=[J ₁J ₂... J _l], corresponding 2l Johnson sequence J=[J ₁J ₂... J _l], the XOR gate network is correspondingly exported 2l cycle tests X=[X ₁X ₂... X _lX _L+1... X _N];

(5) repeating step 3 and step 4 meet the demands until fault coverage or testing length.

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