CN107991602B - Built-in self-testing structure with broadcasting structure - Google Patents

Built-in self-testing structure with broadcasting structure Download PDF

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CN107991602B
CN107991602B CN201711185074.7A CN201711185074A CN107991602B CN 107991602 B CN107991602 B CN 107991602B CN 201711185074 A CN201711185074 A CN 201711185074A CN 107991602 B CN107991602 B CN 107991602B
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CN107991602A (en
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梁峰
王烨
雷绍充
袁野
张国和
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Xian Jiaotong University
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    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31702—Testing digital circuits including elements other than semiconductor transistors, e.g. biochips, nanofabrics, mems, chips with magnetic elements
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    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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Abstract

The invention discloses a built-in self-test structure with a broadcasting structure, and aims to solve the problems of high chip test power consumption, large area overhead and test data volume and the like caused by small characteristic size of a semiconductor device and high integrated circuit integration level and complexity. Firstly, combining a linear feedback shift register structure with a Johnson counter through an exclusive-or network to generate a test vector with multidimensional single input hopping (MSIC) characteristics; then, through a multiplexing test generation structure, the broadcast circuit expands the test vectors into broadcast-based multi-dimensional single-input hopping (BMSIC) test patterns which can fill more scan chains, thereby reducing the area overhead of the test pattern generation circuit; finally, the experiment is carried out by taking five larger circuits in the ISCAS' 89 series as objects, and the result shows that compared with the MSIC test generation circuit, the BMSIC test pattern generation method can reduce the circuit area overhead by about 50 percent on the basis of ensuring low power consumption and high fault coverage rate.

Description

Built-in self-testing structure with broadcasting structure
Technical Field
The invention belongs to the technical field of chip testing, and particularly relates to a low-cost built-in self-testing structure with a broadcasting structure.
Background
As the core of the electronic information field, the integrated circuit attracts attention and develops rapidly since birth, and even becomes a key point for marking a national science and technology. In recent decades, the development of integrated circuits has followed moore's law, the feature size has been continuously reduced, the integration level has been continuously increased, and the complexity has become higher and higher. In terms of feature size, intel enters 45nm, 32nm and 22nm process nodes in 2007, 2009 and 2011 respectively, and intel, samsung and other companies have realized 14nm processes in 2014, and nowadays, many companies have made a major breakthrough in 10nm processes, and even IBM has published that it has made a major progress in 7nm processes; on the level of integration, Pentium 4 Willamate in 2000 has about 4200 thousands of transistors, and today the fifth generation core mobile processor has up to 19 hundred million transistors integrated; in terms of complexity, the System-on-a-Chip (SOC) has entered More molar times, and by integrating an ip (intelligent performance) core, the SOC has More powerful functions and More complex structures, and the modules related to audio, video, wireless and the like are increasingly perfect. The integrated circuit test is an important means for ensuring the correctness and reliability of finished chips, only chips which are subjected to complete test can be delivered to the market, although the integrated circuit industry is favored to develop, the integrated circuit test poses many challenges, and the traditional fault model and test method are difficult to deal with.
In very large scale digital integrated circuits implemented using nanotechnology, the number of gates and the types of defects are continuously increasing, which results in an increasing amount of test data, but the number of I/os of chips, the number of channels of Automatic Test Equipment (ATE), data storage capacity, and operating speed are limited, which results in an increasing test time and a very expensive or even unacceptable test cost. Another important problem is Test power consumption, and the average power consumption and peak power consumption of a tested Circuit (CUT) during testing are 2-4 times of those during normal operation [1], which can cause the temperature of a transistor to be increased, so that a device is burnt out during testing, thereby introducing faults caused by non-manufacture and design and reducing the yield of products; too high power consumption will also increase the cost of the package, which puts higher demands on the reliability and test quality of the device and its packaging, and from an energy perspective, high power consumption will inevitably result in a large loss of energy. Therefore, a test pattern generation method that can achieve both low power consumption and low cost is desired.
The built-in self-Test (BIST) method fundamentally solves the storage problem of the Test data volume of the automatic tester, reduces the Test cost, however, due to the increase of the circuit scale, the traditional BIST technology mostly bases on the pseudo random Test Pattern (Test Pattern) generated by a Linear Feedback Shift Register (LFSR) and causes great Test power consumption during the Test, and due to the increase of the circuit complexity, the probability of the occurrence of the pseudo random Fault resistance is increased, so that the generated Test Pattern is difficult to obtain a satisfactory Fault Coverage (Fault Coverage), while the introduction of the low power consumption technology and the Fault Coverage improvement technology causes the area overhead of the Test Pattern Generator (TPG) to be increased, thereby causing the whole BIST structure area to be too large, and even becoming a new bottleneck. Therefore, low power consumption, low cost testing has become a focus of research and application.
Disclosure of Invention
The invention provides a low-cost built-in self-test structure with a broadcasting structure, which aims to solve the problems of high chip test power consumption, large area overhead and test data volume and the like caused by small characteristic size of a semiconductor device and high integrated circuit integration level and complexity and reduce the area overhead on the basis of giving consideration to low power consumption and satisfactory fault coverage rate.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme:
a low-cost built-in self-test structure with a broadcast structure comprises a clock control module, an original scan chain generation module and a broadcast module; wherein the content of the first and second substances,
the clock control module is used for generating a clock for controlling the generation of the original anchor chain;
the original scan chain generation module is used for generating original scan chain data with low jump;
and the broadcasting module is used for finishing broadcasting of all original scan chain vectors and generating a final test pattern.
The invention has the further improvement that the original scan chain generation module comprises a linear feedback shift register, a reconstructed Johnson counter and an exclusive or network;
the linear feedback shift register is used for generating a seed vector S;
reconstructing a Johnson counter for generating a J vector;
and the exclusive-OR network is used for completing exclusive-OR of the S vector and the J vector to generate original scan chain data.
The invention has the further improvement that the clock control module comprises n-stage D triggers, wherein the D end of the next-stage D trigger is connected with the Q end of the first-stage D trigger, and the clock ends of all the D triggers are connected with a clock ck 1; the output of the last stage is taken as clk2 clock, a clock clk1 is connected with the clock end of the reconstructed Johnson counter, and a clock clk2 is connected with the clock end of the linear feedback shift register.
The linear feedback shift register is further improved in that the linear feedback shift register comprises m-level D triggers and an exclusive-OR gate, a first input end of the exclusive-OR gate is connected with a Q end of the m-level D trigger, a second input end of the exclusive-OR gate is connected with a Q end of the first-level D trigger, and an output of the exclusive-OR gate is connected with an input D end of the first-level D trigger; except that the input end of the first stage D trigger is connected with the output of the exclusive-OR gate, the D ends of the next stage D triggers of other D triggers are connected with the Q end of the previous stage D trigger, and the clock ends of all D triggers are connected with a clock ck 2; taking the Q end output of each stage of D flip-flop, and connecting the Q end output to the input of an exclusive OR gate of an exclusive OR network;
reconstructing a Johnson counter, wherein the Johnson counter comprises an L-level D trigger, an alternative multiplexer and a two-input AND gate; two inputs connected to gate, first input connected to Rst signal, second input connected to L-th D flip-flop
Figure BDA0001479954080000031
The output end of the first selector is connected with the first multiplexer; the control end of the one-out-of-two multi-path selector is connected with a Mode signal, the first input of the one-out-of-two multi-path selector is connected with the output ends of the two-input AND gate, the second output of the one-out-of-two multi-path selector is connected with the Q end of the last stage D trigger, and the output end of the one-out-of-two multi-path; the D ends of the other D triggers are all the D triggers of the next stage and are connected with the Q end of the D trigger of the previous stage, and the clock ends of all the D triggers are all connected with a clock ck 1; taking the Q end output of each stage of D flip-flop, and connecting the Q end output to the input of an exclusive OR gate of an exclusive OR network;
the exclusive-or network comprises m two-input exclusive-or gates, wherein one input of the first exclusive-or gate is the 1 st bit of the s-bit seed vector, the other input of the first exclusive-or gate is the 1 st bit of the L-bit J vector, and the like, one input of the exclusive-or gate is the s-bit seed vector, and the other input of the exclusive-or gate is the corresponding bit of the L-bit J vector; and respectively taking the outputs of the m-level exclusive-OR gates, and connecting the outputs to the exclusive-OR gate network input of the broadcasting module.
A further improvement of the invention is that the broadcast module comprises a broadcast controller and an exclusive or gate network; wherein the content of the first and second substances,
the broadcast controller is a two-bit linear feedback shift register composed of two stages of D triggers, is controlled by a clock clk2 and outputs a two-bit broadcast vector B, wherein the first bit is connected with a second exclusive-OR gate, a fourth exclusive-OR gate and a fifth exclusive-OR gate of the broadcast module, and the second bit is connected with the first exclusive-OR gate, the second exclusive-OR gate, the third exclusive-OR gate, the fifth exclusive-OR gate and a sixth exclusive-OR gate of the broadcast module;
the exclusive-OR gate network comprises 4 two-input exclusive-OR gates and 2 three-input exclusive-OR gates, wherein the first two-input exclusive-OR gate has one input connected with a first original scan chain and the other input connected with one bit of a two-bit control vector generated by a broadcast controller, and the output is a 1 st scan chain; the first three-input exclusive-OR gate has one input connected with the first original scan chain and the other two inputs respectively connected with the two-bit broadcast vector of the broadcast controller, and the output is the 2 nd scan chain; the 1 st scan chain is directly output as a 3 rd scan chain; a second two-input exclusive-or gate, one input of which is connected with the first original scanning link and the other input of which is connected with the 2 nd bit of the broadcast vector and the output of which is the 4 th scanning chain; a third two-input exclusive-or gate, one input of which is connected with the 2 nd original scanning line, the other input of which is connected with the 1 st bit of the broadcast vector, and the output of which is the 5 th scanning chain; the 2 nd original scan chain is directly output as a 6 th scan chain; one input of the second three-input exclusive-or gate is connected with the 2 nd original scan chain, the other two inputs of the second three-input exclusive-or gate are respectively connected with the two-bit broadcast vector of the broadcast controller, and the output of the second three-input exclusive-or gate is the 7 th scan chain; a fourth two-input exclusive-or gate, one input of which is connected with the 2 nd original scanning link and the other input of which is connected with the 2 nd bit of the broadcast vector and the output of which is the 8 th scanning chain; and in the same way, the third scanning chain and the 4 th scanning chain, the 5 th scanning chain and the 6 th scanning chain, and the 7 th scanning chain and the 8 th scanning chain are connected to the XOR gate network of the broadcasting module to multiplex the broadcasting module.
Compared with the prior art, the invention has the following advantages:
the invention combines a linear feedback shift register structure and a reconstructed Johnson counter through an exclusive-or network to generate a test vector with multidimensional single input hopping (MSIC) characteristics, particularly, a broadcaster is introduced, and a broadcast circuit expands the test vector into a broadcast-based multidimensional single input hopping (BMSIC) test pattern capable of filling more scan chains through a multiplexing test generation structure, thereby reducing the area overhead of a test pattern generation circuit.
The introduction of the broadcasting circuit provided by the invention reduces the area overhead of a Test Pattern generating circuit, realizes low power consumption compared with a pseudo-random sequence based on a linear feedback shift register, realizes higher fault coverage compared with a low-jump sequence based on a reconstructed Johnson counter, and reduces the area overhead of the Test Pattern generating circuit compared with a Test Pattern generating method for increasing the area overhead of a Test Pattern Generator (TPG) by introducing some low-power consumption technologies and technologies for improving the fault coverage.
Drawings
FIG. 1 is a schematic representation of a test pattern generation circuit;
FIG. 2 is a diagram of a reconstructed Johnson counter;
FIG. 3 is a schematic representation of an XOR network;
fig. 4 is a circuit diagram of a broadcast module.
Detailed Description
The invention is further described below with reference to the following figures and examples.
The invention provides a low-cost built-in self-test structure with a broadcast structure, which comprises a clock control module, an original scan chain generation module and a broadcast module, wherein a region 1 is the clock control module and generates a clock for controlling the generation of an original scan chain, as shown in figure 1; 2. 3, the regions 4 jointly form an original scan chain generation module to generate original scan chain data with low jump; and 5, the area is a broadcasting module, broadcasting of all original scan chain vectors is completed, and a final test pattern is generated.
And the clock control module generates clocks clk1 and clk2, clk1 drives the reconstructed Johnson counter to complete J vector updating, clk2 drives the linear feedback shift register to complete seed vector updating, and scan-in is realized.
And the original scan chain generation module consists of a Linear Feedback Shift Register (LFSR), a reconstructed Johnson counter and an exclusive or network. And the LFSR generates an S vector, the Johnson counter is reconstructed to generate a J vector, and the XOR network completes the XOR of the S vector and the J vector to generate original scan chain data.
The M-bit LFSR structure connected based on the primitive polynomial feedback mode can generate a pseudo-random sequence with a long period and randomness close to a random sequence, and the BMSIC test graph in the text adopts an M sequence as a seed vector S; the Johnson counter reconstructed according to the graph generation algorithm solves the problem that the data shifting and loading process cannot be completed by a simple Johnson counter, and does not change the low power consumption characteristic of the Johnson counter; the structure combines an LFSR structure capable of generating a pseudo-random sequence and a Johnson counter capable of generating a low-jump sequence to generate a test vector with the characteristic of multidimensional single input jump (MSIC), namely, the test vector has high fault coverage rate and low power consumption;
the broadcast module is used for broadcasting and expanding the original scan chains, and the broadcast circuit expands the test vectors into broadcast-based multi-dimensional single-input hopping (BMSIC) test patterns which can fill more scan chains through a multiplexing test generation structure, so that the area overhead of the test pattern generation circuit is reduced.
The clock control module comprises n stages of D triggers, the D end of the next stage of D trigger is connected with the Q end of the first stage of D trigger, and the clock ends of all the D triggers are connected with a clock ck 1; the output of the last stage is taken as clk2 clock, a clock clk1 is connected with the clock end of the reconstructed Johnson counter, and a clock clk2 is connected with the clock end of the linear feedback shift register.
The linear feedback shift register comprises m stages of D triggers and an exclusive-OR gate, wherein the connection mode of the exclusive-OR gate is related to the stage number m of the linear feedback shift register and is connected based on m stages of primitive polynomial modes. It is assumed here that the first input of the xor gate is connected to the Q terminal of the mth D flip-flop, the second input is connected to the Q terminal of the first D flip-flop, and the output of the xor gate is connected to the D terminal of the input of the first D flip-flop. Except that the input end of the first-stage D trigger is connected with the output of the exclusive-OR gate, the D ends of the other D triggers are connected with the Q end of the previous-stage D trigger, and the clock ends of all the D triggers are connected with a clock ck 2. Taking the Q end output of each stage of D flip-flop, and connecting the Q end output to the input of an exclusive OR gate of an exclusive OR network;
and reconstructing a Johnson counter, which comprises an L-level D trigger, an alternative multiplexer and a two-input AND gate. Two inputs connected to gate, first input connected to Rst signal, second input connected to L-th D flip-flop
Figure BDA0001479954080000051
The output end of the first selector is connected with the first multiplexer; the control end of the one-out-of-two multi-path selector is connected with a Mode signal, the first input of the one-out-of-two multi-path selector is connected with the output ends of the two-input AND gate, the second output of the one-out-of-two multi-path selector is connected with the Q end of the last stage D trigger, and the output end of the one-out-of-two multi-path; the D ends of the other D triggers are connected with the Q end of the previous D trigger, and the clock ends of all the D triggers are connected with the clock ck 1. Taking the Q end output of each stage of D flip-flop, and connecting the Q end output to the input of an exclusive OR gate of an exclusive OR network;
and the exclusive-OR network comprises m two-input exclusive-OR gates, one input of the first exclusive-OR gate is the 1 st bit of the s-bit seed vector, the other input of the first exclusive-OR gate is the 1 st bit of the L-bit J vector, and the like, one input of the exclusive-OR gate is the s-bit seed vector, and the other input of the exclusive-OR gate is the corresponding bit of the L-bit J vector. And respectively taking the outputs of the m-level exclusive-OR gates, and connecting the outputs to the exclusive-OR gate network input of the broadcasting module.
The broadcast module includes a broadcast controller and an exclusive-or gate network.
The broadcast controller is a two-bit linear feedback shift register composed of two stages of D triggers, and is controlled by a clock clk2 to output a two-bit broadcast vector B, wherein the first bit is connected with a second exclusive-OR gate, a fourth exclusive-OR gate and a fifth exclusive-OR gate of the broadcast module, and the second bit is connected with the first exclusive-OR gate, the second exclusive-OR gate, the third exclusive-OR gate, the fifth exclusive-OR gate and a sixth exclusive-OR gate of the broadcast module;
the exclusive-OR gate network comprises 4 two-input exclusive-OR gates and 2 three-input exclusive-OR gates, wherein the first two-input exclusive-OR gate has one input connected with a first original scan chain and the other input connected with one bit of a two-bit control vector generated by a broadcast controller, and the output is a 1 st scan chain; the first three-input exclusive-OR gate has one input connected with the first original scan chain and the other two inputs respectively connected with the two-bit broadcast vector of the broadcast controller, and the output is the 2 nd scan chain; the 1 st scan chain is directly output as a 3 rd scan chain; a second two-input exclusive-or gate, one input of which is connected with the first original scanning link and the other input of which is connected with the 2 nd bit of the broadcast vector and the output of which is the 4 th scanning chain; a third two-input exclusive-or gate, one input of which is connected with the 2 nd original scanning line, the other input of which is connected with the 1 st bit of the broadcast vector, and the output of which is the 5 th scanning chain; the 2 nd original scan chain is directly output as a 6 th scan chain; one input of the second three-input exclusive-or gate is connected with the 2 nd original scan chain, the other two inputs of the second three-input exclusive-or gate are respectively connected with the two-bit broadcast vector of the broadcast controller, and the output of the second three-input exclusive-or gate is the 7 th scan chain; a fourth two-input exclusive-or gate, one input of which is connected with the 2 nd original scanning link and the other input of which is connected with the 2 nd bit of the broadcast vector and the output of which is the 8 th scanning chain; and in the same way, the third scanning chain and the 4 th scanning chain, the 5 th scanning chain and the 6 th scanning chain, and the 7 th scanning chain and the 8 th scanning chain are connected to the XOR gate network of the broadcasting module to multiplex the broadcasting module.
Examples
And setting the tested circuit through full-scan design, wherein the number of scan chains before broadcasting is M, each scan chain is provided with one scan unit, the number of scan chains after broadcasting is M, the number of S bits of a seed vector generated by an LFSR is M, and the number of J vector bits generated by a reconstructed Johnson counter is L.
Through a large number of mathematical analyses and experiments, a scheme for optimally configuring the BMSIC test generator by configuring the J vector bit number L into L is obtained, and the scheme is called as a test contract constraint for short. The J vector number L is required to satisfy L which is more than or equal to m due to the limitation of a test pattern generation algorithm, the limitation is called test generation constraint for short, compared with test convention constraint, the constraint is required to satisfy, and the test convention constraint is optional optimization configuration on the researched test pattern generator on the premise of satisfying the test generation constraint. Obviously, when L ≧ m, both constraints are satisfied simultaneously, at which time L ≧ L is configured to achieve the optimal configuration. When L is less than m, the test generation constraint L is only required to be satisfied, wherein L is equal to m. According to the convention and the broadcast relationship of the researched test pattern, the broadcast relationship comprises M-4M, M bits of a seed vector and L bits (L-L) of a Johnson vector, and the following contents are assumed. Equal numbers of bits for the seed vector and the Johnson vector, respectively, are referred to herein as equal scan configurations.
At most, the LFSR with M bits can generate sequences with different states, the sequence is called as a maximum length sequence and is also called as an M sequence, and the LFSR connected based on a primitive polynomial feedback mode can generate the M sequence. The BMSIC test pattern in the text adopts the M sequence as a seed vector S by utilizing the characteristics that the M sequence has a long period and the randomness is close to a random sequence, wherein the LFSRs are LFSRs which can generate the M sequence based on primitive polynomial connection.
Because the conversion times between adjacent bits of the test vector are positively correlated with the test power consumption [7], the Johnson counter can generate the Johnson vector with low jump characteristics no matter between adjacent vectors or between adjacent bits of the same vector, and therefore the BMSIC test pattern generation method introduces the Johnson counter. The Johnson counter is reconstructed according to a graph generation algorithm, the problem that the Johnson counter cannot complete a data shift loading process is solved, the low power consumption characteristic of the Johnson counter is not changed, and the reconstructed Johnson counter is as shown in FIG. 2, wherein a Mode is a Mode selection end, when an input signal value of a Mode port is logic 1, the Johnson counter is in a counting Mode, and when the input signal value of the Mode port is logic 0, the Johnson counter is in a cyclic shift Mode. Actually participating in generating each piece of scan chain data are L encoding vectors J obtained after cyclic shift of the L-bit Johnson vector, namely L J vectors.
And an exclusive-or network, wherein the exclusive-or network is used for generating an original scan chain vector by performing a bit exclusive-or operation on a seed vector S generated by the LFSR and a vector J generated by a reconstructed Johnson counter, the LFSR generates a seed vector with m bits, which is denoted as S ═ S0, S1, S2, …, Sm-1, the reconstructed Johnson counter generates a J vector with L bits, which is denoted as J ═ J0, J1, J2, …, JL-1, and the bit exclusive-or result of the vector J and the seed vector S is denoted as X ═ X1, XL +1, X2L +1, …, X (m-1) L +1, and a specific exclusive-or principle is shown in fig. 3.
The broadcast module may expand the test patterns generated by the MSIC test pattern generation circuitry to fill a greater number of scan chain structures. To accommodate the requirements of the BIST scheme, a 2-chain extended to 8-chain XOR broadcaster architecture was designed, as shown in figure 4. The architecture includes an XOR gate network and a broadcast controller. The output X of the xor network block shown in fig. 3 is (X1, XL +1, X2L +1, …, X (m-1) L +1) to be shifted into the broadcast circuit as the original scan chain vectors C1, C2, respectively, C11, C12, C13, C14, C21, C22, C23, C24 representing the test vectors to be distributed to the scan chains. The broadcast controller is used for generating a broadcast vector B ═ (B0, B1) to control the broadcast network to reduce correlation between the expanded internal scan chain signals. Here, the broadcast controller is implemented by a 2-bit LFSR, and the 2-bit LFSR is loaded once in a complete test pattern generation process.
Mode of operation of circuit
(1) The clock control module of fig. 1 generates clocks clk1 and clk2, clk1 drives the reconstruction Johnson counter to complete J vector updates, clk2 drives the LFSR to complete seed vector updates, and scan-in is implemented.
(2) The original scan chain generation module of fig. 1 is composed of an LFSR, a reconstructed Johnson counter, and an exclusive or network. And the LFSR generates an S vector, the Johnson counter is reconstructed to generate a J vector, and the XOR network completes the XOR of the S vector and the J vector to generate original scan chain data.
(3) The broadcast module of fig. 1 broadcasts an extension to an original scan chain, and a specific broadcast circuit is shown in fig. 4, where C1 and C2 are original scan chain data, and C11, C12, C13, C14 and C21, C22, C23 and C24 are final scan chains applied to a circuit under test generated by xoring C1 and C2 with a broadcast vector B, respectively.
The specific broadcasting process is as follows:
① XOR the initial bits of each original scan chain with the broadcast vector to generate the initial bits of the 4 scan chains to be applied to the circuit under test;
② each complete original scan chain is expanded into 4 complete final scan chains over a scan depth of clock cycles;
③ generating a complete test pattern by the circuit to be broadcast, and updating a primary broadcast vector by the broadcast controller;
④ repeat steps ① - ③ until the broadcast of the original scan chains for all patterns is completed.
According to the broadcasting process, if M scan chains are actually required to be loaded on a circuit to be tested, the original scan chain generation module only needs to generate M/4 scan chains, and the scanning depth is kept unchanged, so that the requirements on the LFSR series for generating the seed vector and the reconstructed Johnson counter series for generating the J vector are reduced, and the hardware area overhead is reduced.
Test protocol
The modules are connected according to the relationship shown in fig. 1 to form a test pattern generation architecture with broadcast based on a pseudorandom sequence and a low-jump sequence, and the specific test steps are as follows:
the ① clock control module generates two clocks, clk1 and clk2, where the cycle of clk2 is 2L of clk1 cycles 2② clk2 runs for a clock cycle, drives an LFSR once, and updates an S vector once;
③ reconstructing the Johnson counter to enter a counting mode, clk1 running for one clock cycle, driving the Johnson counter to generate a J vector;
④ generating an initial bit of each original scan chain by XOR of the J vector and the S vector according to bit after generating a J vector, ⑤ generating an initial bit of 4 broadcast scan chains after the initial bit of each original scan chain passes through the broadcast circuit;
⑥ reconstructing the Johnson counter to enter a cyclic shift mode, clk1 obtaining a complete test pattern over a scan depth of clock cycles;
⑦ repeat steps ③ - ⑥ until the reconstructed Johnson counter counts 2L times;
⑧ clk1 jumps and repeats steps ② - ⑦ until the fault coverage of the circuit under test is met or the upper test length limit is reached.
BMSIC sequences were characterized as follows:
(1) periodicity of the cycle
The presumed test pattern BMSIC also has the characteristic of periodicity because the seed vector, the broadcast vector and the original scan chain vector before broadcast are all periodic, and the XOR operation belongs to the linear operation. The test pattern is mathematically analyzed, and if the seed vector S is [ S0, S1, S2, …, Sm-1], the vector J is [ J0, J1, J2, …, JL-1], the broadcast vector B is [ B0, B1], and the time t S, J, B can be expressed as:
S(t,x)＝S0(t)x0+S1(t)x1+…+Smxm
J(t,x)＝J0(t)x0+J1(t)x1+…+JL-1(t)xL-1(1)
B(t,x)＝B0(t)x0+B1(t)x1
according to the generation algorithm, the original input test vector is composed of part or all bits of the seed vector or the multiplexing of the seed vector, and can be expressed as:
Figure BDA0001479954080000091
in formula (2): and belongs to an integer, the specific value depending on the number of original inputs N and the number of seed vector bits m. Meanwhile, the k-th original scan chain vector can be represented as:
Figure BDA0001479954080000092
the vector in equation (3) represents the J vector applied to the kth scan chain.
Let the two pre-broadcast original scan chain vectors C1, C2 of the broadcaster shown in fig. 4 be denoted as, where. If the test vector of the ith scan chain after broadcasting is yes, the 8 scan chain vectors after broadcasting, C11, C12, C13, C14, C21, C22, C23 and C24, can be represented as:
Figure BDA0001479954080000093
Figure BDA0001479954080000094
C13＝V4q-1(t,x)＝Cq(t,x)
Figure BDA0001479954080000095
Figure BDA0001479954080000096
C22＝V4q+2(t,x)＝Cq+1(t,x)
Figure BDA0001479954080000097
Figure BDA0001479954080000098
in view of the above, the first complete scan chain vector loaded into the circuit under test can be expressed as:
Figure BDA0001479954080000099
in equation (5), when the original input applied to the circuit under test at time t is expressed, the first test pattern is different from the d-th test pattern or can be expressed as:
Figure BDA00014799540800000910
if and only if S (t)w,x)＝S(td,x)、B(tw,x)＝B(td,x)、
Figure BDA00014799540800000911
At the same time, when the utility model is in use,
Figure BDA0001479954080000101
is it true. The S period of the known seed vector is Ts＝2m-1, broadcast vector B period is TB＝22-1 ═ 3, from document [4]Knowing that the original scan chain vector C period before broadcast is TMSIC＝(2m-1) 2L, so BMSIC test patternsThe period is the least common multiple of the periods of the seed vector, the broadcast vector and the original scan chain vector, and can be specifically expressed as:
Figure BDA0001479954080000102
from the equation (7), the cycle of the BMSIC test pattern is related to the number of bits of the seed vector and the J vector, and the TBMSIC is larger than the TMSIC of the document [4] in the same arrangement. The larger the period of the test pattern, the better the pseudo-randomness of the test pattern samples, and the higher the fault coverage. The number of bits of the seed vectors S and J directly influences the hardware overhead, and the exponential relationship and the multiple relationship of the formula (7) enable a small number of vector bits to obtain a test pattern with a large period and good pseudo-randomness, so that the BMSIC test pattern can reduce the hardware overhead on the premise of obtaining satisfactory fault coverage.
The fault coverage rate of the BMSIC test pattern is counted through experimental simulation, the power consumption characteristic of the BMSIC test pattern is evaluated by using a Weighted Transfer Model (WTM) model [7], and finally, the excellent characteristic of small area overhead of a BMSIC test pattern generation structure is verified through area overhead evaluation.
BMSIC test generation performance:
theoretical analysis shows that the BMSIC test pattern has low power consumption characteristics and can obtain satisfactory fault coverage rate, and the performance of the BMSIC test pattern in the aspects of fault coverage rate, power consumption and area overhead is verified through specific simulation experiments and performance estimation. The RSFC and RTFC are set as the fixed fault coverage and the transition fault coverage, respectively. The experiment uses five larger circuits in ISCAS' 89 series as the tested circuit, and adopts 45nm process library of Nangate company.
(1) Fault simulation
The method comprises the steps of carrying out scanning synthesis on a tested circuit by using a scanning synthesis tool DFT _ Compiler of Synopsys, describing a test pattern generation algorithm by Perl language to realize test generation and test application, and finally completing fault simulation by using a fault simulation tool TetraMAX of Synopsys, wherein the result is shown in table 2, and the result is shown in table 2, so that the BMSIC method can obtain higher fault coverage rate compared with the MSIC method of the document [5] under the same configuration, and the test pattern required for achieving the high fault coverage rate is less than that of the LFSR method of the document [11 ]. Meanwhile, the corresponding fault coverage rates of the same tested circuit under different test generation configurations are different, which shows that the fault coverage rates are related to the test generation configurations.
Table 23 test generation method fault coverage comparison
Figure BDA0001479954080000103
Figure BDA0001479954080000111
(2) Power consumption assessment
The dynamic test power consumption of the tested circuit based on the scanning design comprises scanning shift-in power consumption, scanning shift-out power consumption and scanning capture power consumption according to different stages in the test process. Scan shift power consumption determines the average power consumption during testing, so the performance in terms of power consumption of the test pattern under study is evaluated herein by studying scan shift power consumption. For scan shift power consumption, i.e., scan-in power consumption and scan-out power consumption, document [8] proposes a method for evaluating shift power consumption by calculating the number of scan cell logic flips, which provides a method for calculating the number of scan cell logic flips due to the change of neighboring bits of a test vector, i.e., Weighted Transition Metric (WTM).
The estimation results of the power consumption of the scan shift-in and shift-out of the tested circuit are shown in tables 3 and 4. Wa and Wm are the average WTM value and the maximum WTM value of each test stage of a single test pattern respectively. 10000 groups of LFSR, MSIC and BMSIC test patterns are respectively applied to each tested circuit for experiment, the average WTM value is taken as Wa, and the maximum value is selected as Wm.
In Table 5, Rin, ROut are the percentage reduction in WTM values for each test generation method scan in, scan out, compared to LFSR. BMSIC reduced the shift-in WTM value by more than 70% and shift-out WTM value by more than 10% comparable to MSIC, a feature consistent with the results of section 2 leap forward analysis. In the experiment, the numbers of Johnson vector bits corresponding to tested circuits S13207, S15850, S35932, S38417 and S38584 are respectively 20, 17, 44, 41 and 36, and it can be found that the more the number of Johnson vector bits, the lower the power consumption of the shift of the correspondingly generated BMSIC test pattern is, which indicates that the power consumption is related to the number of bits of a reconstructed Johnson counter of the test pattern generation circuit.
Table 33 test generation method scan shift-in WTM value comparison
Figure BDA0001479954080000112
Figure BDA0001479954080000121
Table 43 test generation method scan shift out WTM value comparison
Figure BDA0001479954080000122
Table 53 test generation WTM value percent reduction
Figure BDA0001479954080000123
(3) Area evaluation
According to the circuit structure shown in fig. 1, the area overhead mainly includes: an m-bit LFSR to generate seed vectors, an L-bit reconstruction Johnson counter to generate J vectors, an xor network to generate original test patterns, a two-bit LFSR to generate broadcast vectors, and a broadcast circuit to generate final test patterns. And respectively obtaining the estimation result of the area overhead of each gate unit of the test pattern generating circuit according to the test generation constraint of the LFSR, MSIC and BMSIC test generation methods and the test convention constraint agreed in section 1.1. The area of each gate cell in the nandate 45nm process library is then translated with a single two input xor gate as a reference. The post-conversion results are shown in table 6, where Rdc represents the percent area savings of BMSIC compared to MSIC. From table 6, it can be seen that: compared with the MSIC method in the document [5], the BMSIC method can reduce the area of the same tested circuit under the same scanning configuration by about 50 percent. Meanwhile, the BMSIC method can save more area overhead when the number of scan chains of a tested circuit of a given scan design is more. Moreover, the larger the scale of the circuit to be tested is, the more outstanding the superiority is.
Area overhead comparison of Table 63 test Generation methods
Figure BDA0001479954080000124
Figure BDA0001479954080000131
。

Claims (1)

1. A built-in self-test structure with a broadcast structure is characterized by comprising a clock control module, an original scan chain generation module and a broadcast module; wherein the content of the first and second substances,
the clock control module is used for generating a clock for controlling the generation of the original anchor chain;
the original scan chain generation module is used for generating original scan chain data with low jump;
the broadcast module is used for completing the broadcast of all original scan chain vectors and generating a final test pattern;
the original scan chain generation module comprises a linear feedback shift register, a reconstructed Johnson counter and an exclusive or network;
the linear feedback shift register is used for generating a seed vector S;
reconstructing a Johnson counter for generating a J vector;
an exclusive or network for performing exclusive or of the S vector and the J vector to generate original scan chain data;
the clock control module comprises n stages of D triggers, wherein the D end of the next stage of D trigger is connected with the Q end of the first stage of D trigger, and the clock ends of all the D triggers are connected with a clock ck 1; taking the output of the last stage as a clk2 clock, connecting a clock clk1 with the clock end of the reconstructed Johnson counter, and connecting a clock clk2 with the clock end of the linear feedback shift register;
the linear feedback shift register comprises m-stage D triggers and an exclusive-OR gate, wherein a first input end of the exclusive-OR gate is connected with a Q end of the m-stage D trigger, a second input end of the exclusive-OR gate is connected with a Q end of the first-stage D trigger, and an output of the exclusive-OR gate is connected with an input D end of the first-stage D trigger; except that the input end of the first stage D trigger is connected with the output of the exclusive-OR gate, the D ends of the next stage D triggers of other D triggers are connected with the Q end of the previous stage D trigger, and the clock ends of all D triggers are connected with a clock ck 2; taking the Q end output of each stage of D flip-flop, and connecting the Q end output to the input of an exclusive OR gate of an exclusive OR network;
reconstructing a Johnson counter, wherein the Johnson counter comprises an L-level D trigger, an alternative multiplexer and a two-input AND gate; two inputs connected to gate, first input connected to Rst signal, second input connected to L-th D flip-flop
Figure DEST_PATH_BDA0001479954080000031
The output end of the first selector is connected with the first multiplexer; the control end of the one-out-of-two multi-path selector is connected with a Mode signal, the first input of the one-out-of-two multi-path selector is connected with the output ends of the two-input AND gate, the second output of the one-out-of-two multi-path selector is connected with the Q end of the last stage D trigger, and the output end of the one-out-of-two multi-path; the D ends of the other D triggers are all the D triggers of the next stage and are connected with the Q end of the D trigger of the previous stage, and the clock ends of all the D triggers are all connected with a clock ck 1; taking the Q end output of each stage of D flip-flop, and connecting the Q end output to the input of an exclusive OR gate of an exclusive OR network;
the exclusive-or network comprises m two-input exclusive-or gates, wherein one input of the first exclusive-or gate is the 1 st bit of the s-bit seed vector, the other input of the first exclusive-or gate is the 1 st bit of the L-bit J vector, and the like, one input of the exclusive-or gate is the s-bit seed vector, and the other input of the exclusive-or gate is the corresponding bit of the L-bit J vector; respectively taking the output of the m-level exclusive-OR gate, and connecting the output to the network input of the exclusive-OR gate of the broadcasting module;
the broadcasting module comprises a broadcasting controller and an exclusive-OR gate network; wherein the content of the first and second substances,
the broadcast controller is a two-bit linear feedback shift register composed of two stages of D triggers, is controlled by a clock clk2 and outputs a two-bit broadcast vector B, wherein the first bit is connected with a second exclusive-OR gate, a fourth exclusive-OR gate and a fifth exclusive-OR gate of the broadcast module, and the second bit is connected with the first exclusive-OR gate, the second exclusive-OR gate, the third exclusive-OR gate, the fifth exclusive-OR gate and a sixth exclusive-OR gate of the broadcast module;
the exclusive-OR gate network comprises 4 two-input exclusive-OR gates and 2 three-input exclusive-OR gates, wherein the first two-input exclusive-OR gate has one input connected with a first original scan chain and the other input connected with one bit of a two-bit control vector generated by the broadcast controller, and the output is a 1 st scan chain; the first three-input exclusive-OR gate has one input connected with the first original scan chain and the other two inputs respectively connected with the two-bit broadcast vector of the broadcast controller, and the output is the 2 nd scan chain; the 1 st scan chain is directly output as a 3 rd scan chain; a second two-input exclusive-or gate, one input of which is connected with the first original scan chain, and the other input of which is connected with the 2 nd bit of the broadcast vector and the output of which is the 4 th scan chain; a third two-input exclusive-or gate, one input of which is connected with the 2 nd original scan chain, the other input of which is connected with the 1 st bit of the broadcast vector, and the output of which is the 5 th scan chain; the 2 nd original scan chain is directly output as a 6 th scan chain; one input of the second three-input exclusive-or gate is connected with the 2 nd original scan chain, the other two inputs of the second three-input exclusive-or gate are respectively connected with the two-bit broadcast vector of the broadcast controller, and the output of the second three-input exclusive-or gate is the 7 th scan chain; a fourth two-input exclusive-or gate, one input of which is connected with the 2 nd original scan chain, the other input of which is connected with the 2 nd bit of the broadcast vector, and the output of which is the 8 th scan chain; and in the same way, the third scan chain and the 4 th scan chain, the 5 th scan chain and the 6 th scan chain, and the 7 th scan chain and the 8 th scan chain are connected to the exclusive-or gate network of the broadcasting module to multiplex the broadcasting module.
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* Cited by examiner, † Cited by third party
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US7770067B2 (en) * 2005-10-27 2010-08-03 International Business Machines Corporation Method for cache correction using functional tests translated to fuse repair
CN101614789A (en) * 2009-07-21 2009-12-30 西安交通大学 A kind of test graph builder of integrated circuit and method of testing thereof
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