CN101087129A - Full-speed pseudo random sequence generator using half speed clock - Google Patents

Abstract

The invention discloses a full speed pseudo-random sequence generator, it includes: low-speed pseudo-random sequence generating unit which includes the first low-speed pseudo-random sequence generator and the second low-speed pseudo-random sequence generator, the first low-speed pseudo-random sequence generator and the second low-speed pseudo-random sequence generator are constructed by N shift registers with setting function; multiple path selecting switch which is constructed by a group of selecting 1 from 2 gating switch controlled by compensated clock signal generated by CLK, it includes two transmission doors, the Pmos tube of the first transmission gate and Nmos tube of the second transmission gate use the same input to control CLK, Nmos tube of the first transmission gate and Pmos tube of the second transmission gate use the same input to control CLKN; output signal adjusting unit is composed by four phase inverters and adjusts output signal for OUT. The structure of the invention is easy, it can generate data rate which is two times higher than traditional pseudo-random sequence generator under condition that input control clock is not change.

Description

Adopt full speed pseudo-random sequence generator

Technical field

The present invention is mainly concerned with the pseudo random sequence generator field that is made of the CMOS transistor, refers in particular to a kind of employing full speed pseudo-random sequence generator.

Background technology

Integrated circuit is a kind of function element of complexity, and occurring some mistakes and defective in exploitation and production process is inevitably, for the quality and reliability that guarantees product need be monitored the quality and reliability of product by test.The methods of inserting pseudo random sequence generator that adopt realize built-in self-test more in integrated circuit.Therefore, the quality of pseudo-random data sequence generation circuit design directly has influence on the effect of self-test.Referring to pseudo-random sequence generator of the prior art shown in Figure 3,, can export pseudorandom sequence signal at output by insert logics such as XOR gate or NAND gate at different feedback loops.The shortcoming of this kind method is the frequency that the pseudo random sequence data rate maximum of output can only reach the input clock of control shift register, and it is very disadvantageous that this pseudo-random data sequence to high speed circuit produces.

Summary of the invention

The problem to be solved in the present invention just is: at the technical problem of prior art existence, the invention provides a kind of simple in structure, can be under the constant condition of input control clock, the data rate that generation doubles than traditional pseudo random sequence generator, adopt full speed pseudo-random sequence generator.

For solving the problems of the technologies described above, the solution that the present invention proposes is: a kind of employing full speed pseudo-random sequence generator is characterized in that it comprises:

Low speed pseudo-random signal generation unit, comprise the first low speed pseudo-random signal maker and the second low speed pseudo-random signal maker, the first low speed pseudo-random signal maker and the second low speed pseudo-random signal maker are formed by the shift register cascade of N band set function respectively, under unified input control clock CLK and asserts signal set control, produce the two paths of data frequency with the input clock frequency unanimity, phase place is identical but the different serial pseudo-random data of data sequence collection is denoted as sequence 1 and sequence 2;

The multidiameter option switch unit, adopt 2 of complementary clock signal control that CLK produces to select 1 gating switch to constitute by one group, this gating switch is made up of two transmission gates, the Pmos pipe of first group of transmission gate and the Nmos pipe of second group of transmission gate use same control input CLK, and the Nmos pipe of first group of transmission gate and the Pmos pipe of second group of transmission gate use same control input CLKN;

Output signal adjusting unit is made of 4 inverters, will realize last output OUT after the output signal adjustment of multidiameter option switch unit.

Compared with prior art, advantage of the present invention just is:

1, the present invention adopts full speed pseudo-random sequence generator to can be used for the High-speed I interface, and clock data recovery circuit, Serdes (serial transceiver) wait the pseudo-random signal of other high speed logic circuit structure built-in self-test to produce;

2, the present invention's test data speed of adopting full speed pseudo-random sequence generator to overcome the Pseudo-random number generator of traditional approach can not be higher than the shortcoming of input clock, use lower clock can obtain the high speed test signal, simplified the design difficulty of test circuit;

3, adopted modified model dynamic circuit structure in the present invention, made the stable fine of circuit working, anti-PVT changing capability is strong, can be applied to the more abominable occasion of various environment.

Description of drawings

Fig. 1 is the frame structure schematic diagram of the specific embodiment of the invention;

Fig. 2 is the circuit theory schematic diagram of the specific embodiment of the invention;

Fig. 3 is a frame structure schematic diagram of the prior art;

Fig. 4 is the circuit theory schematic diagram of band set function shift register.

Embodiment

Below with reference to the drawings and specific embodiments the present invention is described in further details.

Adopt two structures among the present invention, use the rising/trailing edge of clock signal that data are selected output simultaneously along sampling output.As depicted in figs. 1 and 2, the present invention adopts full speed pseudo-random sequence generator, it comprises: low speed pseudo-random signal generation unit, comprise the first low speed pseudo-random signal maker and the second low speed pseudo-random signal maker, the first low speed pseudo-random signal maker and the second low speed pseudo-random signal maker are formed by the shift register cascade of N band set function respectively, under unified input control clock CLK and asserts signal set control, it is consistent with input clock frequency to produce the two paths of data frequency, phase place is identical but serial pseudo-random data that the data sequence collection is different is denoted as sequence 1 and sequence 2; The multidiameter option switch unit, adopt 2 of complementary clock signal control that CLK produces to select 1 gating switch to constitute by one group, this gating switch is made up of two transmission gates, the Pmos pipe of first group of transmission gate and the Nmos pipe of second group of transmission gate use same control input CLK, the Nmos pipe of first group of transmission gate and the Pmos pipe of second group of transmission gate use same control input CLKN, two groups of transmission gates are under the control of clock, when CLK is 0, first group of transmission gate of conducting exported the signal of pseudo random sequence generator 1 this moment; When CLK was 1, second group of transmission gate of conducting exported the signal of pseudo random sequence generator 2 this moment.2 select 1 gating circuit switch respectively clock the above-mentioned first low speed pseudo-random signal maker of low/high level stage conducting and the second low speed pseudo-random signal maker in one group, promptly select output sequence 1 or sequence 2, generate new high speed serialization pseudo random sequence OUT1.Output signal adjusting unit is made of 4 inverters, is used for output signal OUT1 is adjusted back output OUT.By the Pmos pipe of the 1st, 2 grade of inverter in the adjusting inverter group and the ratio of the width of Nmos pipe, the i.e. duty ratio of the high/low level of scalable output OUT1.3rd, 4 grades of inverters drive Buffer, the ability of the driving heavy load of intensifier circuit as output.Because in a control clock clk cycle, respectively export 1 time the lower edge on clock, the serial pseudo random sequence of output can reach the twice of input clock, and this serial sequence collection be two-way Half Speed pseudo-random data maker data alternately output obtain, can predict and calculate.And can change the serial data sequence collection of final output by the feedback loop of adjusting the above-mentioned two-way pseudo random sequence generator of two-way.In like manner, a plurality of alternative output switches can be added, parallel duplex high speed pseudo-random data can be obtained by a plurality of outputs at above-mentioned two-way pseudo random sequence generator by clock CLK control.

Wherein, the shift register that adopts the band set function in the first low speed pseudo-random signal maker and the second low speed pseudo-random signal maker is as elementary cell (referring to shown in Figure 4), the previous stage output of this elementary cell is imported the formation traditional chain low speed pseudo random sequence generator (Pattern Generator) as shown in Figure 3 that joins end to end with the back one-level, this circuit structure can produce can precognition the pseudorandom cycle tests collection of order, and can pass through this pseudo random sequence generative circuit of asserts signal set initialization.The pseudo-random data speed that this kind circuit produces is consistent with the clock rate C LK of control shift register chain.Low speed pseudo-random signal generation unit among the present invention is under unified input control clock CLK and asserts signal set control, produce the two paths of data frequency with the input clock frequency unanimity, phase place is identical but the different serial pseudo-random data of data sequence collection is denoted as sequence 1 and sequence 2.When the set signal is input as 1, be 1 with all shift register set, this moment, two groups of low speed pseudo-random signal makers were output as 1, were in SM set mode.When the set signal was input as 0, two groups of low speed pseudo-random signal makers entered the displacement feedback states under the control of clock CLK.With first pseudo random sequence generator among Fig. 2 is example.At the rising edge of clock CLK, the output SO of the shift register D9 of this group inputs to the input SI of next stage shift register D8, and the SO of D8 exports the SI of D7 to simultaneously, and the rest may be inferred.Simultaneously, after the output SO of D0, D1, D7, D8 carried out XOR by three XOR gate, feedback inputed to the input SI of D9.Because the existence of XOR gate feedback, the class signal that causes importing the SI of D9 is similar to pseudo-random signal, and therefore the output of the SO of all shift registers of whole first pseudo-random generator end is pseudo-random signal.

In specific embodiment, referring to Fig. 1, Fig. 2 and shown in Figure 4, the shift register of band set function is exported feedback in the first low speed pseudo-random signal maker and the second low speed pseudo-random signal maker under three XOR gate logic controls, forms the pseudo random sequence generator of low speed.The first low speed pseudo-random signal maker is different with the XOR gate logic feedback position of the second low speed pseudo-random signal maker, so the pseudo random sequence of its generation is also inequality.Under the control of unified clock CLK and asserts signal, the first low speed pseudo-random signal maker and the second low speed pseudo-random signal maker produce the two paths of data frequency with the input clock frequency unanimity, phase place is identical but the different serial pseudo-random data of data sequence collection: sequence 1 and sequence 2.The multidiameter option switch unit is respectively under the control of clock CLK, the high/low level stage at CLK is selected output sequence 1 or sequence 2 from the first low speed pseudo-random signal maker and the second low speed pseudo-random signal maker respectively, forms new high speed output pseudo random sequence OUT1.By the output signal adjusting unit that 4 inverters constitute, the output waveform of OUT1 is adjusted, and the enhancing driving force obtains exporting OUT.As shown in Figure 4, the shift register of band set function, its data_in and serial_in are two data input pins, can intercourse.Set is an asserts signal, and clk is a clock signal input terminal.Shift register is traditional TSPC type edge triggered flip flop, and structure no longer provides.

Claims (1)

1, a kind of employing full speed pseudo-random sequence generator is characterized in that it comprises:

Low speed pseudo-random signal generation unit, comprise the first low speed pseudo-random signal maker and the second low speed pseudo-random signal maker, the first low speed pseudo-random signal maker and the second low speed pseudo-random signal maker are formed by the shift register cascade of N band set function respectively, under unified input control clock CLK and asserts signal set control, produce the two paths of data frequency with the input clock frequency unanimity, phase place is identical but the different serial pseudo-random data of data sequence collection is denoted as sequence 1 and sequence 2;

The multidiameter option switch unit, adopt 2 of complementary clock signal control that CLK produces to select 1 gating switch to constitute by one group, this gating switch is made up of two transmission gates, the Pmos pipe of first group of transmission gate and the Nmos pipe of second group of transmission gate use same control input CLK, and the Nmos pipe of first group of transmission gate and the Pmos pipe of second group of transmission gate use same control input CLKN;

Output signal adjusting unit is made of 4 inverters, is used for and will exports OUT after the output signal adjustment.