CN111030660B - Reset signal distribution circuit and electronic circuit system - Google Patents
Reset signal distribution circuit and electronic circuit system Download PDFInfo
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- CN111030660B CN111030660B CN201911071971.4A CN201911071971A CN111030660B CN 111030660 B CN111030660 B CN 111030660B CN 201911071971 A CN201911071971 A CN 201911071971A CN 111030660 B CN111030660 B CN 111030660B
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- 239000002699 waste material Substances 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/002—Switching arrangements with several input- or output terminals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
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Abstract
The application discloses a reset signal distribution circuit and an electronic circuit system, wherein the circuit comprises: the reset signal source and the signal distribution module are characterized in that p input interfaces in m input interfaces are respectively connected with the reset signal source, p output interfaces corresponding to the p input interfaces are used for outputting p paths of reset signals, at least one path of reset signals in the p paths of reset signals is connected with other q input interfaces in the m input interfaces, and q output interfaces corresponding to the other q input interfaces in the n output interfaces output q paths of reset signals. The application takes the multipath reset signals distributed by the original reset signals as input signals, and accesses the input interface of the signal distribution module again, so that a plurality of reset signals can be obtained without arranging a plurality of distribution modules, the hardware cost is greatly reduced while the signal integrity is ensured, and a large number of reset signals can be flexibly obtained by only using one multiple-input multiple-output signal distribution module.
Description
Technical Field
The application relates to the field of electronic circuits, in particular to a reset signal distribution circuit and an electronic circuit system.
Background
In modern electronic circuit systems, more and more functions are implemented by special function chips, so that more and more special function chips are integrated on a circuit board of the electronic circuit system, and the function chips are all logic chips. Because the logic chips are required to maintain a factory default state after the power supply of the system is stable, the logic chip design manufacturer generally reserves a signal pin as an input interface of a reset signal in order to realize the action, but along with the continuous improvement of the complexity of an electronic circuit system, the more special functional chips are used on a system board, and the more the reset signals are needed.
In the prior art, as shown in fig. 1, an original reset signal is distributed by a distribution module to obtain n reset signals for driving n logic chips. Wherein the distribution module is of the type of one input multiple outputs. Although the design scheme well solves the problem of insufficient driving capability when one path of reset signal drives a plurality of chips, the output channels of the distribution modules are limited, and if the system needs more reset signals, the distribution modules are required to be designed, so that the system circuit design is more complex, or when the system reset signal requirement is smaller than the output channels of the distribution modules, the waste of hardware resources is caused.
In another design manner of reset distribution, a programmable logic device is used to realize one-drive-multiple distribution design of reset signals, as shown in fig. 2, the design manner can flexibly realize the reset distribution design, reset signals output by each path are all defined in a programmable manner, and a command can be issued to the programmable logic device through a management interface to realize independent reset output of each path, so that a software reset function is realized. However, using programmable logic devices to implement reset distribution and software reset functions is costly and typically employed in high-end electronic circuitry.
Disclosure of Invention
The application aims to solve the problem of high cost and resource waste caused by the fact that a plurality of modules are required to be arranged for multi-path reset output or a programmable logic device is adopted to output a reset signal in the prior art, thereby providing a reset signal distribution circuit and an electronic circuit system.
In one aspect of the present application, there is provided a reset signal distribution circuit including:
a reset signal source for generating an original reset signal;
the signal distribution module comprises m input interfaces and n output interfaces, p input interfaces in the m input interfaces are respectively connected with the reset signal source, p output interfaces corresponding to the p input interfaces are used for outputting p paths of reset signals, at least one path of reset signals in the p paths of reset signals is connected with other q input interfaces in the m input interfaces, q output interfaces corresponding to the other q input interfaces in the n output interfaces output q paths of reset signals, wherein m, n, p, q is a positive integer, m is more than or equal to p+q, and n is more than or equal to p+q.
Optionally, the m=n, and the m input interfaces are in one-to-one correspondence with the n output interfaces.
Optionally, p is greater than or equal to q, and at most p input interfaces in the m input interfaces are connected with the same reset signal source.
Optionally, the m input interfaces include a plurality of groups of q input interfaces, and each of the p reset signals is connected to one of the m input interfaces.
Optionally, the value of p is 3.
Optionally, the signal distribution module is a multi-path buffer, and is used for realizing multi-path distribution of the input reset signal and stabilizing the signal quality of the output reset signal.
Optionally, the signal distribution module is a relay circuit supporting multiple input multiple output.
Optionally, the reset signal source includes:
a system power supply for supplying power;
the first end of the resistor is connected with the system power supply;
the first end of the capacitor is connected with the second end of the resistor, and the second end of the capacitor is grounded;
an output interface is arranged between the second end of the resistor and the first end of the capacitor, and is connected with the signal distribution module and used for outputting the original reset signal.
Optionally, the reset signal source includes:
a system power supply for supplying power;
and the reset chip is respectively connected with the system power supply and the signal distribution module and is used for generating the original reset signal.
In another aspect of the embodiment of the present application, there is also provided an electronic circuit system including: the reset signal distribution circuit described above.
According to the embodiment of the application, one path of original reset signal is adopted, the multipath reset signals distributed by the original reset signal are used as input signals through the multipath buffer or the relay circuit, the input interfaces of the signal distribution modules are accessed again, a plurality of distribution modules are not required to be arranged, a plurality of reset signals can be obtained, the integrity of the signals is ensured, the hardware cost is greatly reduced, and a large number of reset signals can be flexibly obtained only by using one multiple-input multiple-output signal distribution module.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a reset signal distribution circuit according to a first embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a reset signal distribution circuit according to a second embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a reset signal distribution circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a reset signal source according to an embodiment of the present application;
FIG. 5 is a schematic diagram of another reset signal source according to an embodiment of the present application;
FIG. 6 is a schematic diagram of another reset signal distribution circuit according to an embodiment of the present application;
fig. 7 is a schematic diagram of a reset signal distribution circuit according to another embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
An embodiment of the present application provides a reset signal distribution circuit, as shown in fig. 3, including: a reset signal source 10 for generating an original reset signal; the signal distribution module 20 comprises m input interfaces and n output interfaces, wherein p input interfaces in the m input interfaces are respectively connected with the reset signal source, p output interfaces corresponding to the p input interfaces are used for outputting p paths of reset signals, at least one path of reset signals in the p paths of reset signals is connected with other q input interfaces in the m input interfaces, q output interfaces corresponding to the other q input interfaces in the n output interfaces output q paths of reset signals, wherein m, n, p, q is a positive integer, m is greater than or equal to p+q, and n is greater than or equal to p+q.
In the embodiment of the application, the original reset signals generate p reset signals, and at least one path of the p reset signals is connected with other q input interfaces to generate q reset signals, so that (p+q-1) reset signals can be obtained at least under the condition of using one signal distribution module.
According to the embodiment of the application, one path of original reset signal is adopted, multiple paths of reset signals distributed by the original reset signal are used as input signals, and are accessed to the input interface of the signal distribution module again, so that a plurality of reset signals can be obtained without arranging a plurality of distribution modules, the integrity of the signals is ensured, the hardware cost is greatly reduced, and a large number of reset signals can be flexibly obtained by only using one multi-input multi-output signal distribution module.
In the embodiment of the present application, m=n, and the m input interfaces are in one-to-one correspondence with n output interfaces. In order to ensure efficient utilization of resources, the input interfaces and the output interfaces remain in consistent numbers.
Further optionally, p is greater than or equal to q, and at most p input interfaces in the m input interfaces are connected with the same reset signal source. Wherein p is preferably 3. Because reset signals are a critical signal in electronic circuitry design, a single reset signal is typically used to drive up to three logic chips for design considerations of system reset reliability.
In the embodiment of the application, the m input interfaces comprise a plurality of groups of input interfaces, each group of q input interfaces, and each path of reset signal in the p paths of reset signals is connected with one group of input interfaces in the m input interfaces. As shown in fig. 3, the reset signals 1-p are reset signals output by the first set of output interfaces, and the reset signals 1_1-1_q are reset signals output by the second set of interfaces.
In the embodiment of the application, the signal distribution module is a multi-path buffer or a relay circuit supporting multiple inputs and multiple outputs, and is used for realizing multi-path distribution of the input reset signals and stabilizing the signal quality of the output reset signals.
An optional reset signal source in an embodiment of the present application is shown in fig. 4, and includes: a system power supply for supplying power; the first end of the resistor is connected with the system power supply; the first end of the capacitor is connected with the second end of the resistor, and the second end of the capacitor is grounded; an output interface is arranged between the second end of the resistor and the first end of the capacitor, and is connected with the signal distribution module and used for outputting the original reset signal. The capacitor can be a nonpolar capacitor or a capacitor with polarity requirement, such as an electrolytic capacitor, and the anode of the capacitor is required to be connected with the other end of the resistor, and the cathode of the capacitor is required to be grounded.
Another alternative reset signal source is shown in fig. 5, which includes: a system power supply for supplying power; and the reset chip is respectively connected with the system power supply and the signal distribution module and is used for generating the original reset signal.
Specifically, as shown in fig. 3, the multiple-path buffer uses N input/N output types, which is different from the type of one input/N output mentioned in the prior art, and the embodiment of the application can also realize the reliable design of multiple one drive of the reset signal in the circuit system. In the embodiment of the application, any one of the two modes can be adopted as the original signal source, and in order to ensure the signal quality and the driving capability of the reset signals, each path of reset signals does not drive more than three reset input interfaces at most. As shown in fig. 3, the original reset signal is used as the input signal of the previous three channels in the multi-channel buffer, in the figure, the reset signal 1, the reset signal 2 and the reset signal p (p < =3) correspond to the output signal of each channel, when the main reset signal changes from high level to low level for performing the reset operation, the reset signal 1, the reset signal 2 and the reset signal 3 also change from high level to low level, the delay time of the low level is determined by the level delay time of the main reset signal, meanwhile, the reset signal 1 can be used as the input signal of the other three channels of the multi-channel buffer in turn, so as to obtain the reset signal 1_1, the reset signal 1_2 and the reset signal 1_q (q < =3), and the reset signal 1 can be regarded as the main reset signal, so that the multi-channel reset signal can be generated in a reciprocating way, and in particular, the number of channels of the multi-channel buffer can be generated, so that the multi-channel reset signal can be flexibly generated according to the requirement of the system reset signal.
An alternative reset signal distribution circuit embodiment of the present application is shown in fig. 6, wherein a 9-channel multi-channel buffer is used to design the reset distribution circuit, and on the premise of ensuring signal quality, 7 paths of reset signals can be generated at most, and the first two output signals are respectively used as the other two paths of input signals in turn in the figure, thereby generating 7 paths of reset signals. An alternative embodiment is shown in fig. 7, where the previous three outputs may also be used as the remaining three two inputs, thereby generating a 6-way reset signal. Therefore, the input and output can be flexibly matched according to the system reset requirement on the basis of multiple channels of the multi-channel buffer.
The embodiment of the application also provides an electronic circuit system, which comprises the reset signal distribution circuit. Of course, the electronic circuit system further comprises various logic chips, and the reset signal distribution circuit provides reset signals for the logic chips.
As can be seen from the above description, the technical solution adopted in the embodiments of the present application can flexibly build the reset distribution circuit according to the requirement of the reset signal in the electronic circuit system, simplify the design of the reset circuit, and reduce the material cost.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While obvious variations or modifications are contemplated as falling within the scope of the present application.
Claims (8)
1. A reset signal distribution circuit, comprising:
a reset signal source for generating an original reset signal;
the signal distribution module comprises m input interfaces and n output interfaces, p input interfaces in the m input interfaces are respectively connected with the reset signal source, p output interfaces corresponding to the p input interfaces are used for outputting p paths of reset signals, at least one path of reset signals in the p paths of reset signals is connected with other q input interfaces in the m input interfaces, q output interfaces corresponding to the other q input interfaces in the n output interfaces output q paths of reset signals, wherein m, n, p, q is a positive integer, m is more than or equal to p+q, and n is more than or equal to p+q;
the signal distribution module is a multipath buffer and is used for realizing multipath distribution of input reset signals and stabilizing the signal quality of output reset signals;
the reset signal source includes:
a system power supply for supplying power;
the first end of the resistor is connected with the system power supply;
the first end of the capacitor is connected with the second end of the resistor, and the second end of the capacitor is grounded;
an output interface is arranged between the second end of the resistor and the first end of the capacitor, and is connected with the signal distribution module and used for outputting the original reset signal.
2. The reset signal distribution circuit according to claim 1, wherein the m=n, and the m input interfaces are in one-to-one correspondence with the n output interfaces. A 'V' -shaped structure
3. The reset signal distribution circuit according to claim 1, wherein p is greater than or equal to q, and at most p of the m input interfaces are connected to the same reset signal source.
4. The reset signal distribution circuit of claim 1, wherein the m input interfaces comprise a plurality of sets of q input interfaces, each of the p reset signals being coupled to one of the m input interfaces.
5. The reset signal distribution circuit according to any one of claims 1 to 4, wherein the value of p is 3.
6. The reset signal distribution circuit according to any one of claims 1 to 4, wherein the signal distribution module is a relay circuit supporting multiple input multiple output.
7. The reset signal distribution circuit according to any one of claims 1 to 4, wherein the reset signal source includes:
and the reset chip is respectively connected with the system power supply and the signal distribution module and is used for generating the original reset signal.
8. An electronic circuit system, comprising: the reset signal distribution circuit of any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911071971.4A CN111030660B (en) | 2019-11-05 | 2019-11-05 | Reset signal distribution circuit and electronic circuit system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911071971.4A CN111030660B (en) | 2019-11-05 | 2019-11-05 | Reset signal distribution circuit and electronic circuit system |
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| Publication Number | Publication Date |
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| CN111030660A CN111030660A (en) | 2020-04-17 |
| CN111030660B true CN111030660B (en) | 2023-11-24 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5652529A (en) * | 1995-06-02 | 1997-07-29 | International Business Machines Corporation | Programmable array clock/reset resource |
| CN104202034A (en) * | 2014-08-13 | 2014-12-10 | 深圳市亚泰光电技术有限公司 | Circulating multichannel selection circuit system |
| CN104378093A (en) * | 2014-11-17 | 2015-02-25 | 锐迪科创微电子（北京）有限公司 | Power-on reset method and circuit using MIPI standard circuit |
| CN109408292A (en) * | 2018-10-31 | 2019-03-01 | 迈普通信技术股份有限公司 | A kind of reset circuit and electronic equipment |
| CN109994064A (en) * | 2018-01-02 | 2019-07-09 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit and its driving method and display device |
-
2019
- 2019-11-05 CN CN201911071971.4A patent/CN111030660B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5652529A (en) * | 1995-06-02 | 1997-07-29 | International Business Machines Corporation | Programmable array clock/reset resource |
| CN104202034A (en) * | 2014-08-13 | 2014-12-10 | 深圳市亚泰光电技术有限公司 | Circulating multichannel selection circuit system |
| CN104378093A (en) * | 2014-11-17 | 2015-02-25 | 锐迪科创微电子（北京）有限公司 | Power-on reset method and circuit using MIPI standard circuit |
| CN109994064A (en) * | 2018-01-02 | 2019-07-09 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit and its driving method and display device |
| CN109408292A (en) * | 2018-10-31 | 2019-03-01 | 迈普通信技术股份有限公司 | A kind of reset circuit and electronic equipment |
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