CN100508412C - Radio-frequency chip structure circuit of radio communication and method for transmitting-receiving radio-frequency control word - Google Patents
Radio-frequency chip structure circuit of radio communication and method for transmitting-receiving radio-frequency control word Download PDFInfo
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- CN100508412C CN100508412C CNB2006101170128A CN200610117012A CN100508412C CN 100508412 C CN100508412 C CN 100508412C CN B2006101170128 A CNB2006101170128 A CN B2006101170128A CN 200610117012 A CN200610117012 A CN 200610117012A CN 100508412 C CN100508412 C CN 100508412C
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Abstract
The invention discloses one wireless communication radio chip structure circuit and its receive method, wherein, running two registers structures inside radio chips with one store current work time gap radio control words and with other store next work time gap radio control words; between front and back work time gap, through adding one control line and m address lines to send address control words to trigger two memory sets transfer and to determine the register number.
Description
Technical field
The invention belongs to wireless communication field, relate in particular to a kind of wireless communication RF chip structure circuit and radio frequency control word receiving/transmission method.
Background technology
In wireless communication terminal, radio frequency chip needs baseband chip to pass through 3 line (DATA at different communications status, CLK, LE) serial transmission radio frequency control word (as shown in Figure 1), carry out such as the switching frequency synthesizer Frequency point, change charge pump electric current and the control of internal simulation circuit or the like operation, wherein radio frequency chip receives the control operation of LE signal triggering at rising edge or the trailing edge sampling DATA of CLK.Along with radio frequency chip to low-power consumption, the multifunctional direction development, its corresponding figure place and number that satisfies the radio frequency control word of maximum CLK frequency increases, but fix the change-over time of the communications status of TDD communication protocol regulation, the time slot switching time (SLOT Transfer Time) that is different carrier frequencies is fixing, so that the whole transmitting time of radio frequency control word (figure place generally surpass 24) occurred and exceed the time slot situation of switching time (as shown in Figure 2).Present counter-measure is to utilize two 3 lines or many 3 lines, but still does not overcome the long problem of control word transmitting time on single 3 lines; And if the radio frequency control word is realized with memory circuitry fully, can expend a large amount of hardware spendings again.
Summary of the invention
One of technical issues that need to address of the present invention are to provide a kind of wireless communication RF chip structure circuit, to overcome the overtime defective of radio frequency control word transmitting time in the prior art.
Technical scheme at above technical problem is: comprise radio frequency chip analog module, shift register, radio frequency chip 3 lines, be data wire (DATA), clock cable (CLK) and enable signal line (LE), the three-way shift register respective pins that is connected to respectively is characterized in that also comprising registers group 1 and registers group 2, register address controller and relevant pin thereof; Shift register, registers group 1, registers group 2 and radio frequency chip analog module are electrically connected successively, when the radio frequency control word of registers group 2 at the current communication time slot of storage, and the radio frequency control word of the next communication time slot of registers group 1 storage; Above-mentioned register address controller directly is connected with registers group 1, the relevant pin of this registers group 1 (1) is connected with address control line (ADD) with the control line (CNT0) of this register address controller (5) respectively, is used to the register value that determines that registers group 1 is transmitted to registers group 2.
Register value promptly refers to transmit the radio frequency control word by the needs of address control word that transmits on register controller, the address control line and the common decision of clock control line.
Described registers group 1 is identical with the register quantity that registers group 2 is comprised.
Described address control line can be set to the m root, and (size as registers group is n, and promptly described registers group 1 of registers group and registers group 2 contain n register, also is that the radio frequency control word is n, and then m need satisfy n=2m or 2m-1≤n≤2
m), also can be set to 1.When the address control line is set to the m root, control line that is connected with register address controller (CNT0) and m root address control line (ADD0, ADD1, ADD2......ADDm) accept the address control word in protection section blanking time of work at present time slot and the buffer space time period of next working time slot, the parallel address control word that sends comes trigger register group 1 to be worth transmission to registers group 2; When the address control line was set to 1, the control line that is connected with register address controller (CNT0) and this root address control line serial sent the address control word and come trigger register group 1 to be worth transmission to registers group 2.
Be provided with logical circuit in the described register address controller, this logical circuit definition address control word and registers group 1 are to the corresponding relation of the value of the radio frequency control word of registers group 2 transmission, according to different address control words, registers group 1 is transmitted the value of radio frequency control word to registers group 2 when time slot switches.At the address control word of m root address control line, the logic in this logical circuit will determine the radio frequency control word that registers group 1 is transmitted to registers group 2.
Another technical problem that the present invention need solve is to provide a kind of radio frequency control word receiving/transmission method, realizes this method by the wireless communication RF chip structure circuit of technique scheme one.
It is characterized in that may further comprise the steps:
1) initial condition, in previous working time slot (working slot A), one group of radio frequency control word that is used to control the radio frequency chip analog circuit state of storage in the registers group 2, in this working time slot (working slot A), remove simultaneously in buffer space (Ramp) time period and protection interval (Guard) other times section after the time period, shift register receives n the radio frequency control word of controlling next working time slot (working slot B) state successively from 3 line interfaces, and n represents contained the number of registers in the described registers group;
2) shift register is temporary to registers group 1 with the radio frequency control word that receives;
3) in the protection of previous working time slot (working slot A) at interval in buffer space (Ramp) scope continuous time time period of (Guard) time period and next working time slot (working slot B), receiver address control word on the control signal wire that is connected with the register address controller respective pin and the address signal line, with the register value of decision registers group 1 (1) to registers group 2 (2) transmission, and trigger register group 1 transmits operation to registers group 2, and described registers group 1 is identical with the register quantity that registers group 2 is comprised;
4) enter next working time slot, repeat above 1)-3) step.
The described the 1st) control word in the registers group 2 is used to control the radio frequency chip analog circuit state in the step.Described registers group 1,2 contained register numbers are the number of radio frequency control word, and the address control word radio frequency control word that actual needs sends when determining that former and later two working time slots switch, the control word of Fa Songing is 7 if desired, then every group of registers group needs 7 eight bit registers, and correspondingly shift register receives 7 radio frequency control words successively from 3 line interfaces.
At each working time slot, the radio frequency control word of registers group 2 is corresponding with it, and promptly the register value in the registers group 2 has determined the state of a control of connected radio frequency chip analog circuit.
The invention has the beneficial effects as follows, in the framework of two registers group of the inner utilization of radio frequency chip, the radio frequency control word of a register set stores work at present time slot, the radio frequency control word of the next working time slot of another register set stores; At former and later two working time slots in switching time, the serial or send the address control word concurrently and trigger two value transmission operations between the registers group respectively of 1 control line by increasing, 1 address wire or 1 control line, m bar address wire, thereby improved the configuration speed of radio frequency chip radio frequency control word, satisfy communication time slot switching time, solved the overtime technical problem of prior art control word transmitting time.In addition, the CLK that realizes in the present invention is on the interface of 1.92MHz, the transmission time of address control word between working time slot is 2.5us, be 52.1us the switching time less than adjacent time-slots, and the reception of radio frequency control word does not influence the message segment of working time slot, satisfies the switching requirement of adjacent working time slot.The address control word has determined the quantity of the data passes between two registers group, has embodied the configuration flexibility of interface.
Description of drawings
Fig. 1 is the radio frequency control word sequential schematic diagram of 3 line radio frequency chips of prior art;
Fig. 2 exceeds the adjacent time-slots sequential schematic diagram of switching time for the whole transmitting time of radio frequency control word in the prior art;
Fig. 3 sends the sequential chart of radio frequency control word when switching for two adjacent communication time slots of the present invention in the PAS terminal seamless switch-over system;
Fig. 4 is the view of two registers group of working time slot of the present invention and storage radio frequency control word;
Fig. 5 is the hardware circuit schematic diagram that radio frequency chip 3 line configuration interfaces of the present invention are realized, i.e. the wireless communication RF chip structure circuit diagram of technical solution of the present invention one.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is elaborated.
As Fig. 5, the wireless communication RF chip structure circuit of indication of the present invention, comprise radio frequency chip analog module 3, shift register 4, radio frequency chip 3 lines: data wire (DATA), clock (CLK) and enable signal (LE), three-wayly be connected with shift register 4 respective pins respectively, also comprise registers group 1 (1) and registers group 2 (2), register address controller 5 and relevant pin thereof; Shift register 4, registers group 1 (1), registers group 2 (2) and analog module (3) are electrically connected successively; Register address controller 5 is connected with registers group 1, and (ADD0, ADD1 ADD2) connect its relevant pin, and each registers group is made of 78 register with this control line (CNT0) and address control line respectively.All pins all are connected with baseband chip IO mouth among the figure.
The radio frequency chip of present embodiment is needing to send 7 Word (be the radio frequency control word, each radio frequency control word has 8 bits, promptly 8) by previous working time slot in a back working time slot transfer process.Framework two registers group of the inner utilization of radio frequency chip (it is 8 register that each registers group all contains 7 width), the radio frequency control word of a register set stores work at present time slot, the radio frequency control word of the next working time slot of another register set stores; At former and later two working time slots in switching time, trigger two register value transmission operations between the storage register group and (need satisfy n=2 according to m by increasing the parallel address control word that sends of 3 address wires
mPerhaps 2m
-1≤ n≤2
m, present embodiment n=7, then address control line radical m should be 3), these address control words have determined the quantity of the register value of transmission simultaneously.
In conjunction with Fig. 4 and Fig. 5, at first, in previous working time slot, the control word of registers group 2 is in the state of this working time slot of control, in this working time slot, receive the radio frequency control word Word of 7 next working time slot states of control simultaneously in the other times section the time period successively from 3 line interfaces except Ramp time period and Guard, temporary in registers group 1.
Then in the Guard time periods 41.7 μ s of previous working time slot (as the Working_Slot among Fig. 4 or the Working_Slot_A among Fig. 5) and the next working time slot Ramp time periods 10.4 μ s scope of (as the Working_Next_Slot among Fig. 4 or the Working_Slot_B among Fig. 5), from CNT0, ADD0, ADD1, receiver address control word on the ADD2 holding wire, address control word have determined the register value that registers group 1 is transmitted to registers group 2.
As the address that now receives 3 address wires is ADD[2:0]=3 ' b111 (be ADD2=1, ADD1=1, ADD0=1), expression has write the value of corresponding 7 registers in the registers group 1 in the registers group 2.Enter next working time slot (as the Working_Next_Slot among Fig. 4 or the Working_Slot_B among Fig. 5) afterwards, repeat above step.
Following table is the address control word and the corresponding relation of registers group 1 to the register value of registers group 2 transmission of logical circuit set in the present embodiment register controller 5 definition.
| When time slot switches, the register value that registers |
ADD[2:0] |
| Word?I，II，III，IV，V，VI，VII | 111 |
| Word?I，II，III，IV，V，VI | 110 |
| Word?I，II，III，IV，V | 101 |
| Word?I，II，III，IV | 100 |
| Word?I，II，III | 011 |
| Word?I，II | 010 |
| Word?I | 001 |
As can be known from the above table, although original definition need be transmitted 7 Word, if but when reality is tested, find time slot only need transmit 3 radio frequency control words (being respectively Word I, Word II and Word III) when switching and other four registers of 2 li of registers group do not need to change, ADD[2:0 then]=011 get final product.In the radio frequency chip of present embodiment, name 7 registers to be respectively A, B, C, D, E, F, G, corresponding respectively transmit the radio frequency control word be Word I, Word II, WordIII ... and WordVII.
In certain working time slot, the radio frequency control word of registers group 2 is corresponding with it, and registers group 1 receives the radio frequency control word of the next working time slot state of control.This shows each working time slot and analog module state one-to-one relationship, ratio is as when working time slot A (Working_SLOT_A), the radio frequency control word of registers group 2 is being controlled this time slot A corresponding simulating circuit state, and when working time slot B (Working_SLOT_B), the radio frequency control word of registers group 2 is being controlled this time slot B corresponding simulating circuit state.
As shown in Figure 5, in working time slot A (Working_SLOT_A), the value of registers group 2 is the radio frequency control word A of this state of control, and the value of registers group 1 is the radio frequency control word B of the next working time slot B of control (Working_SLOT_B); In working time slot B, the value of registers group 2 is radio frequency control word B, and the value of registers group 1 is radio frequency control word C; Next working time slot C is similar.
Though disclose the preferred embodiments of the present invention, those skilled in the art will appreciate that any various modifications, interpolation and replacement all belong to protection scope of the present invention under the situation of open scope in not deviating from claims of the present invention.
Claims (8)
1, a kind of wireless communication RF chip structure circuit, comprise radio frequency chip analog module (3), shift register (4), radio frequency chip 3 lines, be data wire (DATA), clock cable (CLK) and enable signal line (LE), three-way shift register (4) respective pins that is connected to respectively is characterized in that also comprising registers group 1 (1) and registers group 2 (2), register address controller (5) and relevant pin thereof; Shift register (4), registers group 1 (1), registers group 2 (2) and this radio frequency chip analog module (3) are electrically connected successively, when the radio frequency control word of registers group 2 (2) at the current communication time slot of storage, the radio frequency control word of the next communication time slot of registers group 1 (1) storage; Registers group 1 is identical with the register quantity that registers group 2 is comprised;
Register address controller (5) directly is connected with registers group 1 (1), the relevant pin of this registers group 1 (1) is connected with the address control line with the control line (CNT0) of this register address controller (5) respectively, is used to the register value that determines that registers group 1 is transmitted to registers group 2.
2, wireless communication RF chip structure circuit as claimed in claim 1 is characterized in that described address control line can be set to the m root, and m need satisfy n=2
mPerhaps 2
M-1≤ n≤2
mN represents contained the number of registers in described registers group 1 and the registers group 2; when the address control line is set to the m root; control line (CNT0) that is connected with register address controller (5) and m root address control line (ADD0; ADD1, ADD2 ...; ADDm) accept the address control word in protection section blanking time of work at present time slot and the buffer space time period of next working time slot, the parallel address control word that sends comes trigger register group 1 to be worth transmission to registers group 2.
3, wireless communication RF chip structure circuit as claimed in claim 1 is characterized in that described registers group 1 and registers group 2 be made up of 7 eight bit registers.
4, wireless communication RF chip structure circuit as claimed in claim 1, it is characterized in that being provided with logical circuit in the described register address controller (5), this logical circuit definition address control word and registers group 1 are to the corresponding relation of the value of the radio frequency control word of registers group 2 transmission, according to different address control words, registers group 1 is transmitted the value of radio frequency control word to registers group 2 when time slot switches.
5, a kind of radio frequency control word receiving/transmission method is characterized in that may further comprise the steps:
1) initial condition, in previous working time slot (working slot A), one group of radio frequency control word that is used to control the radio frequency chip analog circuit state of storage in the registers group 2, in this working time slot (working slot A), remove simultaneously in buffer space (Ramp) time period and protection interval (Guard) other times section after the time period, shift register (4) receives n the radio frequency control word of controlling next working time slot (working slot B) state successively from 3 line interfaces, and n represents contained the number of registers in the described registers group;
2) shift register (4) is temporary to registers group 1 (1) with the radio frequency control word that receives;
3) in the protection of previous working time slot (working slot A) at interval in buffer space (Ramp) scope continuous time time period of (Guard) time period and next working time slot (working slot B), receiver address control word on the control line that is connected with register address controller (5) respective pin and the address control line, with the register value of decision registers group 1 (1) to registers group 2 (2) transmission, and trigger register group 1 transmits operation to registers group 2, and described registers group 1 is identical with the register quantity that registers group 2 is comprised;
4) enter next working time slot, repeat above 1)-3) step.
6, radio frequency control word receiving/transmission method as claimed in claim 5 is characterized in that the contained register number of described registers group 1, registers group 2 is identical with radio frequency control word number.
7, radio frequency control word receiving/transmission method as claimed in claim 5 is characterized in that described each registers group can be made up of 7 eight bit registers, and correspondingly shift register (4) receives 78 radio frequency control word successively from 3 line interfaces.
8, radio frequency control word receiving/transmission method as claimed in claim 5 is characterized in that: at each working time slot, and the state of the radio frequency chip analog module (3) of corresponding this working time slot of the radio frequency control word of registers group 2 control.
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| CNB2006101170128A CN100508412C (en) | 2006-10-11 | 2006-10-11 | Radio-frequency chip structure circuit of radio communication and method for transmitting-receiving radio-frequency control word |
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Effective date of registration: 20190313 Address after: 101399 Building 8-07, Ronghui Garden 6, Shunyi Airport Economic Core Area, Beijing Patentee after: Xin Xin finance leasing (Beijing) Co.,Ltd. Address before: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech park, Spreadtrum Center Building 1, Lane 2288 Patentee before: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. |
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Application publication date: 20070808 Assignee: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. Assignor: Xin Xin finance leasing (Beijing) Co.,Ltd. Contract record no.: X2021110000008 Denomination of invention: A RF chip structure circuit and RF control word transceiver method for wireless communication Granted publication date: 20090701 License type: Exclusive License Record date: 20210317 |
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Effective date of registration: 20221021 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech park, Spreadtrum Center Building 1, Lane 2288 Patentee after: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. Address before: 101399 Building 8-07, Ronghui Garden 6, Shunyi Airport Economic Core Area, Beijing Patentee before: Xin Xin finance leasing (Beijing) Co.,Ltd. |