CN111030648B - Symmetrical double-channel signal peak-to-peak value detection circuit - Google Patents
Symmetrical double-channel signal peak-to-peak value detection circuit Download PDFInfo
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- H03K5/1532—Peak detectors
Abstract
A symmetrical double-channel signal peak-to-peak detection circuit relates to the technical field of signal peak-to-peak detection in a limiting amplifier under an integrated circuit. The invention aims to solve the problem that the traditional signal peak-to-peak value detection circuit is easily influenced by a layout to generate an output error and cannot correctly compare the relation between an input signal and a threshold value. The voltage signal output by the trans-impedance amplifier is amplified by a first voltage amplifier and a second voltage amplifier and is transmitted to a first peak-to-peak value detection module, the circuit structure formed by the first voltage amplifier, the second voltage amplifier and a third voltage amplifier is completely equal to the circuit structure of a fourth voltage amplifier, a fifth voltage amplifier and a sixth voltage amplifier, two beams of signals output by the first peak-to-peak value detection module and the second peak-to-peak value detection module are compared by an overvoltage comparator to output an SD signal, and the SD signal is fed back to a period threshold value and hysteresis module, so that the SD signal is stably output. It is used to stabilize the SD signal.
Description
Technical Field
The invention relates to a signal peak-to-peak value detection circuit. Belongs to the technical field of signal peak-to-peak value detection in an integrated circuit lower amplitude Limiting Amplifier (LA).
Background
At the receiving end of an optical fiber communication integrated circuit, a transimpedance amplifier (TIA) converts a current signal of a Photodiode (PD) into a voltage signal, which is typically only a few tens of millivolts in magnitude. Therefore, an additional limiting amplifier must be installed after the transimpedance amplifier to amplify the voltage signal output from the transimpedance amplifier to a logic level. The design requirements for the limiting amplifier are high gain, low noise, and bandwidth equivalent to the data rate, so the limiting amplifier is designed as a multistage amplifier cascade structure. A signal amplitude detection module is added in the limiting amplifier and used for detecting the amplitude of an input signal of the output of the TIA (TIA), namely the Limiting Amplifier (LA), so as to judge whether the signal is normal or not. However, in the chip manufacturing process, devices have mismatch, and the judgment of the amplitude detection module is easy to generate errors, so that the whole communication system is disordered, and therefore, the influence caused by the mismatch of the devices must be overcome.
Fig. 1 shows a schematic diagram of a conventional signal peak-to-peak detection circuit. In fig. 1, the voltage amplifiers A1-A3 are the first three stages of amplifiers in the limiting amplifier, the outputs of the first two stages of amplifiers are connected to a gilbert cell (multiplier) for signal multiplication, the output value of the multiplier cannot accurately reflect the magnitude of the input signal due to mismatch of devices in the chip manufacturing process, and the magnitude of the output value is compared with the internal threshold of the comparator COMP to output an SD signal.
The voltage amplifier A1 amplifies the signal output by TIA with small amplitude, and the output value passes through the capacitors C3 and C4 (blocking direct current and alternating current), and the signal is still a small signal. The amplifier A2 amplifies the signal output by the TIA again, and the output value passes through the capacitors C1 and C2 (dc blocking and ac blocking), and the signal is a large signal. The bipolar transistors Q1, Q2, Q3, Q4, Q5 and Q6 convert input voltage signals into current signals, and multiply the current signals by the resistor R1 or R2, and the capacitor C5 filters alternating current modulation signals obtained by multiplication into direct current signals for comparison by the voltage comparator COMP.
In practical application, a highly symmetrical layout drawing method is used in a gilbert unit to reduce input and output errors caused by device mismatching, however, the multiplied and amplified input signal channel and devices in a threshold channel in a voltage comparator cannot be matched to draw a layout, so that the amplitude and the threshold of a sampled signal cannot be changed along with the change of a process at the same time, and therefore a series of problems of poor judgment accuracy and the like exist in a traditional peak-to-peak value detection circuit. The peak-to-peak value detection circuit with the structure can not meet the practical requirement of a high-performance limiting amplifier.
Disclosure of Invention
The invention aims to solve the problem that the traditional signal peak-to-peak value detection circuit is easily influenced by a layout to generate an output error and cannot correctly compare the relation between an input signal and a threshold value. Symmetrical two-channel signal peak-to-peak detection circuits are now provided.
A symmetrical two-channel signal peak-to-peak detection circuit comprises a voltage amplifier A1 in four, a voltage amplifier A2 in five and a voltage amplifier A3 in six,
the voltage signal output end of the transimpedance amplifier is connected with the voltage signal input end received by the fourth voltage amplifier A1, the voltage signal output end of the fourth voltage amplifier A1 is connected with the voltage signal input end of the fifth voltage amplifier A2, the voltage signal output end of the fifth voltage amplifier A2 is connected with the voltage signal input end of the sixth voltage amplifier A3,
the circuit also comprises a period threshold and hysteresis module 1, a first voltage amplifier 2, a second voltage amplifier 3, a third voltage amplifier 4, a first peak-to-peak value detection module 5, a second peak-to-peak value detection module 6 and a voltage comparator 7,
the inverting output terminal of the fifth voltage amplifier A2 is connected to a voltage signal input terminal of the first peak-to-peak value detection module 5,
the positive phase output end of the fifth voltage amplifier A2 is connected with the other voltage signal input end of the first peak-to-peak value detection module 5,
the output end of the threshold signal is connected with the voltage signal input end of the period threshold and hysteresis module 1, the two paths of signal output ends of the period threshold and hysteresis module 1 are respectively connected with the positive phase input end and the negative phase input end of the first voltage amplifier 2, the negative phase output end of the first voltage amplifier 2 is connected with the negative phase input end of the second voltage amplifier 3, the positive phase output end of the second voltage amplifier 3 is simultaneously connected with the positive phase input end of the third voltage amplifier 4 and one voltage signal input end of the second peak detection module 6, the negative phase output end of the second voltage amplifier 3 is simultaneously connected with the negative phase input end of the third voltage amplifier 4 and the other voltage signal input end of the second peak detection module 6,
the voltage signal output end of the first peak-to-peak value detection module 5 is connected with the positive phase input end of the voltage comparator 7;
the voltage signal output end of the second peak-to-peak value detection module 6 is connected with the inverting input end of the voltage comparator 7;
the output end of the voltage comparator 7 is connected with the period threshold and the hysteresis control end of the hysteresis module 1 and serves as a detection signal output end.
Preferably, the circuit further comprises an offset cancellation module,
an offset cancellation module is arranged between the first voltage amplifier 2 and the second voltage amplifier 3 or between the second voltage amplifier 3 and the second peak-to-peak value detection module 6.
Preferably, a low-pass filter is respectively arranged inside the first peak-to-peak value detection module 5 and the second peak-to-peak value detection module 6, and is used for filtering out high-frequency components and retaining direct-current components.
The beneficial effects of the invention are as follows:
the voltage signal output by the trans-impedance amplifier is amplified by the first voltage amplifier and the second voltage amplifier and is transmitted to the first peak-to-peak value detection module, and a low-pass filter is arranged in the circuit to filter high-frequency components and reserve direct-current components. The circuit structure formed by the first voltage amplifier, the second voltage amplifier and the third voltage amplifier is completely equal to the circuit structure of the fourth voltage amplifier, the fifth voltage amplifier and the sixth voltage amplifier, and the first peak-to-peak value detection module is completely equal to the second peak-to-peak value detection module. Two beams of signals output by the first peak-to-peak detection module and the second peak-to-peak detection module are compared by the overvoltage comparator to output SD signals, and the SD signals are fed back to the period threshold and the hysteresis module, so that threshold hysteresis is increased, continuous SD jump caused by noise and emergency is avoided, and the SD signals are stably output.
The application provides a novel input signal peak-to-peak value detection circuit, and a symmetrical double channel is formed by a voltage amplifier A1, a voltage amplifier A2, a voltage amplifier A3, a voltage amplifier II and a voltage amplifier III, so that the detection precision of input signals is improved, and the signal misjudgment is eliminated to the maximum extent.
The symmetrical double-channel signal peak-to-peak value detection circuit changes the realization method that a traditional circuit uses a Gilbert unit, adopts a threshold-adjustable double-channel signal amplification peak value comparison method, can reduce the design difficulty, is slightly influenced by process deviation, and is suitable for data transmission of high-performance LA.
Drawings
FIG. 1 is a schematic diagram of a conventional signal peak-to-peak detection circuit;
FIG. 2 is a schematic diagram of a symmetrical two channel signal peak to peak detection circuit according to a first embodiment;
FIG. 3 shows simulation results of the present application at a temperature of 27 TT; reference numeral 8 denotes a signal (referring to periodic analog signals input by RIN and RINB in fig. 1) output from the transimpedance amplifier, the figure shows 9 denotes an output from SD, M1 denotes a peak of the output signal, M2 denotes a trough of the output signal, dx is a difference between the horizontal coordinates of two points M1 and M2, and dy is a difference between the vertical coordinates of two points M1 and M2;
fig. 4 shows simulation results of the present application at a temperature of 27 degrees FF process.
Detailed Description
The first embodiment is as follows: referring to fig. 2, the symmetrical dual-channel peak-to-peak detection circuit according to this embodiment includes a voltage amplifier A1 of the fourth type, a voltage amplifier A2 of the fifth type, and a voltage amplifier A3 of the sixth type,
the voltage signal output end of the trans-impedance amplifier is connected with the voltage signal input end of a fourth voltage amplifier A1, the voltage signal output end of the fourth voltage amplifier A1 is connected with the voltage signal input end of a fifth voltage amplifier A2, the voltage signal output end of the fifth voltage amplifier A2 is connected with the voltage signal input end of a sixth voltage amplifier A3,
the circuit also comprises a period threshold value and hysteresis module 1, a first voltage amplifier 2, a second voltage amplifier 3, a third voltage amplifier 4, a first peak-to-peak value detection module 5, a second peak-to-peak value detection module 6 and a voltage comparator 7,
the inverting output terminal of the fifth voltage amplifier A2 is connected to a voltage signal input terminal of the first peak-to-peak value detection module 5,
the non-inverting output terminal of the fifth voltage amplifier A2 is connected to the other voltage signal input terminal of the first peak-to-peak value detection module 5,
the output end of the threshold signal is connected with the voltage signal input end of the period threshold and hysteresis module 1, the two signal output ends of the period threshold and hysteresis module 1 are respectively connected with the positive phase input end and the negative phase input end of the first voltage amplifier 2, the negative phase output end of the first voltage amplifier 2 is connected with the negative phase input end of the second voltage amplifier 3, the positive phase output end of the first voltage amplifier 2 is connected with the positive phase input end of the second voltage amplifier 3, the positive phase output end of the second voltage amplifier 3 is simultaneously connected with the positive phase input end of the third voltage amplifier 4 and one voltage signal input end of the second peak-to-peak value detection module 6, the negative phase output end of the second voltage amplifier 3 is simultaneously connected with the negative phase input end of the third voltage amplifier 4 and the other voltage signal input end of the second peak-to-peak value detection module 6,
the voltage signal output end of the first peak-to-peak value detection module 5 is connected with the positive phase input end of the voltage comparator 7;
the voltage signal output end of the second peak-to-peak value detection module 6 is connected with the inverting input end of the voltage comparator 7;
the output end of the voltage comparator 7 is connected with the period threshold and the hysteresis control end of the hysteresis module 1 and serves as a detection signal output end.
In this embodiment, fig. 1 shows a schematic diagram of a conventional signal peak-to-peak detection circuit, since a gilbert unit is used in the circuit to multiply output signals of two stages of amplifiers before an LA main channel, once a layout device mismatch exists between the path and a voltage comparator COMP, an output SD alarm value will have a serious deviation, so that a chip cannot normally operate. The symmetrical dual-channel signal peak-to-peak detection circuit provided in fig. 2 solves the problem that the common signal peak-to-peak detection circuit uses a gilbert cell to modulate an input signal, and the signal threshold value paths cannot be consistent and symmetrical.
The period threshold and hysteresis module 1 can generate a square wave with a period frequency of megalevel and an amplitude which can be adjusted along with the Vth signal terminal, and the period signal corresponds to the input signals of RIN and RINB terminals. The square wave signal is amplified by the first voltage amplifier 2 and the second voltage amplifier 3 and is transmitted to the second peak-to-peak value detection module 6, and a low-pass filter is arranged inside the circuit to filter high-frequency components and reserve direct-current components. The input signal of LA is amplified by A1 and A2 voltage amplifiers and transmitted to a first peak-to-peak value detection module 5, and a low-pass filter is arranged in the circuit to filter high-frequency components and reserve direct-current components. The first voltage amplifier 2, the second voltage amplifier 3 and the third voltage amplifier 4 are completely identical to the fourth voltage amplifier A1, the fifth voltage amplifier A2 and the sixth voltage amplifier A3 (the circuit structures are completely identical, and the gain and frequency characteristics are also completely identical), and the first peak-to-peak value detection module 5 is completely identical to the second peak-to-peak value detection module 6. The two beams of signals are compared by the overvoltage comparator 7 to output SD signals, and the SD signals are fed back to the period threshold and the hysteresis module 1 to change the comparison threshold of the next time, so that continuous jump of SD (signal detect signal) caused by noise and emergency is avoided. An offset cancellation module can be inserted between the amplifiers to achieve the effect of clearing the offset of the input of the operational amplifier.
The key point is that in the layout, the measurable precision of the symmetrical dual-channel signal peak-to-peak value detection circuit can be increased to the maximum extent only by highly matching the devices of the two-channel circuit.
The threshold signal is the Vth signal in FIG. 2, and Vth < 5:0 > in FIG. 2 is binary digital bits, which means that 6-bit digital signals are input to the period threshold and hysteresis module to change the amplitude of the final output analog signal.
FIG. 3 shows simulation results of the present application at a temperature of 27 TT, where the input signal amplitude is inverted at 51.25 mV.
Fig. 4 shows simulation results of the FF process at 27 degrees in temperature, where the input signal amplitude is inverted at 49.7 mV.
Therefore, under the condition of extreme process deviation, when the amplitude of the input signal reaches a certain amplitude, the inversion occurs, and the reliability of the method is proved.
The second embodiment is as follows: in this embodiment, the symmetrical dual-channel signal peak-to-peak detection circuit according to the first embodiment is further described, in this embodiment, the circuit further includes an offset cancellation module,
an offset cancellation module is arranged between the first voltage amplifier 2 and the second voltage amplifier 3 or between the second voltage amplifier 3 and the second peak-to-peak value detection module 6.
The third concrete implementation mode: in this embodiment, a low-pass filter is respectively disposed inside the first peak-to-peak detection module 5 and the second peak-to-peak detection module 6, and is used for filtering out a high-frequency component and retaining a direct-current component.
Claims (3)
1. A symmetrical two-channel signal peak-to-peak detection circuit comprises a voltage amplifier A1 in four, a voltage amplifier A2 in five and a voltage amplifier A3 in six,
the voltage signal output end of the trans-impedance amplifier is connected with the voltage signal input end received by a fourth voltage amplifier A1, the voltage signal output end of the fourth voltage amplifier A1 is connected with the voltage signal input end of a fifth voltage amplifier A2, the voltage signal output end of the fifth voltage amplifier A2 is connected with the voltage signal input end of a sixth voltage amplifier A3,
characterized in that the circuit also comprises a period threshold value and hysteresis module (1), a first voltage amplifier (2), a second voltage amplifier (3), a third voltage amplifier (4), a first peak-to-peak value detection module (5), a second peak-to-peak value detection module (6) and a voltage comparator (7),
the inverting output end of the fifth voltage amplifier A2 is connected with one voltage signal input end of the first peak-to-peak value detection module (5),
the positive phase output end of the fifth voltage amplifier A2 is connected with the other voltage signal input end of the first peak-to-peak value detection module (5),
the output end of a threshold signal is connected with the input end of a voltage signal of a period threshold and hysteresis module (1), two signal output ends of the period threshold and hysteresis module (1) are respectively connected with the positive phase input end and the negative phase input end of a first voltage amplifier (2), the negative phase output end of the first voltage amplifier (2) is connected with the negative phase input end of a second voltage amplifier (3), the positive phase output end of the first voltage amplifier (2) is connected with the positive phase input end of the second voltage amplifier (3), the positive phase output end of the second voltage amplifier (3) is simultaneously connected with the positive phase input end of a third voltage amplifier (4) and one voltage signal input end of a second peak-to-peak detection module (6), the negative phase output end of the second voltage amplifier (3) is simultaneously connected with the negative phase input end of the third voltage amplifier (4) and the other voltage signal input end of the second peak-to-peak detection module (6),
the voltage signal output end of the first peak-to-peak value detection module (5) is connected with the positive phase input end of a voltage comparator (7);
the voltage signal output end of the second peak-to-peak value detection module (6) is connected with the inverted input end of the voltage comparator (7);
the output end of the voltage comparator (7) is connected with the cycle threshold value and the hysteresis control end of the hysteresis module (1) and is used as a detection signal output end.
2. The symmetrical two-channel signal peak-to-peak detection circuit of claim 1, further comprising an offset cancellation block,
an offset elimination module is arranged between the first voltage amplifier (2) and the second voltage amplifier (3) or between the second voltage amplifier (3) and the second peak-to-peak value detection module (6).
3. The symmetrical dual-channel signal peak-to-peak detection circuit according to claim 1, wherein a low-pass filter is disposed inside each of the first peak-to-peak detection module (5) and the second peak-to-peak detection module (6) for filtering out high-frequency components and retaining direct-current components.
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