CN111030053A

CN111030053A - Protection circuit and protection method of diode-clamped three-level converter

Info

Publication number: CN111030053A
Application number: CN201911206599.3A
Authority: CN
Inventors: 骆鹏; 刘鹏越
Original assignee: Suzhou Weichuang Electrical Technology Co Ltd
Current assignee: Suzhou Weichuang Electrical Technology Co Ltd
Priority date: 2019-11-29
Filing date: 2019-11-29
Publication date: 2020-04-17

Abstract

The application relates to a protection circuit and a protection method of a diode-clamped three-level converter, wherein the protection circuit comprises: the overcurrent detection circuit is used for detecting the output current of the converter and outputting an overcurrent signal according to the output current; the desaturation fault detection circuit is used for detecting whether the insulated gate bipolar transistor in the protection circuit has desaturation faults or not, and outputting a fault signal if the desaturation faults occur; the hardware wave locking circuit is used for locking all the driving signal locking signals and outputting locking signals for locking all the driving signals according to the overcurrent signals and the fault signals; and the switch sequence management circuit is used for controlling the turn-off of each insulated gate bipolar transistor in the protection circuit according to the blocking signal and a preset turn-off sequence, and controlling the turn-on and turn-off of each insulated gate bipolar transistor according to the driving signal and the preset turn-on and turn-off sequence. According to the protection circuit, when a fault signal is detected, the switching-off requirement of the diode clamping three-level converter is met, and meanwhile the fault signal is processed in time, so that adverse effects on the converter caused by delay processing are avoided.

Description

Protection circuit and protection method of diode-clamped three-level converter

Technical Field

The application relates to the technical field of power electronics, in particular to a protection circuit and a protection method of a diode-clamped three-level converter.

Background

With the development of the diode-clamped three-level converter control technology, the application of the diode-clamped three-level converter control technology in medium-voltage frequency converter products is increasingly wide. The diode-clamped three-level converter is characterized in that four IGBTs (insulated gate bipolar transistors) are arranged on each bridge arm of the converter, the four IGBTs are connected to the midpoint of a bus capacitor through two clamping diodes, and in order to realize the three level states output by the converter, the diode-clamped three-level converter has to control the on and off of each IGBT according to a strict specified sequence. The switching logic of the IGBT is realized by software through setting a dead zone and controlling the switching sequence when the converter operates normally. However, the total time of the fault signal detection delay and the software response action delay exceeds the bearable time limit of the IGBT module, and at the moment, the IGBT module is extremely easy to damage, and the damage of the IGBT module is fatal to the converter. If all IGBT driving signals are turned off simultaneously through hardware, the requirement of the turn-off sequence of the diode clamping three-level converter is difficult to guarantee.

Disclosure of Invention

In order to solve the technical problem, the application provides a protection circuit and a protection method of a diode-clamped three-level converter.

In a first aspect, an embodiment of the present application provides a protection circuit for a diode-clamped three-level converter, where the protection circuit includes:

the overcurrent detection circuit is used for detecting the output current of the converter and outputting an overcurrent signal according to the output current;

the desaturation fault detection circuit is used for detecting whether the insulated gate bipolar transistor in the protection circuit has desaturation faults or not, and outputting a fault signal if the desaturation faults occur;

the hardware wave locking circuit is used for locking all the driving signal locking signals and outputting locking signals for locking all the driving signals according to the overcurrent signals and the fault signals;

and the switch sequence management circuit is used for controlling the turn-off of each insulated gate bipolar transistor in the protection circuit according to the blocking signal and a preset turn-off sequence, and controlling the turn-on and turn-off of each insulated gate bipolar transistor according to the driving signal and the preset turn-on and turn-off sequence.

Optionally, the over-current detection circuit includes a current detection circuit and an over-current comparison circuit;

the current detection circuit is used for detecting the output current of the converter and obtaining a current sampling signal according to the output current;

the over-current comparison circuit is used for receiving a current sampling signal output by the current detection circuit, judging whether the output current exceeds a set threshold value according to the current sampling signal, and outputting an over-current signal to the hardware wave locking circuit when the output current exceeds the set threshold value.

Optionally, the desaturation fault detection circuit includes a drive detection circuit and a desaturation fault processing circuit;

the drive detection circuit is used for detecting whether the insulated gate bipolar transistor in the protection circuit has a desaturation fault or not, and outputting a fault signal when the desaturation fault occurs in the protection circuit;

the desaturation fault processing circuit is used for carrying out fault location according to the fault signals, collecting all desaturation fault signals at the same time, and sending the collected desaturation fault signals to the hardware wave locking circuit.

Optionally, the hardware wave locking circuit includes a hardware fault summary circuit and a lockout drive circuit;

the hardware fault collecting circuit is used for collecting the over-current signal and the collected desaturation fault signal to obtain a collected fault signal, and triggering the locking drive circuit according to the collected fault signal;

the lockout drive circuit is used for generating a lockout signal for lockout of all drive signals according to the summary fault signal.

Optionally, the switch sequence management circuit includes an internal and external tube switch sequence management circuit and a driving signal interlock circuit;

the inner and outer tube switch sequence management circuit is used for enabling all insulated gate bipolar transistors to be turned off according to the blocking signal and according to a specified sequence;

the driving signal interlocking circuit is used for enabling the first insulated gate bipolar transistor and the third insulated gate bipolar transistor, and the second insulated gate bipolar transistor and the fourth insulated gate bipolar transistor not to be turned on simultaneously.

In a second aspect, the present embodiment provides a protection method for a diode-clamped three-level converter, the method including:

the overcurrent detection circuit detects the output current of the converter and outputs an overcurrent signal according to the output current;

the desaturation fault detection circuit detects whether the desaturation fault exists in the protection circuit or not, and outputs a fault signal if the desaturation fault occurs;

the hardware wave locking circuit outputs a locking signal for locking all the driving signals according to the overcurrent signal and the fault signal;

and the switch sequence management circuit controls the turn-off of each insulated gate bipolar transistor in the protection circuit according to the blocking signal and a preset turn-off sequence, and controls the turn-on and turn-off of each insulated gate bipolar transistor according to the driving signal and the preset turn-on and turn-off sequence.

Optionally, the over-current detection circuit includes a current detection circuit and an over-current comparison circuit, the over-current detection circuit detects an output current of the converter, and outputs an over-current signal according to the output current, including:

the current detection circuit detects the output current of the converter and obtains a current sampling signal according to the output current;

the over-current comparison circuit receives a current sampling signal output by the current detection circuit, judges whether the output current exceeds a set threshold value according to the current sampling signal, and outputs an over-current signal to the hardware wave locking circuit when the output current exceeds the set threshold value.

Optionally, the desaturation fault detection circuit includes a driving detection circuit and a desaturation fault processing circuit, and the desaturation fault detection circuit detects whether there is a desaturation fault in the protection circuit, and outputs a fault signal if the desaturation fault occurs, including:

the driving detection circuit detects whether a desaturation fault occurs in the protection circuit, and outputs a fault signal when the desaturation fault occurs in the protection circuit;

and the desaturation fault processing circuit carries out fault positioning according to the fault signals, collects all desaturation fault signals and sends the collected desaturation fault signals to the hardware wave locking circuit.

Optionally, the hardware wave locking circuit includes a hardware fault summary circuit and a blocking driving circuit, and the hardware wave locking circuit outputs a blocking signal for blocking all driving signals according to the overcurrent signal and the fault signal, including:

the hardware fault summary circuit summarizes the over-current signal and the converged desaturated fault signal to obtain a summary fault signal, and triggers the locking driving circuit according to the summary fault signal;

the lockout drive circuit generates a lockout signal that blocks all drive signals according to the summed fault signals.

Optionally, the switching sequence management circuit includes an internal and external tube switching sequence management circuit and a driving signal interlock circuit, and the switching sequence management circuit controls turn-off of each igbt in the protection circuit according to the blocking signal and a preset turn-off sequence, and controls turn-on and turn-off of each igbt according to the driving signal and the preset turn-on and turn-off sequence, including:

The invention has the beneficial effects that:

the invention discloses a protection circuit and a protection method of a diode-clamped three-level converter, wherein the protection circuit comprises: the overcurrent detection circuit is used for detecting the output current of the converter and outputting an overcurrent signal according to the output current; the desaturation fault detection circuit is used for detecting whether the insulated gate bipolar transistor in the protection circuit has desaturation faults or not, and outputting a fault signal if the desaturation faults occur; the hardware wave locking circuit is used for locking all the driving signal locking signals and outputting locking signals for locking all the driving signals according to the overcurrent signals and the fault signals; and the switch sequence management circuit is used for controlling the turn-off of each insulated gate bipolar transistor in the protection circuit according to the blocking signal and a preset turn-off sequence, and controlling the turn-on and turn-off of each insulated gate bipolar transistor according to the driving signal and the preset turn-on and turn-off sequence. The protection circuit can detect fault signals and process the fault signals in time, thereby avoiding the adverse effect of time delay processing on the converter and meeting the requirement of the turn-off sequence of the diode-clamped three-level converter.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

FIG. 1 is a schematic diagram of a protection circuit of a converter according to an embodiment;

FIG. 2 is a functional block diagram of an embodiment of an over-current detection circuit;

FIG. 3 is a functional block diagram of a desaturation fault detection circuit in one embodiment;

FIG. 4 is a schematic block diagram of a hardware wave-locking circuit in one embodiment;

FIG. 5 is a functional block diagram of a switching sequence management circuit in one embodiment;

FIG. 6 is a schematic diagram of a switching sequence management circuit in one embodiment;

fig. 7 is a flow chart illustrating a protection method of a converter according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 1 is a schematic structural diagram of a protection circuit of a converter in an embodiment, and in an embodiment of the present invention, referring to fig. 1, an embodiment of the present application provides a protection circuit of a diode-clamped three-level converter, where the protection circuit includes:

an overcurrent detection circuit 110 for detecting an output current of the converter and outputting an overcurrent signal according to the output current;

the desaturation fault detection circuit 120 is used for detecting whether the insulated gate bipolar transistor in the protection circuit has desaturation faults or not, and outputting fault signals if the desaturation faults occur;

the hardware wave locking circuit 130 is used for locking all the driving signal locking signals and outputting locking signals for locking all the driving signals according to the overcurrent signals and the fault signals;

and the switching sequence management circuit 140 is configured to control turn-off of each igbt in the protection circuit according to a preset turn-off sequence according to the blocking signal, and control turn-on and turn-off of each igbt according to a preset turn-on and turn-off sequence according to the driving signal.

Specifically, four IGBTs (insulated gate bipolar transistors) exist on each bridge arm of the diode-clamped three-level converter, and in order to realize that the converter outputs three level states, the diode-clamped three-level converter has to perform on-off control on 4 IGBTs in a strict sequence. Under normal conditions, each bridge arm must ensure that 1 pipe and 3 pipes are interlocked (cannot be opened simultaneously), and 2 pipes and 4 pipes are interlocked; 2, switching on the tube before 1 and switching off the tube after 1; the 3 tubes are switched on before the 4 tubes and switched off after the 4 tubes. Detecting the output current in the diode-clamped three-level converter through the overcurrent detection circuit 110, judging whether the overcurrent phenomenon occurs in the diode-clamped three-level converter, and outputting an overcurrent signal to the hardware wave locking circuit 130 when the overcurrent phenomenon is detected according to the output current; detecting whether the diode-clamped three-level converter has the desaturation fault or not by the desaturation fault detection circuit 120, and outputting a fault signal to the hardware wave locking circuit 130 if the desaturation fault occurs; outputting a blocking signal for blocking all driving signals according to the overcurrent signal and the fault signal through a hardware wave locking circuit 130; and the switching-off sequence management circuit 140 controls the turn-off of each insulated gate bipolar transistor in the protection circuit according to the blocking signal and a preset turn-off sequence, and controls the turn-on and turn-off of each insulated gate bipolar transistor according to the driving signal and the preset turn-on and turn-off sequence.

In one embodiment, fig. 2 is a schematic block diagram of an embodiment of the over-current detection circuit 110, and referring to fig. 2, the over-current detection circuit 110 includes a current detection circuit 111 and an over-current comparison circuit 112;

the current detection circuit 111 is configured to detect an output current of the converter, and obtain a current sampling signal according to the output current.

In this embodiment, the current detection circuit 111 includes a passive filter circuit, an amplifying circuit, and an active filter circuit, where the passive filter circuit performs filtering processing on an input current signal to eliminate interference of a current sampling signal; the amplifying circuit is used for per unit of the current sampling signal according to a preset proportion and then filtering through the active filter circuit, so that the stability and reliability of the output current sampling signal are guaranteed.

The over-current comparison circuit 112 is configured to receive the current sampling signal output by the current detection circuit 111, determine whether the output current exceeds a set threshold according to the current sampling signal, and output an over-current signal to the hardware latch circuit 130 when the output current exceeds the set threshold.

In this embodiment, the over-current comparison circuit 112 includes a comparator, a first voltage reference source and a second voltage reference source, the first voltage reference source represents a positive current over-current reference point, the second voltage reference source represents a negative current over-current reference point, the range of the set threshold is a range between the first voltage reference source and the second voltage reference source, the output current is compared with the first voltage reference source and the second voltage reference source according to the current sampling signal, and when the output current exceeds the set threshold, the over-current signal is output to the hardware latch circuit 130.

Specifically, the current detection circuit 111 includes a passive filter circuit, an amplification circuit, and an active filter circuit, where the passive filter circuit performs filtering processing on an input current signal to enhance the anti-interference capability of a current sampling signal; the amplifying circuit is used for per unit of the current sampling signal according to a preset proportion and then filtering through the active filter circuit, so that the stability and reliability of the output current sampling signal are guaranteed. The over-current comparison circuit 112 includes a comparator, a first voltage reference source and a second voltage reference source, the first voltage reference source represents a positive current over-current reference point, the second voltage reference source represents a negative current over-current reference point, the range of the set threshold is a range between the first voltage reference source and the second voltage reference source, the output current is compared with the first voltage reference source and the second voltage reference source according to the current sampling signal, and when the output current exceeds the set threshold, the over-current signal is output to the hardware latch circuit 130.

In one embodiment, fig. 3 is a schematic block diagram of a desaturation fault detection circuit 120 in one embodiment, and referring to fig. 3, the desaturation fault detection circuit 120 includes a driving detection circuit 121 and a desaturation fault processing circuit 122;

the driving detection circuit 121 is configured to detect whether a desaturation fault occurs in the protection circuit, and output a fault signal when the desaturation fault occurs in the protection circuit.

The desaturation fault processing circuit 122 is configured to perform fault location according to the fault signal, collect all desaturation fault signals, and send the collected desaturation fault signals to the hardware wave locking circuit 130.

In this embodiment, the desaturation fault processing circuit 122 includes a shaping circuit and a summarizing circuit, the shaping circuit processes desaturation fault signals and sends the desaturation fault signals to a main control chip of the diode-clamped three-level converter for fault location, the summarizing circuit summarizes all desaturation fault signals and triggers the hardware wave locking circuit 130, so that the hardware wave locking circuit 130 can be triggered when any IGBT has desaturation fault.

Specifically, whether a desaturation fault occurs in the protection circuit is detected according to the driving detection circuit 121, a fault signal is output when the desaturation fault occurs in the protection circuit, the fault signal is received according to the desaturation fault processing circuit 122, fault location is performed according to the fault signal, all desaturation fault signals are collected at the same time, and the collected desaturation fault signals are sent to the hardware wave locking circuit 130. The desaturation fault processing circuit 122 comprises a shaping circuit and a summarizing circuit, the shaping circuit processes desaturation fault signals and sends the desaturation fault signals to a main control chip of the diode-clamped three-level converter for fault location, the summarizing circuit summarizes all desaturation fault signals and triggers the hardware wave locking circuit 130, and the hardware wave locking circuit 130 can be triggered when any IGBT has desaturation faults.

In one embodiment, fig. 4 is a schematic block diagram of the hardware wave-locking circuit 130 in one embodiment, and referring to fig. 4, the hardware wave-locking circuit 130 includes a hardware fault summary circuit 131 and a lockout driver circuit 132;

the hardware fault summary circuit 131 is configured to summarize the over-current signal and the summarized desaturation fault signal to obtain a summary fault signal, and trigger the lockout drive circuit 132 according to the summary fault signal;

the lockout driver circuit 132 is used to generate a lockout signal that blocks all drive signals based on the summed fault signal.

Specifically, the hardware fault summary circuit 131 summarizes the over-current signal and the summarized desaturated fault signal to obtain a summary fault signal, the lockout drive circuit 132 is triggered according to the summary fault signal, so that any fault can trigger the hardware wave-locking circuit 130, and the lockout drive circuit 132 generates a lockout signal for locking all the drive signals according to the summary fault signal.

In one embodiment, fig. 5 is a schematic block diagram of a switching sequence management circuit 140 in one embodiment, and referring to fig. 4 and 5, the switching sequence management circuit 140 includes an internal/external switch sequence management circuit 141 and a driving signal interlock circuit 142;

the internal and external tube switch sequence management circuit 141 is configured to turn off all the insulated gate bipolar transistors according to a specified sequence according to the blocking signal;

the driving signal interlock circuit 142 is configured to enable the first insulated gate bipolar transistor and the third insulated gate bipolar transistor, and the second insulated gate bipolar transistor and the fourth insulated gate bipolar transistor to be turned on at the same time.

In this embodiment, fig. 6 is a schematic diagram of a switching sequence management circuit 140 in an embodiment, as shown in fig. 6, a signal 1, a signal 2, a signal 3, and a signal 4 respectively represent driving signals of a transistor 1, a transistor 2, a transistor 3, and a transistor 4 of a diode-clamped three-level inverter, the transistor 1 and the transistor 4 represent external transistors, the transistor 2 and the transistor 3 represent internal transistors, the switching sequence management circuit 140 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a first trigger U-1 a trigger a, A second Schmitt trigger U1-C, a third Schmitt trigger U1-E, a fourth Schmitt trigger U2-A, a fifth Schmitt trigger U1-B, a sixth Schmitt trigger U1-D, a seventh Schmitt trigger U1-F, an eighth Schmitt trigger U2-B, a first NAND gate U3-C, a second NAND gate U3-A, a third NAND gate U3-B and a fourth NAND gate U4-B.

The diode-clamped three-level inverter comprises a diode-clamped three-level inverter and is characterized in that a transistor 1 of the diode-clamped three-level inverter is grounded through a first resistor R1, the transistor 1 is connected with a first input end of a second NAND gate U3-A, and the transistor 1 is further connected with a first NAND gate U3-C through a second Schmitt trigger U1-C.

The diode-clamped three-level inverter comprises a diode-clamped three-level inverter, wherein a 2 tube of the diode-clamped three-level inverter is grounded through a second resistor R2, the 2 tube is connected with a first end of a sixth resistor R6, the 2 tube is further connected with a first end of a fifth resistor R5, and the 2 tube is further connected with a third input end of a fourth NAND gate U4-B through a second Schmidt trigger U1-C.

The diode-clamped three-level inverter comprises a diode-clamped three-level inverter and is characterized in that a 3 tube of the diode-clamped three-level inverter is grounded through a third resistor R3, the 3 tube is connected with a first end of a seventh resistor R7, the 3 tube is further connected with a first end of an eighth resistor R8, and the 3 tube is further connected with a second input end of a second NAND gate U3-A through a first Schmidt trigger U1-A.

And 4 tubes of the diode-clamped three-level inverter are grounded through a third resistor R4, the 4 tubes are connected with the second input end of a fourth NAND gate U4-B, and the 4 tubes are also connected with the third input end of a third NAND gate U3-B through a fifth Schmitt trigger U1-B.

The third input end of the second nand gate U3-a is connected to the second end of the fifth resistor R5, the third input end of the second nand gate U3-a is further connected to the first end of the first capacitor, the third input end of the second nand gate U3-a is further connected to the anode of the first diode D1, and the output end of the second nand gate U3-a is connected to the input end of the third schmitt trigger U1-E.

The first input end of the third NAND gate U3-B is connected with the second end of a sixth resistor R6, the first input end of the third NAND gate U3-B is further connected with the cathode of a second diode D2, the first input end of the third NAND gate U3-B is further connected with the first end of a second capacitor C2, the second input end of the third NAND gate U3-B is further connected with a 15V power supply, and the output end of the third NAND gate U3-B is connected with the input end of a seventh Schmidt trigger U1-F.

The second input end of the first NAND gate U3-C is connected with a 15V power supply, the third input end of the first NAND gate U3-C is further connected with the second end of a seventh resistor R7, the third input end of the first NAND gate U3-C is further connected with the cathode of a third diode D3, the third input end of the first NAND gate U3-C is further connected with the first end of a third capacitor C3, and the output end of the first NAND gate U3-C is connected with the input end of a fourth Schmidt trigger U2-A.

The first input end of the fourth NAND gate U4-B is connected with the second end of an eighth resistor R8, the first input end of the fourth NAND gate U4-B is connected with the anode of a fourth diode D4, the first input end of the fourth NAND gate U4-B is connected with the first end of a fourth capacitor C4, and the output end of the fourth NAND gate U4-B is connected with the input end of an eighth Schmidt trigger U2-B.

The cathode of the first diode D1 is connected to the anode of the second diode D2, and the cathode of the first diode D1 is also connected to the first end of the sixth resistor R6.

The second terminal of the first capacitor C1 is connected to the second terminal of the second capacitor C2 in common and grounded.

The anode of the third diode D3 is connected to the cathode of the fourth diode D4, and the anode of the third diode D3 is further connected to the first end of the eighth resistor R8.

The second terminal of the third capacitor C3 is connected to the second terminal of the fourth capacitor C4 in common and to ground.

The output end of the third Schmitt trigger U1-E is connected with the signal output end through a ninth resistor R9.

The output end of the seventh Schmitt trigger U1-F is connected with the signal output end through a tenth resistor R10.

And the output end of the fourth Schmitt trigger U2-A is connected with the signal output end through an eleventh resistor R11.

And the output end of the eighth Schmitt trigger U2-B is connected with the signal output end through a twelfth resistor R12.

The first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 respectively pull down the driving signals of the 1 transistor, the 2 transistor, the 3 transistor and the 4 transistor, wherein the high level of the driving signals represents that the IGBT is switched on, so that the driving signals are pulled down to ensure that the IGBT is reliably switched off when the wiring of a system is disconnected.

The internal and external tube switch sequence management circuit 141 comprises a first Schmitt trigger U1-A, a second Schmitt trigger U1-C, a third Schmitt trigger U1-E, a fourth Schmitt trigger U2-A, a fifth Schmitt trigger U1-B, a sixth Schmitt trigger U1-D, a seventh Schmitt trigger U1-F, an eighth Schmitt trigger U2-B, a first NAND gate U3-C, a second NAND gate U3-A, a third NAND gate U3-B and a fourth NAND gate U4-B. The first Schmitt trigger U1-A and the second Schmitt trigger U1-C respectively invert the driving signals of the 1 transistor and the 3 transistor and then send the inverted driving signals to the first NAND gate U3-C and the second NAND gate U3-A, at the moment, the inverted value of the driving signal of the 1 transistor and the driving signal of the 3 transistor is subjected to logical NAND operation in the second NAND gate U3-A, and the inverted value of the driving signal of the 3 transistor and the driving signal of the 1 transistor is subjected to logical NAND operation in the first NAND gate U3-C. When the driving signals of the 1 tube and the 3 tube are high level at the same time, the output is high level, the system adopts high level to represent that the IGBT is switched on, so that a third Schmitt trigger U1-E and a fourth Schmitt trigger U2-A are added to the output to perform signal inversion operation, finally, the output signal is low level, and the IGBT is switched off; when the driving signals of the 1 transistor and the 3 transistor are both low level or have the level of one high level and one low level, the circuit does not influence the level of the input signal, and therefore the interlocking function of the 1 transistor and the 3 transistor is realized. Similarly, the fifth Schmitt trigger U1-B, the sixth Schmitt trigger U1-D, the seventh Schmitt trigger U1-F, the eighth Schmitt trigger U2-B, the third NAND gate U3-B and the fourth NAND gate U4-B form an interlocking circuit of 2 transistors and 4 transistors.

The driving signal interlock circuit 142 comprises a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8, when the 1 transistor and the 2 transistor are simultaneously in a high level, the 2 transistor is fed to the third nand gate U3-B through the second diode D2 and the second capacitor C2 in a loop mode, the turn-on signal of the 2 transistor is output without delay, the 1 transistor is fed to the second nand gate U3-a through the fifth resistor R5 and the first capacitor C1 in a loop mode, the output of the 1 transistor turn-on signal must pass through one passive filtering delay of the fifth resistor R5 and the first capacitor C1, so that when the 1 transistor and the 2 transistors are simultaneously in a high level, the 2 transistor can be enabled to determine the parameters preferentially over the first capacitor R1, generally, the time delay is 1-2us, and the precision of the resistance and the capacitor is required to be ensured in order to ensure the consistency of the time delay. When the 1 transistor and the 2 transistor are at low level simultaneously, the 2 transistor is sent to the third nand gate U3-B through the sixth resistor R6 and the second capacitor C2, at this time, the original high level needs to be pulled down through the sixth resistor R6 and the second capacitor C2, and the turn-off signal of the 2 transistor needs to be sent out through a delay. The 1 transistor is sent to the second nand gate U3-a through the first diode D1 and the first capacitor C1, at this time, the high level of the first capacitor C1 is pulled down rapidly through the first diode D1, and the signal of the 1 transistor which is turned off is sent out rapidly. Therefore, when the 1 tube and the 2 tube are at low level, the 2 tube can be ensured to be switched off later than the 1 tube, the delay time is driven by the parameters of the sixth resistor R6 and the second capacitor C2, 1-2us is generally selected, and high-precision resistors and capacitors are also required to be selected to ensure the consistency of the switching-off delay. Similarly, the third diode D3, the fourth diode D4, the seventh resistor R7, the eighth resistor R8, the third capacitor C3, the fourth capacitor C4, the first nand gate U3-C and the fourth nand gate U4-B form a logic management circuit for turning on and off the 3-transistor and the 4-transistor, so that the 3-transistor can be turned on before the 4-transistor and turned off after the 4-transistor.

According to the circuit, the rapid response is guaranteed, the turn-off sequence of each IGBT is strictly guaranteed, the interlocking of a tube 1 and a tube 3 and the interlocking of a tube 2 and a tube 4 of the diode clamping three-level inverter can be strictly met under a normal mode, the tube 2 is turned on before the tube 1 and is turned off after the tube 1; the 3 tubes are firstly switched on with the 4 tubes and then switched off later than the 4 tubes.

The rear end is provided with a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12 which are connected in series to the driving signal output, the purpose is to prevent the front-stage circuit from being damaged when the signal is short-circuited to the ground, the values of the resistors are not too large, so that the input amplitude of the rear-end horizontal signal is not influenced, and 100 ohms is generally selected.

According to the method, when all driving signals are closed by triggering hardware locking waves, the switching-off sequence of the diode clamping three-level inner and outer tubes is ensured, and the switching-off of the inner and outer tubes according to the design sequence is strictly ensured while the quick response is ensured; meanwhile, the interlocking logic of the 1 tube and the 3 tubes and the 2 tube and the 4 tube can be strictly ensured under the normal wave-sending mode, the 2 tube is switched on before the 1 tube and is switched off after the 1 tube, and the 3 tube is switched on before the 4 tube and is switched off after the 4 tube. Therefore, complete IGBT switching, turn-off logic management and protection functions are provided for the system, the turn-off of each insulated gate bipolar transistor in the protection circuit is controlled according to the blocking signal and a preset turn-off sequence, the turn-on and turn-off of each insulated gate bipolar transistor are controlled according to the driving signal and the preset turn-on and turn-off sequence, and wrong turn-on and turn-off sequences caused by software defects are prevented.

In an embodiment, fig. 7 is a schematic flowchart of a protection method of a converter in an embodiment, and referring to fig. 7, an embodiment of the present application provides a protection method of a converter, where the method includes:

step S210, the over-current detection circuit 110 detects the output current of the converter and outputs an over-current signal according to the output current;

step S220, the desaturation fault detection circuit 120 detects whether there is a desaturation fault in the protection circuit, and outputs a fault signal if the desaturation fault occurs;

step S230, the hardware wave locking circuit 130 outputs a locking signal for locking all the driving signals according to the overcurrent signal and the fault signal;

in step S240, the switching sequence management circuit 140 controls turn-off of each igbt in the protection circuit according to the blocking signal and a preset turn-off sequence, and controls turn-on and turn-off of each igbt according to the driving signal and the preset turn-on and turn-off sequence. In one embodiment, the over-current detection circuit 110 includes a current detection circuit 111 and an over-current comparison circuit 112, the current detection circuit 111 detects an output current of the converter, and obtains a current sampling signal according to the output current; the over-current comparison circuit 112 receives the current sampling signal output by the current detection circuit 111, determines whether the output current exceeds a set threshold according to the current sampling signal, and outputs an over-current signal to the hardware latch circuit 130 when the output current exceeds the set threshold.

In one embodiment, the desaturation fault detection circuit 120 comprises a driving detection circuit 121 and a desaturation fault processing circuit 122, wherein the driving detection circuit 121 detects whether desaturation fault occurs in the protection circuit, and outputs a fault signal when desaturation fault occurs in the protection circuit; the desaturation fault processing circuit 122 performs fault location according to the fault signal, summarizes all the fault signals, and sends the summarized fault signals to the hardware wave locking circuit 130.

In one embodiment, the switching sequence management circuit 140 includes an internal/external switch sequence management circuit 141 and a driving signal interlock circuit 142, and the internal/external switch sequence management circuit 141 turns on or off all the igbts in a designated sequence; the driving signal interlock circuit 142 enables the first insulated gate bipolar transistor and the third insulated gate bipolar transistor, and the second insulated gate bipolar transistor and the fourth insulated gate bipolar transistor to be turned on at the same time.

In one embodiment, the hardware wave-locking circuit 130 includes a hardware fault collecting circuit 131 and a locking driving circuit 132, where the hardware fault collecting circuit 131 collects the over-current signal and the collected desaturation fault signal to obtain a collected fault signal, and triggers the locking driving circuit 132 according to the collected fault signal; the lockout drive circuit 132 generates a lockout signal that blocks all drive signals based on the summed fault signals.

The embodiment discloses a protection method of a converter, which comprises the following steps: the overcurrent detection circuit 110 detects the output current of the converter and outputs an overcurrent signal according to the output current; the desaturation fault detection circuit 120 detects whether the desaturation fault exists in the protection circuit, and outputs a fault signal if the desaturation fault occurs; the hardware wave locking circuit 130 outputs a locking signal for locking all the driving signals according to the overcurrent signal and the fault signal; the switching sequence management circuit 140 controls turn-off of each igbt in the protection circuit according to the blocking signal and a preset turn-off sequence, and controls turn-on and turn-off of each igbt according to the driving signal and the preset turn-on and turn-off sequence. According to the protection circuit, when a fault signal is detected, the switching-off requirement of the diode clamping three-level converter is met, and meanwhile the fault signal is processed in time, so that adverse effects on the converter caused by delay processing are avoided.

Fig. 7 is a flow chart illustrating a protection method of a converter according to an embodiment. It should be understood that, although the steps in the flowchart of fig. 7 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 7 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, circuit, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, circuit, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, circuit, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A protection circuit for a diode-clamped three-level converter, the protection circuit comprising:

2. The protection circuit according to claim 1, wherein the overcurrent detection circuit includes a current detection circuit and an overcurrent comparison circuit;

3. The protection circuit of claim 1, wherein the desaturation fault detection circuit comprises a drive detection circuit and a desaturation fault handling circuit;

4. The protection circuit of claim 3, wherein the hardware wave-locking circuit comprises a hardware fault summary circuit and a lockout driver circuit;

5. The protection circuit according to claim 4, wherein the switching sequence management circuit includes an inner and outer tube switching sequence management circuit and a drive signal interlock circuit;

6. A method of protecting a diode-clamped three-level converter, the method comprising:

7. The method of claim 6, wherein the over-current detection circuit comprises a current detection circuit and an over-current comparison circuit, the over-current detection circuit detects an output current of the converter, and the over-current signal is output according to the output current, and the method comprises:

8. The method of claim 6, wherein the desaturation fault detection circuit comprises a drive detection circuit and a desaturation fault processing circuit, the desaturation fault detection circuit detects whether a desaturation fault exists in the protection circuit, and outputs a fault signal if the desaturation fault occurs, and the method comprises:

9. The method of claim 8, wherein the hardware wave-locking circuit comprises a hardware fault summary circuit and a lockout driver circuit, and wherein the hardware wave-locking circuit outputs a lockout signal that locks out all driver signals based on the over-current signal and the fault signal, comprising:

10. The method of claim 9, wherein the switching sequence management circuit comprises an inner and outer tube switching sequence management circuit and a driving signal interlock circuit, the switching sequence management circuit controls turn-off of each igbt in the protection circuit according to the blocking signal in a preset turn-off sequence, and controls turn-on and turn-off of each igbt according to the driving signal in a preset turn-on and turn-off sequence, and the method comprises: