CN111029424A - Silicon-based double-diode double-sided solar cell and preparation method thereof - Google Patents
Silicon-based double-diode double-sided solar cell and preparation method thereof Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 109
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 109
- 239000010703 silicon Substances 0.000 title claims abstract description 109
- 238000002360 preparation method Methods 0.000 title claims description 29
- 239000010409 thin film Substances 0.000 claims abstract description 147
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims abstract description 90
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 238000006243 chemical reaction Methods 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 18
- 230000005641 tunneling Effects 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims description 60
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 40
- 239000010408 film Substances 0.000 claims description 31
- 230000008021 deposition Effects 0.000 claims description 29
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 25
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 21
- 239000000243 solution Substances 0.000 claims description 21
- 238000009792 diffusion process Methods 0.000 claims description 20
- 239000007789 gas Substances 0.000 claims description 18
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 15
- 239000005388 borosilicate glass Substances 0.000 claims description 15
- 238000004140 cleaning Methods 0.000 claims description 15
- 239000005360 phosphosilicate glass Substances 0.000 claims description 15
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 10
- 229910052681 coesite Inorganic materials 0.000 claims description 10
- 229910052906 cristobalite Inorganic materials 0.000 claims description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 229910052682 stishovite Inorganic materials 0.000 claims description 10
- 229910052905 tridymite Inorganic materials 0.000 claims description 10
- 239000003513 alkali Substances 0.000 claims description 9
- 238000002310 reflectometry Methods 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 239000002253 acid Substances 0.000 claims description 5
- 239000000654 additive Substances 0.000 claims description 5
- 230000000996 additive effect Effects 0.000 claims description 5
- 230000007797 corrosion Effects 0.000 claims description 5
- 238000005260 corrosion Methods 0.000 claims description 5
- 239000012895 dilution Substances 0.000 claims description 5
- 238000010790 dilution Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 239000012530 fluid Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 5
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 230000035484 reaction time Effects 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 238000004528 spin coating Methods 0.000 claims description 5
- 238000005507 spraying Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 238000007650 screen-printing Methods 0.000 claims description 4
- 230000008020 evaporation Effects 0.000 claims description 2
- 238000001704 evaporation Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
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Abstract
The invention relates to a silicon-based double-diode double-sided solar cell which comprises a bottom cell, a tunnel junction and a top cell, wherein the bottom cell comprises an N-type silicon substrate, and a tunneling oxide layer and a phosphorus-doped N-type silicon substrate which are sequentially prepared on the back surface of the N-type silicon substrate+-a poly-Si thin film layer and a lower transparent conductive thin film layer, P prepared on the front surface of the N-type silicon substrate+A doped layer, the tunnel junction being formed at P+P on the doped layer++Microcrystalline silicon thin film layer and N++A microcrystalline silicon thin film layer, the top cell comprising sequentially preparing P++N on microcrystalline silicon thin film layer++The silicon-based double-sided solar cell comprises a microcrystalline silicon thin film layer, an intrinsic microcrystalline silicon thin film layer, a P-type microcrystalline silicon thin film layer and an upper transparent conductive thin film layer, wherein a bottom cell and a top cell are connected in series through a tunnel junction, the upper transparent conductive thin film layer and the lower transparent conductive thin film layer are respectively connected with an upper electrode and a lower electrode, and the silicon-based double-diode double-sided solar cell is high in photoelectric conversion efficiency, mature in process and high in industrialization degree.
Description
Technical Field
The invention relates to a solar cell, in particular to a silicon-based double-diode double-sided solar cell and a preparation method thereof.
Background
At present, a silicon-based solar cell is a mainstream product in the photovoltaic industry, and with the continuous development and innovation of the solar cell technology, the conversion efficiency of the silicon-based single-diode solar cell is close to the theoretical limit of Shockley-Queisser photovoltaic conversion efficiency; in order to meet the development trend of continuously reducing cost and improving efficiency in the photovoltaic industry and realize the goal of low-price internet access in the early days, a solar cell with a novel structure needs to be developed and designed. The solar cell with the double-diode structure can not be limited by theoretical limit of Shockley-Queisser conversion efficiency. The double-diode structure solar cell consists of two single-diode solar cells and is divided into a top cell and a bottom cell; the top and bottom cells have two materials with different forbidden band widths, which can absorb the sunlight of different wave bands, greatly improving the light utilization rate, and the conversion efficiency can reach 45 percent at most. The double-diode solar cell can be designed into various types and structures, various double-diode single-sided solar cells are mainly designed by taking gallium arsenide, CIGS or perovskite as a substrate in the industry at present, but the double-diode single-sided solar cell has the characteristics of complex process steps, immature and unstable technology, small process window, high manufacturing cost, low light utilization rate of only one side receiving surface and the like, and industrialization is difficult to realize.
Disclosure of Invention
The applicant carries out research and improvement aiming at the defects and provides a silicon-based double-diode double-sided solar cell and a preparation method thereof.
The technical scheme adopted by the invention is as follows:
a silicon-based double-diode double-sided solar cell comprises a bottom cell, a tunnel junction and a top cell, wherein the bottom cell comprises an N-type silicon substrate, and a tunneling oxide layer and a phosphorus-doped N-type silicon substrate which are sequentially prepared on the back of the N-type silicon substrate+-a poly-Si thin film layer and a lower transparent conductive thin film layer, said N-type silicon substrate front sidePreparation of P+A doped layer, the tunnel junction being formed at P+P on the doped layer++Microcrystalline silicon thin film layer and N++A microcrystalline silicon thin film layer, the top cell comprising sequentially preparing P++N on microcrystalline silicon thin film layer++The solar cell comprises a microcrystalline silicon thin film layer, an intrinsic microcrystalline silicon thin film layer, a P-type microcrystalline silicon thin film layer and an upper transparent conductive thin film layer, wherein the bottom cell and the top cell are connected in series through a tunnel junction, and the upper transparent conductive thin film layer and the lower transparent conductive thin film layer are respectively connected with an upper electrode and a lower electrode.
As a further improvement of the above technical solution:
the tunneling oxide layer is an SiO2 layer, and the thickness range of the SiO2 layer is 2-5 nm.
Said N is+The thickness of the-poly-Si thin film layer is in the range of 50-80 nm.
The P is++The thickness range of the microcrystalline silicon thin film layer is 30-80 nm.
Said N is++The thickness range of the microcrystalline silicon thin film layer is 50-100 nm.
The thickness range of the intrinsic microcrystalline silicon thin film layer is 300-500 nm.
The thickness range of the P-type microcrystalline silicon thin film layer is 60-120 nm.
A preparation method of a silicon-based double-diode double-sided solar cell comprises the following steps:
1) surface cleaning and texturing: cleaning and damaging the surface of the N-type silicon substrate by using a low-concentration alkali solution, and corroding the surface of the N-type silicon substrate to form a pyramid-shaped surface appearance;
2) front boron diffusion: adopting any one of thermal diffusion mode or spin coating and spray coating mode to carry out boron diffusion on the N-type silicon substrate to prepare P+The doping layer is matched with the N-type silicon substrate to form a PN junction;
3) back wet etching: the N type silicon substrate openly adopts the water film protection, and N type silicon substrate back floats in chemical corrosion solution, utilizes HF acidizing fluid to corrode diffusion back N type silicon substrate lower surface and edge, gets rid of the P type silicon at N type silicon substrate back edge for the upper and lower surface of N type silicon substrate is insulating each other, uses KOH and polishing additive to carry out polishing treatment, back reflectivity to the silicon chip back: 40-45%;
4) back deposition of SiOx: preparing a tunneling oxide layer by using LPCVD;
5) back deposition of Poly-Si: preparation of phosphorus-doped N Using LPCVD+-a poly-Si thin film layer, prepared with PH3, SiH 4;
6) borosilicate glass (BSG)/phosphosilicate glass (PSG): under the condition of room temperature, etching the upper surface of the N-type silicon substrate by using 49% HF acid solution to remove BSG and PSG on the upper surface of the silicon wafer;
7) preparation of P from the front++A microcrystalline silicon thin film layer: using Plasma Enhanced Chemical Vapor Deposition (PECVD) on P+Preparation of P on the doped layer++A microcrystalline silicon thin film layer, wherein the reaction gases are B (CH3)3, SiH4 and H2, the deposition temperature is 160-260 ℃, and the ratio (hydrogen dilution ratio) R of H2/SiH4 is 20-35;
8) preparation of N from the front++A microcrystalline silicon thin film layer: using Plasma Enhanced Chemical Vapor Deposition (PECVD) on P++Preparation of N on microcrystalline silicon thin film layer++The microcrystalline silicon thin film layer is prepared by reacting PH3, SiH4 and H2 gases at a deposition temperature of 200-250 ℃, wherein R is 20-35;
9) depositing an intrinsic amorphous silicon film: using Plasma Enhanced Chemical Vapor Deposition (PECVD) on N++Depositing and preparing an intrinsic amorphous silicon thin film layer on the microcrystalline silicon thin film layer, wherein the reaction gases are SiH4 and H2, R is 15-20, and the deposition temperature is 180-200 ℃;
10) depositing a P-type microcrystalline silicon thin film layer: depositing and preparing front surface doped P on the intrinsic amorphous silicon thin film by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method+The microcrystalline silicon film comprises a reaction gas of B (CH3)3, SiH4 and H2, and is deposited at the temperature of 200-250 ℃, wherein R is 20-35;
11) depositing a transparent conductive film; respectively in the doping of phosphorus N+Depositing a lower transparent conductive thin film layer and an upper transparent conductive thin film layer on the lower side of the poly-Si thin film layer and the upper side of the P-type microcrystalline silicon thin film layer respectively;
12) preparing an electrode: the upper electrode and the lower electrode are respectively connected with the upper transparent conductive thin film layer and the lower transparent conductive thin film layer through a screen printing mode or an evaporation plating mode.
As a further improvement of the above technical solution:
the low-concentration alkaline solution for surface cleaning and texturing is 1.0-1.5 wt% NaOH, and the reaction time is as follows: 350s, temperature: 85 ℃, reflectance: 11 to 12 percent.
The P is+The doped layer has a sheet resistance in the range of 115-125 Ω/□.
The invention has the following beneficial effects:
1) the N-type crystal silicon-based single diode solar cell is used as a bottom cell, and has the characteristics of wide raw material source, simple process steps, low manufacturing cost and the like; the top cell adopts an amorphous silicon thin film cell, an amorphous silicon thin film can be deposited in a large scale and a large area, the process is simple and mature, the film forming area is matched with the size of the crystalline silicon, and the integration level of the amorphous silicon thin film and the crystalline silicon is high; and the amorphous silicon thin film battery is manufactured under the low temperature condition (less than 300 ℃) in the whole manufacturing process, so that the bottom battery is not damaged, and the quality of the bottom battery is ensured.
2) The bottom battery is formed by combining an N-type crystal silicon substrate with a tunneling oxide layer passivation contact technology, the N-type crystal silicon battery has the advantages of reduced light attenuation, good metal impurity pollution resistance, mature process technology, high photoelectric conversion efficiency, high commercialization degree and the like, the combination of the tunneling oxide layer passivation contact technology can provide good back surface passivation, the ultrathin oxide layer can enable multi-electron tunneling to enter a polycrystalline silicon layer and prevent minority hole recombination, and then electrons are transversely transmitted in the polycrystalline silicon layer and collected by metal, so that metal contact recombination current is greatly reduced, and open-circuit voltage and short-circuit current of the battery are improved.
3) The amorphous silicon thin film battery is used as a top battery, a large-area deposited film can be matched with a commercial crystalline silicon solar battery, the process steps are simple, the deposition temperature is low, the manufacturing cost is low, and the forbidden bandwidth of the material of the amorphous silicon thin film can be changed by doping, so that the matching width of the forbidden bandwidth of the material of the bottom battery is high;
4) the top battery and the bottom battery are connected in series, an intermediate electrode does not need to be additionally manufactured, the process steps are simple, the integration level is high, and the assembly packaging at the later stage is convenient;
5) the whole solar cell is designed to be double-sided and can absorb sunlight, the light utilization rate is improved, the photoelectric conversion efficiency of the whole double-diode solar cell is further improved, and the short-circuit current of the whole cell is improved.
Drawings
Fig. 1 is a schematic structural diagram of a silicon-based double-diode double-sided solar cell provided by the invention.
Fig. 2 is a circuit diagram of a silicon-based double-diode double-sided solar cell provided by the invention.
In the figure: 1. an N-type silicon substrate; 2. tunneling through the oxide layer; 3. n is a radical of+-a poly-Si thin film layer; 4. a lower transparent conductive thin film layer; 5. p+Doping layer; 6. p++A microcrystalline silicon thin film layer; 7. n is a radical of++A microcrystalline silicon thin film layer; 8. an intrinsic microcrystalline silicon thin film layer; 9. a P-type microcrystalline silicon thin film layer; 10. an upper transparent conductive thin film layer; 11. an upper electrode; 12. and a lower electrode.
Detailed Description
Example one
The following describes a specific embodiment of the present embodiment with reference to the drawings.
As shown in fig. 1 and fig. 2, the silicon-based double-diode bifacial solar cell of the present embodiment includes a bottom cell, a tunnel junction and a top cell, the bottom cell includes an N-type silicon substrate 1, the tunnel junction comprises a P + + microcrystalline silicon thin film layer 6 and an N + + microcrystalline silicon thin film layer 7 which are prepared on the P + doping layer 5, the top cell comprises the N + + microcrystalline silicon thin film layer 7, an intrinsic microcrystalline silicon thin film layer 8, a P type microcrystalline silicon thin film layer 9 and an upper transparent conductive thin film layer 10 which are prepared on the P + + microcrystalline silicon thin film layer 6 in sequence, the bottom cell and the top cell are connected in series through the tunnel junction, and the upper transparent conductive thin film layer 10 and the lower transparent conductive thin film layer 4 are respectively connected with an upper electrode 11 and a lower electrode 12.
The preparation method of the silicon-based double-diode double-sided solar cell comprises the following steps:
1) surface cleaning and texturing: cleaning and damaging the surface of the N-type silicon substrate 1 by using low-concentration alkali solution, and corroding the surface of the N-type silicon substrate 1 to form a pyramid-shaped surface morphology for surface cleaning and texturing, wherein the low-concentration alkali solution is prepared by the following steps: 1.0-1.5 wt% NaOH, reaction time: 350s, temperature: 85 ℃, reflectance: 11 to 12 percent;
2) front boron diffusion: adopting any one of a thermal diffusion mode or a spin coating and spraying mode to carry out boron diffusion on the N-type silicon substrate 1 to prepare P+The doped layer 5 cooperates with the N-type silicon substrate to form a PN junction, P+The sheet resistance range of the doping layer 5 is 115-125 omega/□;
3) back wet etching: n type silicon substrate 1 openly adopts the water film protection, and 1 back of N type silicon substrate floats in chemical corrosion solution, utilizes HF acidizing fluid to corrode 1 lower surface of N type silicon substrate and edge after the diffusion, gets rid of the P type silicon at 1 lower surface edge of N type silicon substrate for the upper and lower surface of N type silicon substrate 1 is insulated each other, uses KOH and polishing additive to carry out polishing treatment, back reflectivity to the silicon chip back: 40-45%;
4) back deposition of SiOx: preparing a SiO2 layer as a tunneling oxide layer 2 by LPCVD, wherein the thickness of the SiO2 layer is 2 nm;
5) back deposition of Poly-Si: preparation of phosphorus-doped N Using LPCVD+A film 3 of poly-Si prepared with PH3, SiH4, said N+The thickness of the poly-Si thin film layer 3 is 50 nm;
6) borosilicate glass (BSG)/phosphosilicate glass (PSG): under the condition of room temperature, etching the upper surface of the N-type silicon substrate 1 by using 49% HF acid solution, and removing BSG and PSG on the upper surface of the N-type silicon substrate 1;
7) preparation of P from the front++A microcrystalline silicon thin film layer: using Plasma Enhanced Chemical Vapor Deposition (PECVD) on P+Preparation of P on the doped layer 5++The microcrystalline silicon thin film layer 6 contains B (CH3)3, SiH4 and H2 as reaction gases, the deposition temperature is 160-260 ℃, the ratio (hydrogen dilution ratio) R of H2/SiH4 is 20-35, and P++The thickness of the microcrystalline silicon thin film layer 6 is 30 nm;
8) preparation of N from the front++A microcrystalline silicon thin film layer: using Plasma Enhanced Chemical Vapor Deposition (PECVD) on P++Preparing N on the microcrystalline silicon thin film layer 6++A microcrystalline silicon thin film layer 7 with a reaction gas of PH3 and SiH4 and H2 gas, the deposition temperature is 200-250 ℃, wherein R is 20-35, and N is++The thickness of the microcrystalline silicon thin film layer 7 is 50 nm;
9) depositing an intrinsic amorphous silicon film: using Plasma Enhanced Chemical Vapor Deposition (PECVD) on N++Depositing and preparing an intrinsic amorphous silicon thin film 8 on the microcrystalline silicon thin film layer 7, wherein the reaction gases are SiH4 and H2, R is 15-20, the deposition temperature is 180-;
10) depositing a P-type microcrystalline silicon thin film layer: depositing and preparing front surface doped P on the intrinsic amorphous silicon thin film 8 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method+The microcrystalline silicon film 9 is formed by depositing B (CH3)3, SiH4 and H2 gases at 200-250 ℃, wherein R is 20-35 and P is+The thickness of the microcrystalline silicon film 9 is 60 nm;
11) depositing a transparent conductive film; respectively in the doping of phosphorus N+A lower transparent conductive thin film layer 4 and an upper transparent conductive thin film layer 10 are respectively deposited on the lower side of the poly-Si thin film layer 3 and the upper side of the P-type microcrystalline silicon thin film layer 9;
12) preparing an electrode: the upper electrode 11 and the lower electrode 12 are respectively connected to the upper transparent conductive thin film layer 10 and the lower transparent conductive thin film layer 4 by a screen printing method.
Example two
The preparation method of the silicon-based double-diode double-sided solar cell comprises the following steps:
1) surface cleaning and texturing: cleaning and damaging the surface of the N-type silicon substrate 1 by using low-concentration alkali solution, and corroding the surface of the N-type silicon substrate 1 to form a pyramid-shaped surface morphology for surface cleaning and texturing, wherein the low-concentration alkali solution is prepared by the following steps: 1.0-1.5 wt% NaOH, reaction time: 350s, temperature: 85 ℃, reflectance: 11 to 12 percent;
3) front boron diffusion: adopting any one of a thermal diffusion mode or a spin coating and spraying mode to carry out boron diffusion on the N-type silicon substrate 1 to prepare P+The doped layer 5 cooperates with the N-type silicon substrate to form a PN junction, P+The sheet resistance range of the doping layer 5 is 115-125 omega/□;
3) back wet etching: n type silicon substrate 1 openly adopts the water film protection, and 1 back of N type silicon substrate floats in chemical corrosion solution, utilizes HF acidizing fluid to corrode 1 lower surface of N type silicon substrate and edge after the diffusion, gets rid of the P type silicon at 1 lower surface edge of N type silicon substrate for the upper and lower surface of N type silicon substrate 1 is insulated each other, uses KOH and polishing additive to carry out polishing treatment, back reflectivity to the silicon chip back: 40-45%;
4) back deposition of SiOx: preparing a SiO2 layer as a tunneling oxide layer 2 by LPCVD, wherein the thickness of the SiO2 layer is 5 nm;
5) back deposition of Poly-Si: preparation of phosphorus-doped N Using LPCVD+A film 3 of poly-Si prepared with PH3, SiH4, said N+The thickness of the poly-Si thin film layer 3 is 80 nm;
6) borosilicate glass (BSG)/phosphosilicate glass (PSG): under the condition of room temperature, etching the upper surface of the N-type silicon substrate 1 by using 49% HF acid solution, and removing BSG and PSG on the upper surface of the N-type silicon substrate 1;
7) preparation of P from the front++A microcrystalline silicon thin film layer: using Plasma Enhanced Chemical Vapor Deposition (PECVD) on P+Preparation of P on the doped layer 5++The microcrystalline silicon thin film layer 6 contains B (CH3)3, SiH4 and H2 as reaction gases, the deposition temperature is 160-260 ℃, the ratio (hydrogen dilution ratio) R of H2/SiH4 is 20-35, and P++The thickness of the microcrystalline silicon thin film layer is 80 nm;
8) preparation of N from the front++A microcrystalline silicon thin film layer: using Plasma Enhanced Chemical Vapor Deposition (PECVD) on P++Preparing N on the microcrystalline silicon thin film layer 6++The microcrystalline silicon thin film layer 7 is formed by depositing PH3, SiH4 and H2 gases at a deposition temperature of 200-250 ℃, wherein R is 20-35 and N is++The thickness of the microcrystalline silicon thin film layer is 100 nm;
9) depositing an intrinsic amorphous silicon film: using Plasma Enhanced Chemical Vapor Deposition (PECVD) on N++Depositing and preparing an intrinsic amorphous silicon thin film 8 on the microcrystalline silicon thin film layer 7, wherein the reaction gases are SiH4 and H2, R is 15-20, the deposition temperature is 180-;
10) depositing a P-type microcrystalline silicon thin film layer: depositing and preparing front surface doped P on the intrinsic amorphous silicon thin film 8 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method+ Microcrystalline silicon film 9, reaction gasThe deposition temperature is 200-250 ℃ and the deposition temperature is B (CH3)3, SiH4 and H2, wherein R is 20-35, and P is+The thickness of the microcrystalline silicon film 9 is 120 nm;
11) depositing a transparent conductive film; respectively in the doping of phosphorus N+A lower transparent conductive thin film layer 4 and an upper transparent conductive thin film layer 10 are respectively deposited on the lower side of the poly-Si thin film layer 3 and the upper side of the P-type microcrystalline silicon thin film layer 9;
12) preparing an electrode: the upper electrode 11 and the lower electrode 12 are connected to the upper transparent conductive thin film layer 10 and the lower transparent conductive thin film layer 4, respectively, by vapor deposition.
EXAMPLE III
The preparation method of the silicon-based double-diode double-sided solar cell comprises the following steps:
1) surface cleaning and texturing: cleaning and damaging the surface of the N-type silicon substrate 1 by using low-concentration alkali solution, and corroding the surface of the N-type silicon substrate 1 to form a pyramid-shaped surface morphology for surface cleaning and texturing, wherein the low-concentration alkali solution is prepared by the following steps: 1.0-1.5 wt% NaOH, reaction time: 350s, temperature: 85 ℃, reflectance: 11 to 12 percent;
3) front boron diffusion: adopting any one of a thermal diffusion mode or a spin coating and spraying mode to carry out boron diffusion on the N-type silicon substrate 1 to prepare P+The doped layer 5 cooperates with the N-type silicon substrate to form a PN junction, P+The sheet resistance range of the doping layer 5 is 115-125 omega/□;
3) back wet etching: n type silicon substrate 1 openly adopts the water film protection, and 1 back of N type silicon substrate floats in chemical corrosion solution, utilizes HF acidizing fluid to corrode 1 lower surface of N type silicon substrate and edge after the diffusion, gets rid of the P type silicon at 1 lower surface edge of N type silicon substrate for the upper and lower surface of N type silicon substrate 1 is insulated each other, uses KOH and polishing additive to carry out polishing treatment, back reflectivity to the silicon chip back: 40-45%;
4) back deposition of SiOx: preparing a SiO2 layer as a tunneling oxide layer 2 by LPCVD, wherein the thickness of the SiO2 layer is 3 nm;
5) back deposition of Poly-Si: preparation of phosphorus-doped N Using LPCVD+A film 3 of poly-Si prepared with PH3, SiH4, said N+The thickness of the-poly-Si thin film layer 3 is65nm；
6) Borosilicate glass (BSG)/phosphosilicate glass (PSG): under the condition of room temperature, etching the upper surface of the N-type silicon substrate 1 by using 49% HF acid solution to remove BSG and PSG on the upper surface of the silicon wafer;
7) preparation of P from the front++A microcrystalline silicon thin film layer: using Plasma Enhanced Chemical Vapor Deposition (PECVD) on P+Preparation of P on the doped layer 5++The microcrystalline silicon thin film layer 6 contains B (CH3)3, SiH4 and H2 as reaction gases, the deposition temperature is 160-260 ℃, the ratio (hydrogen dilution ratio) R of H2/SiH4 is 20-35, and P++The thickness of the microcrystalline silicon thin film layer 6 is 55 nm;
8) preparation of N from the front++A microcrystalline silicon thin film layer: using Plasma Enhanced Chemical Vapor Deposition (PECVD) on P++Preparing N on the microcrystalline silicon thin film layer 6++The microcrystalline silicon thin film layer 7 is formed by depositing PH3, SiH4 and H2 gases at a deposition temperature of 200-250 ℃, wherein R is 20-35 and N is++The thickness of the microcrystalline silicon thin film layer 7 is 75 nm;
9) depositing an intrinsic amorphous silicon film: using Plasma Enhanced Chemical Vapor Deposition (PECVD) on N++Depositing and preparing an intrinsic amorphous silicon thin film 8 on the microcrystalline silicon thin film layer 7, wherein the reaction gases are SiH4 and H2, R is 15-20, the deposition temperature is 180-;
10) depositing a P-type microcrystalline silicon thin film layer: depositing and preparing front surface doped P on the intrinsic amorphous silicon thin film 8 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method+The microcrystalline silicon film 9 is formed by depositing B (CH3)3, SiH4 and H2 gases at 200-250 ℃, wherein R is 20-35 and P is+The thickness of the microcrystalline silicon film 9 is 90 nm;
11) depositing a transparent conductive film; respectively in the doping of phosphorus N+A lower transparent conductive thin film layer 4 and an upper transparent conductive thin film layer 10 are respectively deposited on the lower side of the poly-Si thin film layer 3 and the upper side of the P-type microcrystalline silicon thin film layer 9;
12) preparing an electrode: the upper electrode 11 and the lower electrode 12 are respectively connected to the upper transparent conductive thin film layer 10 and the lower transparent conductive thin film layer 4 by a screen printing method.
The foregoing description is illustrative of the present invention and is not to be construed as limiting thereof, the scope of the invention being defined by the appended claims, which may be modified in any manner without departing from the basic structure thereof.
Claims (10)
1. A silicon-based double-diode double-sided solar cell is characterized in that: the solar cell comprises a bottom cell, a tunnel junction and a top cell, wherein the bottom cell comprises an N-type silicon substrate (1), and a tunneling oxide layer (2) and a phosphorus-doped N-type silicon substrate (1) which are sequentially prepared on the back surface of the N-type silicon substrate (1)+-a poly-Si thin film layer (3) and a lower transparent conductive thin film layer (4), P prepared on the front side of the N-type silicon substrate (1)+A doped layer (5), said tunnel junction comprising a doped layer prepared at P+P on the doped layer (5)++Microcrystalline silicon thin film layer (6) and N++A microcrystalline silicon thin film layer (7), said top cell comprising sequentially prepared P++N on the microcrystalline silicon thin film layer (6)++The solar cell comprises a microcrystalline silicon thin film layer (7), an intrinsic microcrystalline silicon thin film layer (8), a P-type microcrystalline silicon thin film layer (9) and an upper transparent conductive thin film layer (10), wherein the bottom cell and the top cell are connected in series through a tunnel junction, and the upper transparent conductive thin film layer (10) and the lower transparent conductive thin film layer (4) are respectively connected with an upper electrode (11) and a lower electrode (12).
2. The silicon-based two-diode bifacial solar cell of claim 1, wherein: the tunneling oxide layer (2) is a SiO2 layer, and the thickness range of the SiO2 layer is 2-5 nm.
3. The silicon-based two-diode bifacial solar cell of claim 1, wherein: said N is+The thickness of the poly-Si thin film layer (3) is in the range of 50-80 nm.
4. The silicon-based two-diode bifacial solar cell of claim 1, wherein: the P is++The thickness range of the microcrystalline silicon thin film layer (6) is 30-80 nm.
5. The silicon-based two-diode bifacial solar cell of claim 1, wherein: said N is++Microcrystalline silicon thin film layer (7)) The thickness of (a) is in the range of 50-100 nm.
6. The silicon-based two-diode bifacial solar cell of claim 1, wherein: the thickness range of the intrinsic microcrystalline silicon thin film layer (8) is 300-500 nm.
7. The silicon-based two-diode bifacial solar cell of claim 1, wherein: the thickness range of the P-type microcrystalline silicon thin film layer (9) is 60-120 nm.
8. The method for preparing a silicon-based double-diode bifacial solar cell as claimed in claim 1, comprising the steps of:
1) surface cleaning and texturing: cleaning and damaging the surface of the N-type silicon substrate (1) by using low-concentration alkali solution, and corroding the surface of the N-type silicon substrate (1) to form a pyramid-shaped surface appearance;
2) front boron diffusion: carrying out boron diffusion on the N-type silicon substrate (1) by adopting any one of a thermal diffusion mode or a spin coating and spraying mode to prepare P+The doping layer (5) is matched with the N-type silicon substrate (1) to form a PN junction;
3) back wet etching: n type silicon substrate (1) openly adopts the water film protection, and N type silicon substrate (1) back floats in chemical corrosion solution, utilizes HF acidizing fluid to corrode N type silicon substrate (1) lower surface and edge after the diffusion, gets rid of the P type silicon at N type silicon substrate (1) back edge for the upper and lower surface of N type silicon substrate (1) is insulating each other, uses KOH and polishing additive to carry out polishing treatment, back reflectivity to the silicon chip back: 40-45%;
4) back deposition of SiOx: preparing a tunneling oxide layer by using LPCVD;
5) back deposition of Poly-Si: preparation of phosphorus-doped N Using LPCVD+-a poly-Si thin film layer, prepared with PH3, SiH 4;
6) borosilicate glass (BSG)/phosphosilicate glass (PSG): under the condition of room temperature, etching the upper surface of the N-type silicon substrate (1) by using 49% HF acid solution to remove BSG and PSG on the upper surface of the silicon wafer;
7) preparation of P from the front++Microcrystalline silicon thin filmLayer (b): using Plasma Enhanced Chemical Vapor Deposition (PECVD) on P+Preparation of P on the doped layer (5)++A microcrystalline silicon thin film layer (6) with reaction gases of B (CH3)3, SiH4 and H2, the deposition temperature is 160-260 ℃, and the ratio (hydrogen dilution ratio) R of H2/SiH4 is 20-35;
8) preparation of N from the front++A microcrystalline silicon thin film layer: using Plasma Enhanced Chemical Vapor Deposition (PECVD) on P++Preparing N on the microcrystalline silicon film layer (6)++The microcrystalline silicon thin film layer (7) is prepared by reacting PH3, SiH4 and H2 gases at a deposition temperature of 200-250 ℃, wherein R is 20-35;
9) depositing an intrinsic amorphous silicon film: using Plasma Enhanced Chemical Vapor Deposition (PECVD) on N++Depositing and preparing an intrinsic amorphous silicon thin film layer (8) on the microcrystalline silicon thin film layer (7), wherein the reaction gases are SiH4 and H2, R is 15-20, and the deposition temperature is 180-;
10) depositing a P-type microcrystalline silicon thin film layer: depositing and preparing front surface doped P on the intrinsic amorphous silicon thin film (8) by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method+The microcrystalline silicon film (9) is prepared by reacting B (CH3)3, SiH4 and H2 gases at a deposition temperature of 200-250 ℃, wherein R is 20-35;
11) depositing a transparent conductive film; respectively in the doping of phosphorus N+-depositing a lower transparent conductive thin film layer (4) and an upper transparent conductive thin film layer (10) on the lower side of the poly-Si thin film layer (3) and the upper side of the P-type microcrystalline silicon thin film layer (9), respectively;
12) preparing an electrode: the upper electrode (11) and the lower electrode (12) are respectively connected with the upper transparent conductive film layer (10) and the lower transparent conductive film layer (4) through a screen printing mode or an evaporation mode.
9. The method of claim 7, wherein the silicon-based double-diode bifacial solar cell comprises: the low-concentration alkali solution for surface cleaning and texturing is 1.0-1.5 wt% NaOH, the reaction time is 350s, the temperature is 85 ℃, and the reflectivity is as follows: 11 to 12 percent.
10. The method of claim 7, wherein the silicon-based double-diode bifacial solar cell comprises: the P is+Of the doped layer (5)The sheet resistance ranges from 115 to 125 Ω/□.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101777593A (en) * | 2010-01-20 | 2010-07-14 | 景德镇陶瓷学院 | Non-crystalline/micro-crystalline silicon laminated solar battery with middle layer doping structure and manufacture method thereof |
| CN102738291A (en) * | 2012-07-07 | 2012-10-17 | 蚌埠玻璃工业设计研究院 | Silicon-based heterojunction double-side solar cell and preparation method thereof |
| CN103928539A (en) * | 2013-01-11 | 2014-07-16 | 国际商业机器公司 | Multi-junction Iii-v Solar Cell And Manufacturing Method Thereof |
| CN110233180A (en) * | 2019-06-02 | 2019-09-13 | 苏州腾晖光伏技术有限公司 | The preparation method of p-type back side tunnel oxide passivation contact solar cell |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102738291A (en) * | 2012-07-07 | 2012-10-17 | 蚌埠玻璃工业设计研究院 | Silicon-based heterojunction double-side solar cell and preparation method thereof |
| CN103928539A (en) * | 2013-01-11 | 2014-07-16 | 国际商业机器公司 | Multi-junction Iii-v Solar Cell And Manufacturing Method Thereof |
| CN110233180A (en) * | 2019-06-02 | 2019-09-13 | 苏州腾晖光伏技术有限公司 | The preparation method of p-type back side tunnel oxide passivation contact solar cell |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN114300564B (en) * | 2021-12-28 | 2024-04-05 | 武汉锐科光纤激光技术股份有限公司 | Double-sided solar cell and manufacturing method thereof |
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