CN111010147B - IGBT gate driver of double-slope peak suppression analog circuit - Google Patents
IGBT gate driver of double-slope peak suppression analog circuit Download PDFInfo
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- CN111010147B CN111010147B CN201911226145.2A CN201911226145A CN111010147B CN 111010147 B CN111010147 B CN 111010147B CN 201911226145 A CN201911226145 A CN 201911226145A CN 111010147 B CN111010147 B CN 111010147B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/021—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of more than one type of element or means, e.g. BIMOS, composite devices such as IGBT
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses an IGBT gate driver of a double-slope peak suppression analog circuit, which comprises: the device comprises a power supply and protection circuit, an isolation driving circuit, an IGBT overvoltage clamping circuit and an interference filter circuit; the power supply and protection circuit converts input high-frequency alternating current into direct current, monitors the power supply in real time, and locks IGBT driving signals when detecting power supply abnormality; the isolation driving circuit receives a light driving signal sent by the upper computer, converts the light driving signal into a +IGBT grid driving signal, controls the slope of an IGBT grid voltage change curve, and achieves the aim of inhibiting grid voltage spikes by reducing the rising or falling slope at the tail end of the curve; the overvoltage clamping circuit monitors and compares the driving signal and the voltages at two ends of the IGBT in real time; the interference filter circuit can filter high-frequency electromagnetic interference and prevent the IGBT from being turned on by mistake. The invention realizes the control and protection functions of the IGBT through the analog circuit, controls the output waveform through the push-pull circuit, and has the characteristics of high action speed and continuously adjustable waveform.
Description
Technical Field
The invention belongs to the technical field of control of power electronics and power automation equipment, and particularly relates to an IGBT gate driver of a double-slope peak suppression analog circuit.
Background
At present, the domestic and foreign IGBT driver technology is mature in application in the field of medium and small power, mainly adopts a digital control mode to realize driving, and has single function; the IGBT integrates the advantages of MOSFET and GTR, has the characteristics of high input impedance, fast switching speed, good thermal stability, reduced on-state voltage, high withstand voltage, large withstand current, and the like, and has been widely used in various fields in recent years. The adoption of a set of driving circuit with good performance can shorten the switching time and reduce the switching loss, so that the IGBT works in an ideal switching state, and has important significance on the running efficiency, the reliability and the safety of products. IGBTs are voltage controlled devices in which a direct voltage of ten or more volts is applied between the gate and emitter electrodes, and only microamperes of current flow. The IGBT driver is an interface circuit between the IGBT and the controller DSP chip, and has the function of converting a control signal from the digital signal processor into a driving signal with enough power to realize safe on and off of the IGBT and provide electrical isolation between the processor and the IGBT. In order for the IGBT to be properly and effectively protected in the event of a system failure, the IGBT driver also needs to provide a corresponding overvoltage protection function.
In the related art, the single slope is mostly adopted to control the on and off of the IGBT, the control mode can generate peak voltage at the grid electrode of the IGBT, the IGBT is easy to damage under the environment of strong electromagnetic interference (such as driving 3300V and 1500A high-voltage high-power IGBT), and the reliability of the system is reduced. In addition, the fault protection of the IGBT mostly adopts overcurrent protection, and the false alarm rate of the protection mode is higher.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an IGBT gate driver with a dual slope spike suppression analog circuit, so as to meet the requirements of miniaturization trend of the current high-power inverter; the driver of the invention adopts a dual-slope peak suppression analog circuit to control the IGBT grid. In the linear amplifying region of the IGBT, the driver outputs a gate driving signal with a larger slope so as to reduce the heating value of the IGBT, and in the saturated conducting region of the IGBT, the driver outputs a low-slope driving signal so as to inhibit the voltage spike of the gate. The adoption of overvoltage protection can effectively prevent breakdown of the IGBT, further avoid damage of the inverter and reduce the possibility of false alarm. The invention can flexibly adjust the output waveform curve according to specific IGBT model, and the output waveform is continuous and smooth, thus having wide application range.
In order to achieve the above purpose, the invention adopts the following technical scheme:
the invention relates to an IGBT gate driver of a dual-slope peak suppression analog circuit, which comprises: the device comprises a power supply and protection circuit, an isolation driving circuit, an IGBT overvoltage clamping circuit and an interference filter circuit;
wherein, the power supply and protection circuit includes: the power supply circuit converts the input high-frequency alternating current into direct current and outputs DC+ V, DC + V, DC +12.4V and DC-25V power supply; the power supply protection circuit monitors the power supply in real time, and when the power supply is abnormal, the output of an IGBT (insulated gate bipolar transistor) on-driving signal is forbidden, so that the IGBT is always kept in an off state;
the isolation driving circuit receives a light driving signal sent by an upper computer, converts the light driving signal into a +15V and-10V IGBT gate driving signal and inhibits the IGBT gate voltage spike in a double-slope mode;
the IGBT overvoltage clamping circuit judges whether overvoltage conditions exist according to the received upper computer driving signals and the voltage values at two ends of the IGBT; if overvoltage exists, the IGBT is controlled to be turned on slightly, so that the voltage at two ends of the IGBT is reduced, and the breakdown of the IGBT is prevented;
the interference filter circuit filters high-frequency electromagnetic interference to prevent the IGBT from misoperation.
Preferably, the power supply circuit includes: high-frequency transformer TR1, diodes V1-V4, voltage regulators U1 and U6, resistors R10, R11, R60, and capacitors C1, C2, C10, C60, C61, C80; the high-frequency transformer TR1 realizes electric isolation of a power circuit, magnetic field coupling realizes electric energy transmission, the input voltage is AC 24V, and the output is AC 25V; the diode components V1-V4 form a bridge rectifier circuit and are connected with the output end of the high-frequency transformer TR1, so that alternating current output by the high-frequency transformer TR1 is converted into direct current, and DC+25V and DC-25V are output; the capacitors C1 and C2 form a voltage dividing circuit to provide a 0V reference for the power supply; the voltage regulator U1 and peripheral elements R10, R11, C10 and C80 thereof form a voltage stabilizing circuit and output DC+12.4V; the voltage regulator U6 and peripheral components R60, C60 and C61 thereof form a voltage stabilizing circuit and output DC+20V.
The 1, 3 pin short circuit, 2, 4 pin short circuit, 8, 9, 11, 14 pin short circuit, 10, 12 pin short circuit, 7, 13 pin short circuit of the transformer TR 1; the diode V1 1 pin is connected with the diode V3 2 pin, the diode V2 1 pin is connected with the diode V4 2 pin, the diode V2 2 pin is connected with the diode V1 2 pin, and the diode V4 1 pin is connected with the diode V3 1 pin; the TR1 pin 12 is connected with the V2 1 pin, and the TR1 pin 13 is connected with the V1 1 pin; the pin of the capacitor C1 1 is connected with the pin of the capacitor C2 2; the TR1 pin is connected with the C1 1 pin, the C1 2 pin is connected with the V1 2 pin, and the C2 1 pin is connected with the V3 1 pin; the capacitor C1 2 outputs a DC+25V network, the capacitor C2 1 outputs a DC-25V network, and the capacitor C1 1 outputs a DC 0V network;
The capacitor C60 2 is connected with a DC+25V network, the 1 pin is connected with the resistor R60 2 pin, and the R60 1 pin is connected with 0V;
the U6 6 pin of the voltage stabilizer is connected with the C60 pin 1, and the U60, 3, 6 and 7 pins are in short circuit;
the C61 pin of the capacitor is connected with the U6 1 pin, and the 2 pin is connected with the DC+25V network. The U6 1 pin outputs DC+20V;
the capacitor C10 is connected with a DC+25V network by a pin C10, and is connected with a DC0V network by a pin C1;
the U1 1 pin of the voltage stabilizer is connected with the C10 pin, the U1 2, the U3, the U6 pin and the U7 pin are short-circuited, and the 4 pin is connected with the R11 pin of the resistor;
the resistor R11 pin is connected with the resistor R10 pin, and the resistor R10 pin is connected with a DC0V network; the R11 pin is connected with the U16 pin;
the C80 pin 2 of the capacitor is connected with the U16 pin, and the C80 pin 1 is connected with a DC0V network;
the C11 pin 2 of the capacitor is connected with the U16 pin, the C11 pin 1 is connected with a DC0V network, and DC+12.4V is output.
Preferably, the power supply protection circuit includes: comparator U3, voltage regulator U2, triodes V31, V33, V54, V56, V21, V22, diodes V30, V32, voltage regulator V20, resistors R30, R31, R32, R33, R34, R35, R36, R37, R38, R54, R56, R57, R20, R21, R22, R23, R24, R25, capacitors C30, C31, C32, C56, C20;
the comparator U3A, the diode V30, the diode V32, the triode V31, the triode V33, the peripheral resistors R30-R35 and the capacitor C30 form a DC+25V and DC-25V power supply monitoring protection circuit; the comparator U3B, the triode V33, the triode V54, peripheral resistors R36-R38 and R54, the capacitors C31 and C32 form a delay control circuit, and the delay control circuit is used for controlling the locking time of the IGBT; triode V56, resistance R57, make up DC +20V power monitoring protective circuit;
The voltage stabilizing tube V20, the resistor R20 and the resistor R21 form a reference voltage circuit, and a reference voltage is provided for the triode V21; the voltage stabilizer U2, the triode V21, the triode V22 and the resistors R21-R25 form a low-voltage locking circuit, and when the voltage is low, an IGBT locking signal is output.
The resistor R30 pin is connected with the resistor R31 pin, the resistor R30 pin is connected with DC+12.4V, and the resistor R31 pin is connected with a DC-25V network;
the diode V30 pin is connected with the R31 pin, and the V30 pin 1 is connected with DC 0V;
the resistor R32 pin is connected with the triode V31 pin, the R32 pin is connected with DC+25V, the V31 pin is connected with the V30 pin, and the V31 pin is connected with DC 0V;
the R33 pin of the resistor is connected with DC 0V, and the R33 pin 2 of the resistor is connected with the R32 pin 1;
the comparator U3A 3 pin is connected with DC 12.4V, the U3A 2 pin is connected with R33 pin, the U3A 4 pin is connected with DC 0V, the U3A 8 pin is connected with DC+25V, and the U3A 1 pin is connected with resistor R34 pin;
the C30 pin of the capacitor is connected with the U3A 8 pin, and the C30 pin 1 is connected with DC 0V;
the R34 pin 2 of the resistor is connected with DC+25V, and the R34 pin 1 is connected with the U3A 1 pin;
the diode V32 pin is connected with the R34 pin 1, and the diode V32 pin is connected with the resistor R35 pin 3;
the resistor R35 pin 2 is connected with the triode V33 pin 1, and the R35 pin 1 is connected with DC 0V;
the triode V33 is connected with the R35 pin, the V33 pin is connected with the DC 0V, and the V33 3 pin is connected with the R36 pin;
The resistor R36 pin is connected with the capacitor C31 pin, and the capacitor C31 pin is connected with DC 0V;
the C32 pin of the capacitor is connected with the C31 pin of the capacitor, and the C32 pin is connected with DC 0V;
the comparator U3B 5 pin is connected with the C32 pin, the C32 pin is connected with the resistor R37 pin, the resistor R37 pin is connected with Dc+25V, the U3B 6 pin is connected with DC 12.4V, the U3B 7 pin is connected with the resistor R38 pin, and the resistor R38 pin is connected with DC+25V;
the R54 pin 2 of the resistor is connected with the R38 pin 2, and the R54 pin 1 is connected with the V54 pin of the triode;
the triode V54 pin is connected with a DC+25V network, and the triode V54 pin 3 is connected with the triode V56 pin 2;
the resistor R56 pin is connected with a DC+25V network, the resistor R56 pin is connected with the resistor R57 pin, and the resistor R57 pin 1 is connected with DC 20V;
the triode V56 1 is connected with the R57 pin, the V56 3 pin is connected with the DC+25V network, and the V56 2 pin is connected with the V54 pin 3;
the resistor R20 pin is connected with a DC+25V network, the R20 pin is connected with the voltage stabilizing tube V20 pin 3, the V20 pin is connected with the resistor R21 pin R2, and the R21 pin is connected with DC 0V;
the voltage stabilizing tube U2 pin is connected with the capacitor C20 pin and a DC+25V network, the U2 4 pin is connected with the resistor R22 pin, and the capacitor C20 pin is connected with DC 0V;
the resistor R23 pin 2 is connected with the U2 4 pin, and the R23 pin 1 is connected with the triode V21 pin 3;
the triode V21 pin is connected with the R21 pin 2 of the resistor, and the V21 pin 2 is connected with DC 0V;
the R24 pin of the resistor is connected with the V21 pin, and the R24 pin of the resistor is connected with the V22 pin of the triode V24;
The resistor R22 pin is connected with the triode V22 pin, the resistor V22 pin is connected with the R25 pin, the resistor V22 pin is connected with the DC+25V pin, and the resistor R25 pin is connected with the DC+25V pin;
resistor R25 is connected with the V120/V82/V22 network by pin, and V56 is connected with the V51/V56 network by pin 2.
Preferably, the isolation driving circuit includes: the optical fiber receiver U4, the jumper connector X4, the exclusive-OR gate chip U5, the triodes V50, V51, V13, V120, V121, V124, V125, V126, V127, the voltage stabilizing tubes V10, V11, V12, V23, V93, the diodes V92, V94, V122, V128, V135, and the resistors R31, R40, R41, R50, R51, R52, R53, R95, R96, R97, R120, R121, R124, R125, R126, R127, R128, R135, R136, R139 and the capacitors C12, C61, C96;
the optical fiber receiver U4 converts the optical driving signal sent by the upper computer into an internal control signal, the control signal is amplified by the exclusive-or gate chip U5 and amplified by the triode V50 and then output to the base electrode of the triode V124, and the V124 controls the output of the push-pull amplifying circuits V126, V127, V121 and V125 so as to control the IGBT to turn on the driving signal; meanwhile, the push-pull amplifying circuit realizes the control of the slope of the driving signal; the optical fiber receiver U4, the exclusive-OR gate chip U5, the resistor R41, the resistor R40 and the jumper connector X4 form an optical fiber input circuit, and receive an upper computer control signal; triode V50, resistance R50-R53, form the first-level amplifying circuit, further amplify the control signal, output to protecting and controlling circuit; and the third transistor V51 is used for locking the IGBT starting signal. The diode V92 and the voltage stabilizing tube V93 are used for adjusting the voltage of the control signal;
The voltage stabilizing tube V10, V11, V12 and R31 form a voltage stabilizing reference circuit, a reference potential is provided for the triode V13, the output end of the V136 is connected with the base electrode of the V124, and the push-pull amplifying circuit is controlled to output an IGBT turn-off driving signal; meanwhile, the push-pull amplifying circuit realizes the control of the slope of the driving signal; the triode V13, the resistor R97, the resistor R95, the resistor R96 and the capacitor C96 form a primary IGBT turn-off signal control circuit which is used for delay control of the primary IGBT turn-off signal;
triode V120 is used for low voltage locking control; the diode V122 and the voltage stabilizing tube V123 are used for potential adjustment; the triode V124 and the resistor R124 form an interlocking control circuit which is used for interlocking the driving signals of the IGBT switch; the triodes V126 and V121, the triodes V127 and V125, the resistor R121 and the resistor R125 form a push-pull output and amplification circuit which is used for controlling a driving signal of the two-stage IGBT and realizing a double-slope peak suppression function; diode V128, resistance R126-R128, form IGBT grid current limiting circuit, finish the slope control of the voltage change curve of grid together with push-pull circuit;
diode V135, resistor R139 and indicator lamp H1 form IGBT turn-off output state indication circuit; the resistor R135 and the indicator lamp H2 form an IGBT on output state indicating circuit; resistor R136 is an IGBT gate GE shorting resistor.
The U4 4 pin of the optical fiber receiver is connected with a DC+25V network, the U4 2 pin is connected with a DC+20V network, and the U4 1 pin is connected with the R41 pin of the resistor;
the C61 pin and the U4 2 pin of the capacitor are connected, and the C61 pin and the U4 4 pin are connected;
the resistor R41 pin is connected with the pin U5 1 of the exclusive-OR gate chip, and the pin R41 2 is connected with DC+25V;
the resistor R40 pin 2 is connected with DC+25V, the R40 pin 1 is connected with the resistor R42 pin 2, and the R42 pin 1 is connected with DC+20V;
the X4 4 pin of the connector is connected with the R42 pin 2, the X4 1 pin is connected with the R42 pin 1, the X4 2 pin and the X4 1 pin are in short circuit, and the X3 pin is in short circuit;
the exclusive-OR gate chip U5 1 pin is connected with the resistor R41 pin, the U5 2 pin is connected with the resistor R42 pin, the U5 3 pin is connected with the resistor R50 pin, and the resistor R50 pin is connected with the triode V50 pin 1. U5 1, 4, 9, 12 pin short circuit, U5 2, 5, 10, 13 pin short circuit, U5 3, 6, 8, 11 pin short circuit. U5 7 pin is connected with DC+20V, U5 pin 14 pin is connected with DC+25V;
the triode V50 pin is connected with the resistor R51 pin, the R51 pin is connected with DC+25V, the triode V50 pin 2 pin and the triode V4 pin are connected with the resistor R52 pin, and the R52 pin 1 pin is connected with DC 0V;
resistor R53 pin R52 pin R53 and R53 pin 1 pin DC 0V. Meanwhile, the R53 pin leads out a V50/V70 network, and the R51 pin leads out a V50/V51 network;
the triode V51 is connected with a V50/V51 network by a V51 pin, the triode V51 is connected with a V51/V56 network by a V51 pin, and the triode V2 and the triode V4 are connected with a V92 pin 1. The V92 pin is connected with the V93 pin of the voltage stabilizing tube, and the V93 pin 1 is connected with DC 0V;
The voltage stabilizing tube V10 pin is connected with DC 0V, the V10 pin is connected with the voltage stabilizing tube V11 pin, the V11 pin is connected with the voltage stabilizing tube V12 pin, the V12 pin is connected with the R31 pin, and the R31 pin is connected with a DC-25V network;
the triode V13 is connected with the R31 pin, the V13 pin is connected with a DC-25V network, the V13 pin 2 is connected with the R97 pin and a V13/V95 network;
the diode V94 is connected with the pins V51, 4 of the triode V2, the pin V94 1 is connected with the V124/V90 network, and the pin V94 2 is connected with the V94/V95 network;
the C12 pin of the capacitor C12 is connected with the R97 pin and the C12 pin is connected with DC 0V;
the resistor R97 pin 2 is connected with the R95 pin 2, the R97 pin 1 is connected with the C95 pin 2, the C95 pin 1 is connected with the triode V124 pin 1 and the V124/V90 network;
the resistor R95 pin R95 is connected with the R97 pin R95 pin 1 is connected with the V124 pin 1;
the resistor R96 is connected with the R97 pin R96, and the R96 1 pin is connected with the V124 pin 1;
the triode V124 is connected with the pin V123 1 of the voltage stabilizing tube, the pins V124 and 4 are connected with the pin R1242, and the pin R124 is connected with the DC-25V network. The pin V123 is connected with the pin V1223 of the diode, and the pin V122 1 is connected with the pins V123 2 and 4 of the triode;
the triode V120 pin is connected with a V120/V82/V22 network, the V120 pin is connected with an R120 pin 1, and the R120 pin 2 is connected with a DC+25V network;
the V122 pin is connected with the V126 pin 1 of the triode, the V126 pins 2 and 4 pins are connected with the R121 pin and the R1212 pin is connected with the DC+25V network. V126 pin 3 is connected with R126 pin 2;
The triode V121 is connected with the pins V126 2 and 4, the pins V1212 and 4 are connected with the pin R1261, and the pin R126 is connected with the pin V126 3;
the triode V125 pin is connected with the R125 pin, the V125 pins 2 and 4 pins are connected with the V1212 and 4 pins, and the V125 pin 2 is connected with a DC-25V network;
the R145 2 pin of the resistor is connected with the V121 pins 2 and 4 pins, and the R145 1 pin is connected with the DC 0V;
the diode V128 pin R145 2 pin, the diode V128 pin R1271 pin;
the resistor R1272 is connected with the V128 pin, the R1271 is connected with the resistor R1272, the R128 pin is connected with the resistor R139 pin, the R139 pin is connected with the V1353 pin, the V135 1 pin is connected with the indicating lamp H1 1 pin, and the H1 2 pin is connected with DC 0V;
the resistor R135 pin R139 pin, the resistor R135 pin H2 2 pin and the resistor H2 1 pin DC 0V;
the X2 1 and 2 pins of the connector are in short circuit, the X2 1 and 2 pins of the connector are connected with the R135 2 pin of the resistor, the R136 pin is connected with the X2 2 pin, the R136 pin is connected with the X3 1 pin and the DC 0V, and the X3 and 2 pins are in short circuit.
Preferably, the IGBT overvoltage clamping circuit includes: comparator U7, triodes V80-V82, diode V70, diode V83, diode V90, diode V86, diode V87, resistors R70-R74, R80-R87, R101-R108, R111-R118, and capacitors C70, C71, C83, C88, C100, C111;
the IGBT overvoltage clamping action speed is related to the IGBT state and is divided into an IGBT working state and an idle state; in the IGBT working state, the clamp protection action speed is faster; the diode V70, the resistor R70 and the capacitor C71 form a delay circuit, so that the overvoltage clamping circuit is delayed to enter an IGBT idle clamping protection state;
The comparator U7, the resistors R72 and R71 form an IGBT working state detection circuit, and the resistors R72 and R71 provide reference voltages for the U7. The capacitor C71 is a U7 power supply filter capacitor;
triode V82, resistor R73, resistor R72, resistor R80 and resistor R81 form a pull-up circuit of the U7 output end;
the triode V81, the resistor R84 and the resistor R83 form an action circuit of over-voltage clamping; when overvoltage occurs, the IGBT micro-turn-on signal is forcedly output;
the triode V80, the diode V83 and the diode V90 form an overvoltage clamping output circuit to control the voltage of the IGBT GE pin;
the diode V86, the diode V87, the resistor R85, the resistor R87, the resistors R111-R118, the resistors R101-R108, the capacitor C88, the capacitor C111 and the capacitor C100 form an IGBT C pin voltage acquisition circuit; diodes V86, V87 are used for protection, resistors R85, R87 are pull-down resistors.
The resistor R70 2 is connected with a V50/V70 network, the resistor R70 1 is connected with the capacitor C71 2, and the resistor C71 is connected with DC 0V;
the diode V70 pin 3 is connected with the R70 pin 2, and the diode V70 pin 1 is connected with the R70 pin 1;
the resistor R72 pin is connected with DC+12.4V, the resistor R72 pin R71 pin R2 pin, and the resistor R71 pin R1 pin is connected with DC 0V;
the comparator U7A 3 is connected with the R71 pin, the U7A 2 is connected with the R70 pin. U7A 8 pin is connected with DC+12.4V, U7A 4 pin is connected with DC 0V; U7A 1 pin is connected with R73 pin 2;
the pin of the comparator U7B 6 is connected with the pin U7A 2, the pin U7B 5 is connected with the pin U7A 3, and the pin U7B 7 is connected with the pin R74 2;
Resistor R73 pin is connected with resistor R81 pin, resistor R74 pin is connected with resistor R80 pin;
the triode V82 pin is connected with a V120/V82/V22 network, the V82 pin 3 is connected with a resistor R82 pin 1, and the R82 pin 2 is connected with a DC+25V network; v82, 4 pins are connected with R82 pin and R80 pin 2;
the triode V81 3 is connected with the R81 pin, the V81 pin is connected with the capacitor C83 pin, and the C83 pin 1 is connected with DC 0V. V81, 4 pin connects DC 0V;
the R84 1 pin of the resistor is connected with the V81 pin, the R84 2 pin is connected with the V86 pin 3;
the diode V83 pin is connected with the triode V80 pin, the V83 1 pin and the 2 pin are connected with the R83 pin and the R83 pin 1 pin is connected with DC 0V;
the triode V80 pin is connected with DC+12.4V, the V80 pin is connected with the resistor R80 pin, the V80 pin 2 and the 4 pin are connected with the diode V90 pin 1, and the V90 pin 3 is connected with a V124/V90 network;
the diode V86 2 is connected with the R84 2 pin, and the V86 1 is connected with the capacitor C111 pin;
the pins X1 1 and 2 of the connector are short-circuited, the pin X1 2 is connected with the pin R101 and the pin R102, the pin R101 and the pin R102 are connected with the pin R103 and the pin R103, the pin R103 and the pin R104 2, R104 is connected with R105, R105 is connected with R106, R106 is connected with R107, R107 is connected with R108, R108 is connected with capacitor C100 1, C100 is connected with X1;
resistor R111 pin R106 pin, resistor R112 pin R1111 pin, resistor R113 pin R112 pin, resistor R114 pin R1131 pin, resistor R114 pin R115 pin, resistor R115 pin R1162 pin, resistor R116 pin R117 2 pin, resistor R117 1 pin R1182 pin, resistor R118 pin C111 1 pin, C111 pin R1112 pin;
the resistor R85 pin 2 is connected with the R86 pin 2, and the R85 pin 1 is connected with the R86 pin 1;
the diode V87 3 is connected with the R87 2 pin of the resistor, and the V87 1 pin is connected with DC 0V;
the C87 2 pin of the capacitor is connected with the R87 2 pin, and the C87 1 pin is connected with DC 0V;
the capacitor C88 2 is connected with the R87 2 pin, and the C88 1 is connected with the DC 0V pin.
Preferably, the interference filter circuit includes: transistor V91, transistor V95, resistors R90, R91, R94, R98, capacitor C94, capacitor C95;
the triode V91, the resistor R90, the resistor R91 and the resistor R98 form a filter function prohibiting circuit, and when an IGBT on signal arrives, the filter function is prohibited;
the triode V95, the resistor R94, the capacitor C94 and the capacitor C95 form a filter circuit, the output end of the V94 is pulled down, and the delay of the IGBT on driving signals is controlled.
The resistor R91 2 is connected with the V94/V51 network, the resistor R91 1 is connected with the resistor R98 2, and the resistor R98 1 is connected with the V13/V95 network;
the triode V91 is connected with the R91 pin, the V91 2 pin is connected with the R98 pin, the V91 3 pin is connected with the R90 pin, and the R90 pin is connected with DC 0V;
the triode V95 pin is connected with the R90 pin, the V95 pin is connected with the R94 pin 1, and the R94 pin 2 is connected with the V94/V95 network;
the capacitor C95 pin 2 is connected with the R94 pin 1, and the C95 pin 1 is connected with the V91 pin 2. The capacitor C94 is connected with the C95 pin C2, and the capacitor C94 is connected with the C95 pin C1.
The invention has the beneficial effects that:
the driver has the characteristics of high integration level, strong anti-interference capability, high reaction speed and low energy consumption, and can meet the requirements of high-frequency high-speed IGBT control; the invention adopts a double-slope mode to inhibit peak voltages of the G and E ends of the IGBT, and can better protect the IGBT. The over-voltage clamping is used for preventing the voltage across the IGBT from being too high, so that the IGBT breaks down. In addition, the driver has a power supply voltage protection design, and when the power supply voltage exceeds a reasonable range, the IGBT is locked to turn on output. The drive signal is transmitted through the optical fiber, so that a better isolation effect is achieved. The state of the IGBT is monitored by adopting an analog circuit, and delay triggering is performed; the push-pull circuit is used for controlling the output waveform, and the push-pull circuit has the characteristics of high action speed and continuous and adjustable waveform.
The invention greatly meets the requirement of the miniaturization trend of the current high-power inverter and is the necessary trend of the development of the IGBT gate driver in the future.
The invention is realized by using the analog circuit formed by discrete components, and has the characteristics of high flexibility and low cost.
Drawings
Fig. 1 is a schematic diagram of the operation of the driver of the present invention.
Fig. 2 is a schematic structural diagram of the actuator of the present invention.
Fig. 3 is a schematic diagram of a power supply circuit.
Fig. 4 is a schematic diagram of a power protection circuit.
Fig. 5 is a schematic diagram of an isolated drive circuit.
Fig. 6 is a schematic diagram of an IGBT over-voltage clamp circuit.
Fig. 7 is a schematic diagram of an interference filter circuit.
Detailed Description
The invention will be further described with reference to examples and drawings, to which reference is made, but which are not intended to limit the scope of the invention.
Referring to fig. 1 and 2, an IGBT gate driver of a dual slope spike suppression analog circuit according to the present invention includes: the device comprises a power supply and protection circuit, an isolation driving circuit, an IGBT overvoltage clamping circuit and an interference filter circuit;
wherein, the power supply and protection circuit includes: the power supply circuit converts the input high-frequency alternating current into direct current and outputs DC+ V, DC + V, DC +12.4V and DC-25V power supply; the power supply protection circuit monitors the power supply in real time, and when the power supply is abnormal, the output of an IGBT (insulated gate bipolar transistor) on-driving signal is forbidden, so that the IGBT is always kept in an off state;
the isolation driving circuit receives a light driving signal sent by an upper computer, converts the light driving signal into a +15V and-10V IGBT gate driving signal and inhibits the IGBT gate voltage spike in a double-slope mode;
The IGBT overvoltage clamping circuit judges whether overvoltage conditions exist according to the received upper computer driving signals and the voltage values at two ends of the IGBT; if overvoltage exists, the IGBT is controlled to be turned on slightly, so that the voltage at two ends of the IGBT is reduced, and the breakdown of the IGBT is prevented;
the interference filter circuit filters high-frequency electromagnetic interference, prevents the IGBT from misoperation, and improves the stability of the driver.
Referring to fig. 3, the power supply circuit includes: high-frequency transformer TR1, diodes V1-V4, voltage regulators U1 and U6, resistors R10, R11, R60, and capacitors C1, C2, C10, C60, C61, C80; the high-frequency transformer TR1 realizes electric isolation of a power circuit, magnetic field coupling realizes electric energy transmission, the input voltage is AC 24V, and the output is AC 25V; the diode components V1-V4 form a bridge rectifier circuit and are connected with the output end of the high-frequency transformer TR1, so that alternating current output by the high-frequency transformer TR1 is converted into direct current, and DC+25V and DC-25V are output; the capacitors C1 and C2 form a voltage dividing circuit to provide a 0V reference for the power supply; the voltage regulator U1 and peripheral elements R10, R11, C10 and C80 thereof form a voltage stabilizing circuit and output DC+12.4V; the voltage regulator U6 and peripheral components R60, C60 and C61 thereof form a voltage stabilizing circuit and output DC+20V.
The 1, 3 pin short circuits, 2, 4 pin short circuits, 8, 9, 11, 14 pin short circuits, 10, 12 pin short circuits and 7, 13 pin short circuits of the transformer TR 1. The diode V1 1 pin is connected with the diode V3 2 pin, the diode V2 1 pin is connected with the diode V4 2 pin, the diode V2 2 pin is connected with the diode V1 2 pin, and the diode V4 1 pin is connected with the diode V3 1 pin. The TR1 pin 12 is connected with the V2 1 pin, and the TR1 pin 13 is connected with the V1 1 pin. The pin of the capacitor C1 1 is connected with the pin of the capacitor C2 2. The TR1 pin is connected with the C1 1 pin, the C1 2 pin is connected with the V1 2 pin, and the C2 1 pin is connected with the V3 1 pin. The capacitor C1 2 outputs a DC+25V network, the capacitor C2 1 outputs a DC-25V network, and the capacitor C1 1 outputs a DC0V network;
the capacitor C60 2 is connected with a DC+25V network, the 1 pin is connected with the resistor R60 2 pin, and the R60 1 pin is connected with 0V;
the U6 6 pin of the voltage stabilizer is connected with the C60 pin 1, and the U60, 3, 6 and 7 pins are in short circuit;
the C61 pin of the capacitor is connected with the U6 1 pin, and the 2 pin is connected with the DC+25V network. The U6 1 pin outputs DC+20V;
the capacitor C10 is connected with a DC+25V network by a pin C10, and is connected with a DC0V network by a pin C1;
the U1 1 pin of the voltage stabilizer is connected with the C10 pin, the U1 2, the U3, the U6 pin and the U7 pin are short-circuited, and the 4 pin is connected with the R11 pin of the resistor;
the resistor R11 pin is connected with the resistor R10 pin, and the resistor R10 pin is connected with a DC0V network; the R11 pin is connected with the U16 pin;
the C80 pin 2 of the capacitor is connected with the U16 pin, and the C80 pin 1 is connected with a DC0V network;
The C11 pin 2 of the capacitor is connected with the U16 pin, the C11 pin 1 is connected with a DC 0V network, and DC+12.4V is output.
Referring to fig. 4, the power protection circuit includes: comparator U3, voltage regulator U2, triodes V31, V33, V54, V56, V21, V22, diodes V30, V32, voltage regulator V20, resistors R30, R31, R32, R33, R34, R35, R36, R37, R38, R54, R56, R57, R20, R21, R22, R23, R24, R25, capacitors C30, C31, C32, C56, C20;
the comparator U3A, the diode V30, the diode V32, the triode V31, the triode V33, the peripheral resistors R30-R35 and the capacitor C30 form a DC+25V and DC-25V power supply monitoring protection circuit; the comparator U3B, the triode V33, the triode V54, peripheral resistors R36-R38 and R54, the capacitors C31 and C32 form a delay control circuit, and the delay control circuit is used for controlling the locking time of the IGBT; triode V56, resistance R57, make up DC +20V power monitoring protective circuit;
the voltage stabilizing tube V20, the resistor R20 and the resistor R21 form a reference voltage circuit, and a reference voltage is provided for the triode V21; the voltage stabilizer U2, the triode V21, the triode V22 and the resistors R21-R25 form a low-voltage locking circuit, and when the voltage is low, an IGBT locking signal is output.
The resistor R30 pin is connected with the resistor R31 pin, the resistor R30 pin is connected with DC+12.4V, and the resistor R31 pin is connected with a DC-25V network;
the diode V30 pin is connected with the R31 pin, and the V30 pin 1 is connected with DC 0V;
the resistor R32 pin is connected with the triode V31 pin, the R32 pin is connected with DC+25V, the V31 pin is connected with the V30 pin, and the V31 pin is connected with DC 0V;
the R33 pin of the resistor is connected with DC 0V, and the R33 pin 2 of the resistor is connected with the R32 pin 1;
the comparator U3A 3 pin is connected with DC 12.4V, the U3A 2 pin is connected with R33 pin, the U3A 4 pin is connected with DC 0V, the U3A 8 pin is connected with DC+25V, and the U3A 1 pin is connected with resistor R34 pin;
the C30 pin of the capacitor is connected with the U3A 8 pin, and the C30 pin 1 is connected with DC 0V;
the R34 pin 2 of the resistor is connected with DC+25V, and the R34 pin 1 is connected with the U3A 1 pin;
the diode V32 pin is connected with the R34 pin 1, and the diode V32 pin is connected with the resistor R35 pin 3;
the resistor R35 pin 2 is connected with the triode V33 pin 1, and the R35 pin 1 is connected with DC 0V;
the triode V33 is connected with the R35 pin, the V33 pin is connected with the DC 0V, and the V33 3 pin is connected with the R36 pin;
the resistor R36 pin is connected with the capacitor C31 pin, and the capacitor C31 pin is connected with DC 0V;
the C32 pin of the capacitor is connected with the C31 pin of the capacitor, and the C32 pin is connected with DC 0V;
the comparator U3B 5 pin is connected with the C32 pin, the C32 pin is connected with the resistor R37 pin, the resistor R37 pin is connected with Dc+25V, the U3B 6 pin is connected with DC 12.4V, the U3B 7 pin is connected with the resistor R38 pin, and the resistor R38 pin is connected with DC+25V.
The R54 pin 2 of the resistor is connected with the R38 pin 2, and the R54 pin 1 is connected with the pin V54 1 of the triode.
The triode V54 pin is connected with a DC+25V network, and the triode V54 pin 3 is connected with the triode V56 pin 2.
The triode V56 pin is connected with the resistor R57 pin, the V56 pin is connected with the DC+25V network, and the V56 pin 2 is connected with the V54 pin 3.
The resistor R20 pin is connected with a DC+25V network, the R20 pin is connected with the voltage stabilizing tube V20 pin 3, the V20 pin is connected with the resistor R21 pin R2, and the R21 pin is connected with DC 0V.
The voltage regulator tube U2 pin connects capacitor C20 pin and DC+25V network, U2 4 pin connects resistor R22 pin, capacitor C20 pin connects DC 0V.
The R23 pin 2 of the resistor is connected with the U2 4 pin, and the R23 pin 1 is connected with the V21 pin 3 of the triode.
The triode V21 is connected with the pin R21 2 of the resistor, and the pin V21 2 is connected with DC 0V.
The R24 pin of the resistor is connected with the V21 pin and the R24 pin of the resistor is connected with the V22 pin of the triode V24.
The resistor R22 is connected with the triode V22 1, the resistor V22 is connected with the R25 1, the resistor V22 is connected with the DC+25V, and the resistor R25 is connected with the DC+25V.
Resistor R25 is connected with the V120/V82/V22 network by pin, and V56 is connected with the V51/V56 network by pin 2.
Referring to fig. 5, the isolation driving circuit includes: the optical fiber receiver U4, the jumper connector X4, the exclusive-OR gate chip U5, the triodes V50, V51, V13, V120, V121, V124, V125, V126, V127, the voltage stabilizing tubes V10, V11, V12, V23, V93, the diodes V92, V94, V122, V128, V135, and the resistors R31, R40, R41, R50, R51, R52, R53, R95, R96, R97, R120, R121, R124, R125, R126, R127, R128, R135, R136, R139 and the capacitors C12, C61, C96;
The optical fiber receiver U4 converts the optical driving signal sent by the upper computer into an internal control signal, the control signal is amplified by the exclusive-or gate chip U5 and amplified by the triode V50 and then output to the base electrode of the triode V124, and the V124 controls the output of the push-pull amplifying circuits V126, V127, V121 and V125 so as to control the IGBT to turn on the driving signal; meanwhile, the push-pull amplifying circuit realizes the control of the slope of the driving signal; the optical fiber receiver U4, the exclusive-OR gate chip U5, the resistor R41, the resistor R40 and the jumper connector X4 form an optical fiber input circuit, and receive an upper computer control signal; triode V50, resistance R50-R53, form the first-level amplifying circuit, further amplify the control signal, output to protecting and controlling circuit; and the third transistor V51 is used for locking the IGBT starting signal. The diode V92 and the voltage stabilizing tube V93 are used for adjusting the voltage of the control signal;
the voltage stabilizing tube V10, V11, V12 and R31 form a voltage stabilizing reference circuit, a reference potential is provided for the triode V13, the output end of the V136 is connected with the base electrode of the V124, and the push-pull amplifying circuit is controlled to output an IGBT turn-off driving signal; meanwhile, the push-pull amplifying circuit realizes the control of the slope of the driving signal; the triode V13, the resistor R97, the resistor R95, the resistor R96 and the capacitor C96 form a primary IGBT turn-off signal control circuit which is used for delay control of the primary IGBT turn-off signal;
Triode V120 is used for low voltage locking control; the diode V122 and the voltage stabilizing tube V123 are used for potential adjustment; the triode V124 and the resistor R124 form an interlocking control circuit which is used for interlocking the driving signals of the IGBT switch; the triodes V126 and V121, the triodes V127 and V125, the resistor R121 and the resistor R125 form a push-pull output and amplification circuit which is used for controlling a driving signal of the two-stage IGBT and realizing a double-slope peak suppression function; diode V128, resistance R126-R128, form IGBT grid current limiting circuit, finish the slope control of the voltage change curve of grid together with push-pull circuit;
diode V135, resistor R139 and indicator lamp H1 form IGBT turn-off output state indication circuit; the resistor R135 and the indicator lamp H2 form an IGBT on output state indicating circuit; resistor R136 is an IGBT gate GE shorting resistor.
The U4 4 pin of the optical fiber receiver is connected with a DC+25V network, the U4 2 pin is connected with a DC+20V network, and the U4 1 pin is connected with the R41 pin of the resistor;
the C61 pin and the U4 2 pin of the capacitor are connected, and the C61 pin and the U4 4 pin are connected;
the resistor R41 pin is connected with the pin U5 1 of the exclusive-OR gate chip, and the pin R41 2 is connected with DC+25V;
the resistor R40 pin 2 is connected with DC+25V, the R40 pin 1 is connected with the resistor R42 pin 2, and the R42 pin 1 is connected with DC+20V;
The X4 4 pin of the connector is connected with the R42 pin 2, the X4 1 pin is connected with the R42 pin 1, the X4 2 pin and the X4 1 pin are in short circuit, and the X3 pin is in short circuit;
the exclusive-OR gate chip U5 1 pin is connected with the resistor R41 pin, the U5 2 pin is connected with the resistor R42 pin, the U5 3 pin is connected with the resistor R50 pin, and the resistor R50 pin is connected with the triode V50 pin 1. U5 1, 4, 9, 12 pin short circuit, U5 2, 5, 10, 13 pin short circuit, U5 3, 6, 8, 11 pin short circuit. U5 7 pin is connected with DC+20V, U5 pin 14 pin is connected with DC+25V;
the triode V50 pin is connected with the resistor R51 pin, the R51 pin is connected with DC+25V, the triode V50 pin 2 pin and the triode V4 pin are connected with the resistor R52 pin, and the R52 pin 1 pin is connected with DC 0V;
resistor R53 pin R52 pin R53 and R53 pin 1 pin DC 0V. Meanwhile, the R53 pin leads out a V50/V70 network, and the R51 pin leads out a V50/V51 network;
the triode V51 is connected with a V50/V51 network by a V51 pin, the triode V51 is connected with a V51/V56 network by a V51 pin, and the triode V2 and the triode V4 are connected with a V92 pin 1. The V92 pin is connected with the V93 pin of the voltage stabilizing tube. V93 pin DC 0V;
the voltage stabilizing tube V10 pin is connected with DC 0V, the V10 pin is connected with the voltage stabilizing tube V11 pin, the V11 pin is connected with the voltage stabilizing tube V12 pin, the V12 pin is connected with the R31 pin, and the R31 pin is connected with a DC-25V network;
the triode V13 is connected with the R31 pin, the V13 pin is connected with a DC-25V network, the V13 pin 2 is connected with the R97 pin and a V13/V95 network;
the diode V94 is connected with the pins V51, 4 of the triode V2, the pin V94 1 is connected with the V124/V90 network, and the pin V94 2 is connected with the V94/V95 network;
The C12 pin of the capacitor C12 is connected with the R97 pin and the C12 pin is connected with DC 0V;
the resistor R97 pin 2 is connected with the R95 pin 2, the R97 pin 1 is connected with the C95 pin 2, the C95 pin 1 is connected with the triode V124 pin 1 and the V124/V90 network;
the resistor R95 pin R95 is connected with the R97 pin R95 pin 1 is connected with the V124 pin 1;
the resistor R96 is connected with the R97 pin R96, and the R96 1 pin is connected with the V124 pin 1;
the triode V124 is connected with the pin V123 1 of the voltage stabilizing tube, the pins V124 and 4 are connected with the pin R1242, and the pin R124 is connected with the DC-25V network. The pin V123 is connected with the pin V122 of the diode, and the pin V122 1 is connected with the pins V123 2 and 4 of the triode;
the triode V120 pin is connected with a V120/V82/V22 network, the V120 pin is connected with an R120 pin 1, and the R120 pin 2 is connected with a DC+25V network;
the V122 pin is connected with the V126 pin 1 of the triode, the V126 pins 2 and 4 pins are connected with the R121 pin and the R1212 pin is connected with the DC+25V network. V126 pin 3 is connected with R126 pin 2;
the triode V121 is connected with the pins V126 2 and 4, the pins V1212 and 4 are connected with the pin R1261, and the pin R126 is connected with the pin V126 3;
the triode V125 pin is connected with the R125 pin, the V125 pins 2 and 4 pins are connected with the V1212 and 4 pins, and the V125 pin 2 is connected with a DC-25V network;
the R145 2 pin of the resistor is connected with the V121 pins 2 and 4 pins, and the R145 1 pin is connected with the DC 0V;
the diode V128 pin R145 2 pin, the diode V128 pin R1271 pin;
The resistor R1272 is connected with the V128 pin, the R127 1 is connected with the resistor R1272, the R128 pin is connected with the resistor R139 pin, the R139 pin is connected with the V1353 pin, the V135 1 pin is connected with the indicating lamp H1 1 pin, and the H1 2 pin is connected with DC 0V;
the resistor R135 pin R139 pin, the resistor R135 pin H2 2 pin and the resistor H2 1 pin DC 0V;
the X2 1 and 2 pins of the connector are in short circuit, the X2 1 and 2 pins of the connector are connected with the R135 2 pin of the resistor, the R136 pin is connected with the X2 2 pin, the R136 pin is connected with the X3 1 pin and the DC 0V, and the X3 and 2 pins are in short circuit.
Referring to fig. 6, the IGBT overvoltage clamping circuit includes: comparator U7, triodes V80-V82, diode V70, diode V83, diode V90, diode V86, diode V87, resistors R70-R74, R80-R87, R101-R108, R111-R118, and capacitors C70, C71, C83, C88, C100, C111;
the IGBT overvoltage clamping action speed is related to the IGBT state and is divided into an IGBT working state and an idle state; in the IGBT working state, the clamp protection action speed is faster; the diode V70, the resistor R70 and the capacitor C71 form a delay circuit, so that the overvoltage clamping circuit is delayed to enter an IGBT idle clamping protection state;
the comparator U7, the resistors R72 and R71 form an IGBT working state detection circuit, and the resistors R72 and R71 provide reference voltages for the U7. The capacitor C71 is a U7 power supply filter capacitor;
Triode V82, resistor R73, resistor R72, resistor R80 and resistor R81 form a pull-up circuit of the U7 output end;
the triode V81, the resistor R84 and the resistor R83 form an action circuit of over-voltage clamping; when overvoltage occurs, the IGBT micro-turn-on signal is forcedly output;
the triode V80, the diode V83 and the diode V90 form an overvoltage clamping output circuit to control the voltage of the IGBT GE pin;
the diode V86, the diode V87, the resistor R85, the resistor R87, the resistors R111-R118, the resistors R101-R108, the capacitor C88, the capacitor C111 and the capacitor C100 form an IGBT C pin voltage acquisition circuit; diodes V86, V87 are used for protection, resistors R85, R87 are pull-down resistors.
The resistor R70 2 is connected with a V50/V70 network, the resistor R70 1 is connected with the capacitor C71 2, and the resistor C71 is connected with DC 0V;
the diode V70 pin 3 is connected with the R70 pin 2, and the diode V70 pin 1 is connected with the R70 pin 1;
the resistor R72 pin is connected with DC+12.4V, the resistor R72 pin R71 pin R2 pin, and the resistor R71 pin R1 pin is connected with DC 0V;
the comparator U7A 3 is connected with the R71 pin, the U7A 2 is connected with the R70 pin. U7A 8 pin is connected with DC+12.4V, U7A 4 pin is connected with DC 0V; U7A 1 pin is connected with R73 pin 2;
the pin of the comparator U7B 6 is connected with the pin U7A 2, the pin U7B 5 is connected with the pin U7A 3, and the pin U7B 7 is connected with the pin R74 2;
resistor R73 pin is connected with resistor R81 pin, resistor R74 pin is connected with resistor R80 pin;
The triode V82 pin is connected with a V120/V82/V22 network, the V82 pin 3 is connected with a resistor R82 pin 1, and the R82 pin 2 is connected with a DC+25V network; v82, 4 pins are connected with R82 pin and R80 pin 2;
the triode V81 3 is connected with the R81 pin, the V81 pin is connected with the capacitor C83 pin, and the C83 pin 1 is connected with DC 0V. V81, 4 pin connects DC 0V;
the R84 1 pin of the resistor is connected with the V81 pin, the R84 2 pin is connected with the V86 pin 3;
the diode V83 pin is connected with the triode V80 pin, the V83 1 pin and the 2 pin are connected with the R83 pin and the R83 pin 1 pin is connected with DC 0V;
the triode V80 pin is connected with DC+12.4V, the V80 pin is connected with the resistor R80 pin, the V80 pin 2 and the 4 pin are connected with the diode V90 pin 1, and the V90 pin 3 is connected with a V124/V90 network;
the diode V86 2 is connected with the R84 2 pin, and the V86 1 is connected with the capacitor C111 pin;
the pins X1 1 and 2 of the connector are short-circuited, the pin X1 2 is connected with the pin R101 and the pin R102, the pin R101 and the pin R102 are connected with the pin R103 and the pin R103, the pin R103 and the pin R104 2, R104 is connected with R105, R105 is connected with R106, R106 is connected with R107, R107 is connected with R108, R108 is connected with capacitor C100 1, C100 is connected with X1;
resistor R111 pin R106 pin, resistor R112 pin R1111 pin, resistor R113 pin R112 pin, resistor R114 pin R1131 pin, resistor R114 pin R115 pin, resistor R115 pin R1162 pin, resistor R116 pin R117 2 pin, resistor R117 1 pin R1182 pin, resistor R118 pin C111 1 pin, C111 pin R1112 pin;
the resistor R85 pin 2 is connected with the R86 pin 2, and the R85 pin 1 is connected with the R86 pin 1;
the diode V87 3 is connected with the R87 2 pin of the resistor, and the V87 1 pin is connected with DC 0V;
the C87 2 pin of the capacitor is connected with the R87 2 pin, and the C87 1 pin is connected with DC 0V;
the capacitor C88 2 is connected with the R87 2 pin, and the C88 1 is connected with the DC 0V pin.
Referring to fig. 7, the interference filter circuit includes: transistor V91, transistor V95, resistors R90, R91, R94, R98, capacitor C94, capacitor C95;
the triode V91, the resistor R90, the resistor R91 and the resistor R98 form a filter function prohibiting circuit, and when a real IGBT on signal arrives, the filter function is prohibited;
the triode V95, the resistor R94, the capacitor C94 and the capacitor C95 form a filter circuit, the output end of the V94 is pulled down, and the delay of the IGBT on driving signals is controlled.
The resistor R91 2 is connected with the V94/V51 network, the resistor R91 1 is connected with the resistor R98 2, and the resistor R98 1 is connected with the V13/V95 network;
the triode V91 is connected with the R91 pin, the V91 2 pin is connected with the R98 pin, the V91 3 pin is connected with the R90 pin, and the R90 pin is connected with DC 0V;
the triode V95 pin is connected with the R90 pin, the V95 pin is connected with the R94 pin 1, and the R94 pin 2 is connected with the V94/V95 network;
the capacitor C95 pin 2 is connected with the R94 pin 1, and the C95 pin 1 is connected with the V91 pin 2. The capacitor C94 is connected with the C95 pin C2, and the capacitor C94 is connected with the C95 pin C1.
The present invention has been described in terms of the preferred embodiments thereof, and it should be understood by those skilled in the art that various modifications can be made without departing from the principles of the invention, and such modifications should also be considered as being within the scope of the invention.
Claims (5)
1. An IGBT gate driver for a dual slope spike suppression analog circuit, comprising: the device comprises a power supply and protection circuit, an isolation driving circuit, an IGBT overvoltage clamping circuit and an interference filter circuit; wherein, the liquid crystal display device comprises a liquid crystal display device,
the power supply and protection circuit comprises: the power supply circuit converts the input high-frequency alternating current into direct current and outputs DC+ V, DC + V, DC +12.4V and DC-25V power supply; the power supply protection circuit monitors the power supply in real time, and when the power supply is abnormal, the output of an IGBT (insulated gate bipolar transistor) on-driving signal is forbidden, so that the IGBT is always kept in an off state;
the isolation driving circuit receives a light driving signal sent by an upper computer, converts the light driving signal into a +15V and-10V IGBT gate driving signal and inhibits the IGBT gate voltage spike in a double-slope mode;
the IGBT overvoltage clamping circuit judges whether overvoltage conditions exist according to the received upper computer driving signals and the voltage values at two ends of the IGBT; if overvoltage exists, the IGBT is controlled to be turned on slightly, so that the voltage at two ends of the IGBT is reduced, and the breakdown of the IGBT is prevented;
The interference filter circuit filters high-frequency electromagnetic interference to prevent the IGBT from misoperation;
the isolation driving circuit includes: the optical fiber receiver U4, the jumper connector X4, the exclusive-OR gate chip U5, the triodes V50, V51, V13, V120, V121, V124, V125, V126, V127, the voltage stabilizing tubes V10, V11, V12, V23, V93, the diodes V92, V94, V122, V128, V135, and the resistors R31, R40, R41, R50, R51, R52, R53, R95, R96, R97, R120, R121, R124, R125, R126, R127, R128, R135, R136, R139, and the capacitors C12, C61, C96;
the optical fiber receiver U4 converts the optical driving signal sent by the upper computer into an internal control signal, the control signal is amplified by the exclusive-or gate chip U5 and amplified by the triode V50 and then output to the base electrode of the triode V124, and the V124 controls the output of the push-pull amplifying circuits V126, V127, V121 and V125 so as to control the IGBT to turn on the driving signal; meanwhile, the push-pull amplifying circuit realizes the control of the slope of the driving signal; the optical fiber receiver U4, the exclusive-OR gate chip U5, the resistor R41, the resistor R40 and the jumper connector X4 form an optical fiber input circuit, and receive an upper computer control signal; triode V50, resistance R50-R53, form the first-level amplifying circuit, further amplify the control signal, output to protecting and controlling circuit; a third transistor V51 for locking the IGBT opening signal; the diode V92 and the voltage stabilizing tube V93 are used for adjusting the voltage of the control signal;
The voltage stabilizing tube V10, V11, V12 and R31 form a voltage stabilizing reference circuit, a reference potential is provided for the triode V13, the output end of the V136 is connected with the base electrode of the V124, and the push-pull amplifying circuit is controlled to output an IGBT turn-off driving signal; meanwhile, the push-pull amplifying circuit realizes the control of the slope of the driving signal; the triode V13, the resistor R97, the resistor R95, the resistor R96 and the capacitor C96 form a primary IGBT turn-off signal control circuit which is used for delay control of the primary IGBT turn-off signal;
triode V120 is used for low voltage locking control; the diode V122 and the voltage stabilizing tube V123 are used for potential adjustment; the triode V124 and the resistor R124 form an interlocking control circuit which is used for interlocking the driving signals of the IGBT switch; the triodes V126 and V121, the triodes V127 and V125, the resistor R121 and the resistor R125 form a push-pull output and amplification circuit which is used for controlling a driving signal of the two-stage IGBT and realizing a double-slope peak suppression function; diode V128, resistance R126-R128, form IGBT grid current limiting circuit, finish the slope control of the voltage change curve of grid together with push-pull circuit;
diode V135, resistor R139 and indicator lamp H1 form IGBT turn-off output state indication circuit; the resistor R135 and the indicator lamp H2 form an IGBT on output state indicating circuit; resistor R136 is an IGBT gate GE shorting resistor.
2. The IGBT gate driver of the dual slope spike suppression analog circuit of claim 1 wherein the power supply circuit comprises: high-frequency transformer TR1, diodes V1-V4, voltage regulators U1 and U6, resistors R10, R11, R60, and capacitors C1, C2, C10, C60, C61, C80; the high-frequency transformer TR1 realizes electric isolation of a power circuit, magnetic field coupling realizes electric energy transmission, the input voltage is AC 24V, and the output is AC 25V; the diode components V1-V4 form a bridge rectifier circuit and are connected with the output end of the high-frequency transformer TR1, so that alternating current output by the high-frequency transformer TR1 is converted into direct current, and DC+25V and DC-25V are output; the capacitors C1 and C2 form a voltage dividing circuit to provide a 0V reference for the power supply; the voltage regulator U1 and peripheral elements R10, R11, C10 and C80 thereof form a voltage stabilizing circuit and output DC+12.4V; the voltage regulator U6 and peripheral components R60, C60 and C61 thereof form a voltage stabilizing circuit and output DC+20V.
3. The IGBT gate driver of the dual slope spike suppression analog circuit of claim 1 wherein the power supply protection circuit comprises: comparator U3, voltage regulator U2, triodes V31, V33, V54, V56, V21, V22, diodes V30, V32, voltage regulator V20, resistors R30, R31, R32, R33, R34, R35, R36, R37, R38, R54, R56, R57, R20, R21, R22, R23, R24, R25, capacitors C30, C31, C32, C56, C20;
The comparator U3A, the diode V30, the diode V32, the triode V31, the triode V33, the peripheral resistors R30-R35 and the capacitor C30 form a DC+25V and DC-25V power supply monitoring protection circuit; the comparator U3B, the triode V33, the triode V54, peripheral resistors R36-R38 and R54, the capacitors C31 and C32 form a delay control circuit, and the delay control circuit is used for controlling the locking time of the IGBT; triode V56, resistance R57, make up DC +20V power monitoring protective circuit;
the voltage stabilizing tube V20, the resistor R20 and the resistor R21 form a reference voltage circuit, and a reference voltage is provided for the triode V21; the voltage stabilizer U2, the triode V21, the triode V22 and the resistors R21-R25 form a low-voltage locking circuit, and when the voltage is low, an IGBT locking signal is output.
4. The IGBT gate driver of the dual slope spike suppression analog circuit of claim 1 wherein the IGBT over voltage clamp circuit comprises: comparator U7, triodes V80-V82, diode V70, diode V83, diode V90, diode V86, diode V87, resistors R70-R74, R80-R87, R101-R108, R111-R118, and capacitors C70, C71, C83, C88, C100, C111;
the IGBT overvoltage clamping action speed is related to the IGBT state and is divided into an IGBT working state and an idle state; in the IGBT working state, the clamp protection action speed is faster; the diode V70, the resistor R70 and the capacitor C71 form a delay circuit, so that the overvoltage clamping circuit is delayed to enter an IGBT idle clamping protection state;
The comparator U7, the resistors R72 and R71 form an IGBT working state detection circuit, and the resistors R72 and R71 provide reference voltage for the U7; the capacitor C71 is a U7 power supply filter capacitor;
triode V82, resistor R73, resistor R72, resistor R80 and resistor R81 form a pull-up circuit of the U7 output end;
the triode V81, the resistor R84 and the resistor R83 form an action circuit of over-voltage clamping; when overvoltage occurs, the IGBT micro-turn-on signal is forcedly output;
the triode V80, the diode V83 and the diode V90 form an overvoltage clamping output circuit to control the voltage of the IGBT GE pin;
the diode V86, the diode V87, the resistor R85, the resistor R87, the resistors R111-R118, the resistors R101-R108, the capacitor C88, the capacitor C111 and the capacitor C100 form an IGBT C pin voltage acquisition circuit; diodes V86, V87 are used for protection, resistors R85, R87 are pull-down resistors.
5. The IGBT gate driver of the dual slope spike suppression analog circuit of claim 1 wherein the interference filter circuit comprises: transistor V91, transistor V95, resistors R90, R91, R94, R98, capacitor C94, capacitor C95;
the triode V91, the resistor R90, the resistor R91 and the resistor R98 form a filter function prohibiting circuit, and when an IGBT on signal arrives, the filter function is prohibited;
The triode V95, the resistor R94, the capacitor C94 and the capacitor C95 form a filter circuit, the output end of the V94 is pulled down, and the delay of the IGBT on driving signals is controlled.
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| CN1056763A (en) * | 1990-05-23 | 1991-12-04 | 三星电子株式会社 | The sense amplifier driving circuit that is used for semiconductor memory |
| TW200719567A (en) * | 2005-11-04 | 2007-05-16 | Chroma Ate Inc | Driving method and circuit of power MOS |
| WO2011024591A1 (en) * | 2009-08-27 | 2011-03-03 | 富士電機ホールディングス株式会社 | Semiconductor drive device |
| CN106849923A (en) * | 2016-12-23 | 2017-06-13 | 电子科技大学 | A kind of IGBT drive circuit |
| CN109450230A (en) * | 2018-10-24 | 2019-03-08 | 南京轨道交通系统工程有限公司 | A kind of IGBT gate drivers based on analog circuit |
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|---|---|---|---|---|
| CN1056763A (en) * | 1990-05-23 | 1991-12-04 | 三星电子株式会社 | The sense amplifier driving circuit that is used for semiconductor memory |
| TW200719567A (en) * | 2005-11-04 | 2007-05-16 | Chroma Ate Inc | Driving method and circuit of power MOS |
| WO2011024591A1 (en) * | 2009-08-27 | 2011-03-03 | 富士電機ホールディングス株式会社 | Semiconductor drive device |
| CN106849923A (en) * | 2016-12-23 | 2017-06-13 | 电子科技大学 | A kind of IGBT drive circuit |
| CN109450230A (en) * | 2018-10-24 | 2019-03-08 | 南京轨道交通系统工程有限公司 | A kind of IGBT gate drivers based on analog circuit |
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