CN110992239B

CN110992239B - Image time domain filtering and displaying method based on single DDR3 chip

Info

Publication number: CN110992239B
Application number: CN201911111830.0A
Authority: CN
Inventors: 孔冬; 毛义伟; 田立坤
Original assignee: Luoyang Institute of Electro Optical Equipment AVIC
Current assignee: Luoyang Institute of Electro Optical Equipment AVIC
Priority date: 2019-11-14
Filing date: 2019-11-14
Publication date: 2023-03-24
Anticipated expiration: 2039-11-14
Also published as: CN110992239A

Abstract

The invention relates to a method for filtering and displaying an image time domain based on a single DDR3 chip.A time domain filtering module, two paths of image direct memory access IP core modules and an access interface IP core module are arranged in an FPGA; the single DDR3 chip is connected with the access interface IP core module, and the DVI interface chip is connected with the second image direct memory access IP core module; the invention uses a single DDR3 chip to simultaneously cache and read and write two paths of image data, thereby realizing the functions of image time domain filtering and display. The method occupies less FPGA resources, has low power consumption, is suitable for processing high-frame-frequency and high-resolution images, has high operation speed and high real-time performance, and is easy to realize by the FPGA.

Description

Image time domain filtering and displaying method based on single DDR3 chip

Technical Field

The invention belongs to the field of image processing, and relates to an image time domain filtering and displaying method based on a single DDR3 chip.

Background

The current common image time domain filtering and displaying method uses two dual-port RAM chips which are respectively used for the cache reading and writing of two paths of images. However, with the continuous improvement of image frame frequency and resolution, the read-write speed and the stored data amount of the dual-port RAM chip cannot meet the requirements.

The DDR3 chip is a third generation double-rate synchronous dynamic random access memory, and has higher working frequency, faster access speed, lower power consumption and larger memory capacity compared with a double-port RAM chip.

In order to solve the problems of time domain filtering and display of high frame frequency and high resolution images, the image time domain filtering and display method based on the single DDR3 chip is particularly provided, the single DDR3 chip is used for caching and reading of two paths of image data simultaneously, the method occupies few FPGA resources, is high in operation speed and good in real-time performance, is easy to realize by an FPGA, reduces the power consumption of a circuit board and improves the integration level of the circuit board.

Disclosure of Invention

Technical problem to be solved

In order to avoid the defects of the prior art, the invention provides an image time domain filtering and displaying method based on a single DDR3 chip, which can meet the requirements of high frame frequency and high resolution image time domain filtering and displaying.

Technical scheme

A method for filtering and displaying an image time domain based on a single DDR3 chip is characterized in that: a time domain filtering module, two paths of image direct memory access IP core modules and an access interface IP core module in an FPGA are adopted; the single DDR3 chip is connected with the access interface IP core module, and the DVI interface chip is connected with the second image direct memory access IP core module; the time domain filtering and displaying steps are as follows:

step 1: the high frame frequency and high resolution image output by the front-end image sensor is sent to an FPGA chip, the current frame image data is divided into 2 paths in the FPGA chip, wherein 1 path is sent to a time domain filter module 1, and the other 1 path is sent to an image direct memory access IP core 2 and written into a DDR3 chip 5 through an access interface IP core 4 for caching;

and 2, step: the first image direct memory access IP core 2 reads the cached previous frame image data from the DDR3 chip 5 through the access interface IP core 4 and sends the previous frame image data to the time domain filtering module 1; the image filtering of the current frame image data and the previous frame image data is carried out in a time domain filtering module 1, and the time domain noise of the current frame image is filtered;

and step 3: the time domain filtering module 1 outputs the filtered image to a second image direct memory access IP core 3, and writes the second image into a DDR3 chip 5 through an access interface IP core 4 for caching;

and 4, step 4: the second image direct memory access IP core 3 reads the cached filtered image data from the DDR3 chip 5 through the access interface IP core 4, generates a DVI standard time sequence image and sends the DVI standard time sequence image to the DVI interface chip 6 for DVI image display.

Advantageous effects

The invention provides a method for filtering and displaying an image time domain based on a single DDR3 chip.A time domain filtering module, two paths of image direct memory access IP core modules and an access interface IP core module are arranged in an FPGA; the single DDR3 chip is connected with the access interface IP core module, and the DVI interface chip is connected with the second image direct memory access IP core module; the invention uses a single DDR3 chip to simultaneously cache and read and write two paths of image data, thereby realizing the functions of image time domain filtering and display. The method occupies less FPGA resources, has low power consumption, is suitable for processing high-frame-frequency and high-resolution images, has high operation speed and high real-time performance, and is easy to realize by the FPGA.

Drawings

FIG. 1 is a schematic diagram of the present invention

FIG. 2 is a schematic diagram of an embodiment

Detailed Description

The invention will now be further described with reference to the following examples and drawings:

in the embodiment, the image sensor adopts a GSENSE2011BSC color photosensitive chip of Changchun Chang light core photoelectric company, a 24-bit color image with the image resolution of 1920 multiplied by 1080, an FPGA chip adopts XC7A200T-2SBG484I of Xilinx company, a DDR3 chip adopts MT41J128M8 of Meiguan company, and a DVI interface chip adopts a TFP410 chip of TI company.

The connection relationship is as follows: a time domain filtering module, two paths of image direct memory access IP core modules and an access interface IP core module in the FPGA are respectively connected with a single DDR3 chip and a DVI interface chip; two paths of image direct memory access IP core modules in the FPGA are connected with an access interface IP core module, and the output of a front-end image sensor chip is connected with a time domain filtering module in the FPGA and a first image direct memory access IP core module; the output of the first image direct memory access IP core module is connected with the time domain filtering module; the output of the time domain filtering module is connected with the second image direct memory access IP core module, and the output of the second image direct memory access IP core module is connected with the DVI interface chip.

The image direct memory access IP core module adopts two VDMA IP cores of an FPGA chip.

The access interface IP core module adopts an MIG IP core of an FPGA chip.

The method comprises the following implementation flows:

step 1: the original high-frame-frequency high-resolution image output by the front-end image sensor chip is transmitted to the FPGA chip, the image is divided into 2 paths in the FPGA chip, wherein 1 path is sent to a time domain filtering module 1, and the other 1 path is sent to a first VDMA IP core and written into a DDR3 chip through an MIG IP core for caching;

step 2: reading the cached previous frame of image data from the DDR3 chip through a first VDMA IP core and an MIG IP core of the FPGA chip, carrying out image filtering operation on the current frame of image data and the previous frame of image data in a time domain filtering module, and filtering out time domain noise of the current frame of image;

and step 3: the filtered image output by the time domain filtering module is written into a DDR3 chip through a second VDMA IP core and an MIG IP core for caching;

and 4, step 4: and reading the cached filtered image data from the DDR3 chip (5) through a second VDMA IP core and an MIG IP core of the FPGA chip, generating a DVI standard time sequence image, and sending the DVI standard time sequence image to a DVI interface chip for DVI image display.

Claims

1. A method for filtering and displaying an image time domain based on a single DDR3 chip is characterized in that: a time domain filtering module, two paths of image direct memory access IP core modules and an access interface IP core module in an FPGA are adopted; the single DDR3 chip is connected with the access interface IP core module, and the DVI interface chip is connected with the second image direct memory access IP core module; the time domain filtering and displaying steps are as follows:

step 1: the high-frame-frequency high-resolution image output by the front-end image sensor is sent to an FPGA chip, the image data of the current frame is divided into 2 paths in the FPGA chip, wherein 1 path is sent to a time domain filtering module (1), and the other 1 path is sent to an image direct memory access IP core (2) and written into a DDR3 chip (5) through an access interface IP core (4) for caching;

and 2, step: the first image direct memory access IP core (2) reads cached previous frame image data from the DDR3 chip (5) through the access interface IP core (4) and sends the previous frame image data to the time domain filtering module (1); carrying out image filtering on the current frame image data and the previous frame image data in a time domain filtering module (1) to filter out time domain noise of the current frame image;

and step 3: the time domain filtering module (1) outputs the filtered image to a second image direct memory access IP core (3), and then writes the image into a DDR3 chip (5) through an access interface IP core (4) for caching;

and 4, step 4: the second image direct memory access IP core (3) reads the cached filtered image data from the DDR3 chip (5) through the access interface IP core (4), generates a DVI standard time sequence image and sends the DVI standard time sequence image to the DVI interface chip (6) for DVI image display.

2. The method for image temporal filtering and display based on the single DDR3 chip as claimed in claim 1, wherein: the FPGA adopts XC7A200T-2SBG484I of Xilinx corporation.

3. The method for image temporal filtering and display based on the single DDR3 chip as claimed in claim 1, wherein: the DDR3 chip selects MT41J128M8 from Meiguang company.

4. The method for image temporal filtering and display based on the single DDR3 chip as claimed in claim 1, wherein: the DVI interface chip is a TFP410 chip of TI company.