CN103051829A - Noise reduction system and noise reduction method for original image data based on FPGA (Field Programmable Gate Array) platform - Google Patents

Noise reduction system and noise reduction method for original image data based on FPGA (Field Programmable Gate Array) platform Download PDF

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Publication number
CN103051829A
CN103051829A CN2012105269852A CN201210526985A CN103051829A CN 103051829 A CN103051829 A CN 103051829A CN 2012105269852 A CN2012105269852 A CN 2012105269852A CN 201210526985 A CN201210526985 A CN 201210526985A CN 103051829 A CN103051829 A CN 103051829A
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data
module
noise
noise reduction
image data
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CN103051829B (en
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戴林
唐波
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Tiandi Weiye Technology Co., Ltd.
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Tianjin Tiandy Digital Technology Co Ltd
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Abstract

The invention relates to a noise reduction system and a noise reduction method for original image data based on an FPGA (Field Programmable Gate Array) platform. The noise reduction system comprises a template generating module, a mean filtering module, a data analysis selecting module and a data output module which are connected in turn, wherein five FIFO (First In, First Out) storages are arranged in the template generating module; the mean filtering module is used for performing mean filtering treatment on the original image data and the noise variance; the data analysis selecting module is used for calculating the scope of the image signal in each step length according to the image data and the values of the corresponding noise in different step lengths; and selecting the optimal step length according to the scope. According to the invention, a mean filter is used for filtering the noise, the mean values in different step lengths are calculated, the noise information is analyzed and a mean filtering result in optimal step length is adaptively selected. The noise reduction system provided by the invention is applied to the noise reduction for real-time video original data and has the characteristics of low complexity and excellent noise reduction property.

Description

Raw image data noise reduction system and noise-reduction method based on the FPGA platform
Technical field
The present invention relates to the technical field that video image is processed, is a kind of raw image data noise reduction system and noise-reduction method based on the FPGA platform specifically.
Background technology
Gathering the noise of sneaking in the picture signal process at imageing sensor mainly is Gaussian noise and salt-pepper noise, wherein Gaussian noise becomes Gaussian Profile, mainly produce by resistive components and parts are inner, and produce poisson noise in the white point noise on the salt-pepper noise picture black that mainly to be the image cutting cause or the photoelectric conversion process.The main target of video image denoising is filtering noise wherein, has kept as far as possible detailed information simultaneously, and reduces because the vision that filtering is introduced degrades in the video image of requirement behind noise reduction.
The noise of video image denoising technology in not only can the filtering video image, improve the video image subjective visual quality do, and significant for subsequent treatment tasks such as compressed encoding, target recognition and tracking, frame frequency liftings.Existing video image denoising algorithm can be divided into two classes: early stage pixel domain noise reduction algorithm and Transformation Domain noise reduction algorithm in recent years.
According to the filter range of filter, filtering algorithm when the pixel domain noise reduction algorithm can be divided into time-domain filtering algorithm and sky.The time-domain filtering algorithm utilizes correlation on the video image time domain to suppress noise, and based on motion estimation/motion compensation process obtains time domain prediction usually; Filtering algorithm then is the space-time correlation filtering noise that utilizes in the video image three dimensions when empty.The major defect of pixel domain noise reduction algorithm is exactly to introduce easily in the video image behind noise reduction that time domain degrades, the spatial domain such as excessively level and smooth degrades, and does not up to the present also have a kind of other noise reduction algorithm of multiple noise level that is fit to.In addition, many employing estimation are obtained the relevant information on the time domain in the pixel domain noise reduction algorithm, but the existence of noise affects the accuracy of estimation easily, thereby reduce anti-acoustic capability.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of raw image data noise reduction system and noise-reduction method based on the FPGA platform.
The technical scheme that the present invention takes for the technical problem that exists in the solution known technology is:
Raw image data noise reduction system based on the FPGA platform of the present invention is characterized in that, comprising: module and data outputting module are selected in template generation module, mean filter module, data analysis, and above-mentioned each sequence of modules is connected; 5 FIFO memories are set in the template generation module, are respectively FIFO1, FIFO2, FIFO3, FIFO4 and FIFO5; The mean filter module is carried out the mean filter processing to raw image data, noise variance, and its Output rusults is selected the input of module as data analysis; Data analysis selects module to be connected between mean filter module and the data outputting module.
Raw image data noise-reduction method based on the FPGA platform of the present invention may further comprise the steps:
A, vedio data is input to the template generation module, the neighborhood template of use 1 * 5 is processed the capable data of video image, respectively odd-numbered line vedio data and even number line vedio data are processed, result is cached to 5 FIFO, each FIFO can the buffer memory data line, when the 5th row data arrive, 5 FIFO just all buffer memory data line, among the FIFO1 buffer memory the 1st row data, among the FIFO2 buffer memory the 2nd row data, the FIFO3 buffer memory the 3rd row data, the FIFO4 buffer memory the 4th row data, among the FIFO5 buffer memory the 5th row data, calculate corresponding noise variance according to the amplitude of input noise size;
B, the 5 row raw video image data that the template generation module produced by the mean filter module and noise variance carry out mean filter to be processed, calculate the average of raw video image data under 1,1 * 2,3 * 4 three class step-lengths, and each self-corresponding noise variance average, export the result to data analysis and select module;
C: calculate the scope of each step-length hypograph signal according to vedio data and the value of corresponding noise under different step-lengths, select optimum step-length according to this scope;
D, by data outputting module output data.
Advantage and good effect that the present invention has are:
In the raw image data noise reduction system and noise-reduction method based on the FPGA platform of the present invention, adopt mean filter to come filtering noise, calculate the average under the different step-lengths, by analyzing noise information, the mean filter result of adaptively selected optimal step size.The present invention is applied to the noise reduction of real-time video initial data, has the advantages that implementation complexity is low, anti-acoustic capability is good.
Description of drawings
Fig. 1 is the schematic diagram of the raw image data noise reduction system based on the FPGA platform of the present invention.
Embodiment
The present invention will be described in detail referring to drawings and Examples.
Fig. 1 is the schematic diagram of the raw image data noise reduction system based on the FPGA platform of the present invention.
As shown in Figure 1, the raw image data noise reduction system based on the FPGA platform of the present invention is characterized in that, comprising: module and data outputting module are selected in template generation module, mean filter module, data analysis, and above-mentioned each sequence of modules is connected; 5 FIFO memories are set in the template generation module, are respectively FIFO1, FIFO2, FIFO3, FIFO4 and FIFO5; The mean filter module is carried out the mean filter processing to raw image data, noise variance, and its Output rusults is selected the input of module as data analysis; Data analysis selects module to be connected between mean filter module and the data outputting module.
The basic principle of mean filter is: the initial value of using the average replacement A of point adjoining on certain some A space.Adopt the mean filter of different step-lengths among the present invention, be respectively 1,1 * 2,3 * 4, used this three classes step-length, can effectively realize the primary Calculation of noise reduction.
Raw image data noise-reduction method based on the FPGA platform of the present invention may further comprise the steps:
A, vedio data is input to the template generation module, the neighborhood template of use 1 * 5 is processed the capable data of video image, respectively odd-numbered line vedio data and even number line vedio data are processed, result is cached to 5 FIFO, each FIFO can the buffer memory data line, when the 5th row data arrive, 5 FIFO just all buffer memory data line, among the FIFO1 buffer memory the 1st row data, among the FIFO2 buffer memory the 2nd row data, the FIFO3 buffer memory the 3rd row data, the FIFO4 buffer memory the 4th row data, among the FIFO5 buffer memory the 5th row data, calculate corresponding noise variance according to the amplitude of input noise size;
B, the 5 row raw video image data that the template generation module produced by the mean filter module and noise variance carry out mean filter to be processed, calculate the average of raw video image data under 1,1 * 2,3 * 4 three class step-lengths, and each self-corresponding noise variance average, export the result to data analysis and select module;
C: calculate the scope of each step-length hypograph signal according to vedio data and the value of corresponding noise under different step-lengths, select optimum step-length according to this scope;
D, by data outputting module output data.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, although the present invention with preferred embodiment openly as above, yet, be not to limit the present invention, any those skilled in the art, within not breaking away from the technical solution of the present invention scope, certainly can utilize the technology contents of announcement to make a little change or modification, become the equivalent embodiment of equivalent variations, be the content that does not break away from technical solution of the present invention in every case, any simple modification that foundation technical spirit of the present invention is done above embodiment, equivalent variations and modification all belong in the scope of technical solution of the present invention.

Claims (2)

1. the raw image data noise reduction system based on the FPGA platform is characterized in that, comprising: module and data outputting module are selected in template generation module, mean filter module, data analysis, and above-mentioned each sequence of modules is connected; 5 FIFO memories are set in the template generation module, are respectively FIFO1, FIFO2, FIFO3, FIFO4 and FIFO5; The mean filter module is carried out the mean filter processing to raw image data, noise variance, and its Output rusults is selected the input of module as data analysis; Data analysis selects module to be connected between mean filter module and the data outputting module.
2. initial data noise-reduction method based on the raw image data noise reduction system based on the FPGA platform claimed in claim 1 may further comprise the steps:
A, vedio data is input to the template generation module, the neighborhood template of use 1 * 5 is processed the capable data of video image, respectively odd-numbered line vedio data and even number line vedio data are processed, result is cached to 5 FIFO, each FIFO can the buffer memory data line, when the 5th row data arrive, 5 FIFO just all buffer memory data line, among the FIFO1 buffer memory the 1st row data, among the FIFO2 buffer memory the 2nd row data, the FIFO3 buffer memory the 3rd row data, the FIFO4 buffer memory the 4th row data, among the FIFO5 buffer memory the 5th row data, calculate corresponding noise variance according to the amplitude of input noise size;
B, the 5 row raw video image data that the template generation module produced by the mean filter module and noise variance carry out mean filter to be processed, calculate the average of raw video image data under 1,1 * 2,3 * 4 three class step-lengths, and each self-corresponding noise variance average, export the result to data analysis and select module;
C: calculate the scope of each step-length hypograph signal according to vedio data and the value of corresponding noise under different step-lengths, select optimum step-length according to this scope;
D, by data outputting module output data.
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