CN109544469A - A kind of discrete Kalman's self-adapting image denoising system based on FPGA - Google Patents
A kind of discrete Kalman's self-adapting image denoising system based on FPGA Download PDFInfo
- Publication number
- CN109544469A CN109544469A CN201811317274.8A CN201811317274A CN109544469A CN 109544469 A CN109544469 A CN 109544469A CN 201811317274 A CN201811317274 A CN 201811317274A CN 109544469 A CN109544469 A CN 109544469A
- Authority
- CN
- China
- Prior art keywords
- module
- image
- data
- fpga
- kalman
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001914 filtration Methods 0.000 claims abstract description 42
- 238000011946 reduction process Methods 0.000 claims abstract description 6
- 238000004364 calculation method Methods 0.000 claims description 12
- 230000009467 reduction Effects 0.000 claims description 12
- 238000004891 communication Methods 0.000 claims description 5
- 238000012545 processing Methods 0.000 abstract description 26
- 238000013461 design Methods 0.000 abstract description 8
- 238000005265 energy consumption Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 9
- 238000004422 calculation algorithm Methods 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 241001269238 Data Species 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T5/00—Image enhancement or restoration
- G06T5/70—Denoising; Smoothing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2200/00—Indexing scheme for image data processing or generation, in general
- G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/10—Image acquisition modality
- G06T2207/10004—Still image; Photographic image
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/20—Special algorithmic details
- G06T2207/20076—Probabilistic image processing
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Image Processing (AREA)
Abstract
The present invention discloses a kind of discrete Kalman's self-adapting image denoising system based on FPGA, including Kalman Filtering for Discrete module, image data input module, data memory module, clock frequency division module and the data outputting module constructed based on FPGA processor, image data input module will be in the image pixel data deposit data memory module of acquisition, clock frequency division module realizes timing control, after Kalman Filtering for Discrete module carries out noise reduction process to the image in data memory module, image output is carried out by data outputting module.Such system cost is lower, and image processing speed is fast, and performance with higher and lower energy consumption can satisfy the complexity and real-time of design, reduce complexity when hardware design, has the advantages that operation is easy, is applied widely.
Description
Technical field
The image noise reduction system based on FPGA hardware platform that the present invention relates to a kind of, in particular to it is a kind of to be based on FPGA platform
A kind of discrete Kalman's Recursive Filtering system built.
Background technique
With being constantly progressive for information digitalization processing technique development, image is more and more extensive as the medium that information is transmitted
Ground is applied in the every field of study, work, scientific research and life.Among continuous application, people are for the clear of image
Degree has higher requirement, also higher and higher for the imaging requirements of system, but due to the complexity of imaging circumstances condition, number
Image inevitably will receive the interference of noise signal in acquisition, cause the clarity of digital picture to be affected, so as to cause figure
Image quality quantitative change is poor, it is therefore desirable to which the noise for reducing image improves the clarity of image, embodies image information more truly.
A variety of more common Image denoising algorithms, such as median filtering algorithm, wavelet analysis method are proposed both at home and abroad at present, it is wide
General application, but still have improved space.
Due to the continuous development of image processing techniques, the requirement of people's digital image processing technology is also higher and higher.Mesh
Before, the related system for carrying out image procossing is very big for the demand of data processing amount, and requires cracking processing speed, so greatly
Algorithm of the majority for image procossing can only go operation using software, but cost needed for software environment is too high, and scale is very
Greatly, so that realized by operation platform it is more difficult, so being badly in need of that a kind of cost is lower and image processing speed is fast and can guarantee good
The image noise reduction scheme based on hardware platform that filters out of picture noise, thus this case generates.
Summary of the invention
The purpose of the present invention is to provide a kind of discrete Kalman's self-adapting image denoising system based on FPGA, make
Valence is lower, and image processing speed is fast, performance with higher and lower energy consumption, can satisfy design complexity and in real time
Property, complexity when hardware design is reduced, has the advantages that operation is easy, is applied widely.
In order to achieve the above objectives, solution of the invention is:
A kind of discrete Kalman's self-adapting image denoising system based on FPGA, including based on FPGA processor construct from
Dissipate Kalman filtering module, image data input module, data memory module, clock frequency division module and data outputting module, figure
As data input module is by the image pixel data of acquisition deposit data memory module, clock frequency division module realizes timing control
System is carried out after Kalman Filtering for Discrete module carries out noise reduction process to the image in data memory module by data outputting module
Image output.
The course of work of above-mentioned image data input module is: the image for wanting noise reduction read in by MATLAB, and
Image pixel information is generated as .mif formatted file, image data is stored by the memory ROM module in FPGA later.
The course of work of above-mentioned clock frequency division module is: frequency dividing setting is carried out to externally input clock, for data
It is periodically read, and carries out the recursive calculation of discrete Kalman according to the period.
Above-mentioned Kalman filtering module includes filter module and kalman gain calculates and filtering parameter modified module.
Above-mentioned data outputting module task is using the serial communication between FPGA and computer, by Kalman Filtering for Discrete module
Filtered image data is sent to computer, and generates .txt file；Then MATLAB program is utilized, by the figure in txt file
As data are read out, to generate filtered image result.
The present invention will carry out the Algorithm mapping of image denoising based on the end PC to FPGA hardware platform using Kalman model,
The high speed processing for realizing image noise reduction process, to improve the computational efficiency of image denoising；FPGA does not use operating system, institute
The problem of mutually occupying to obtain risk not have task, avoiding some stability aspects, and its requirement to external environment
Nor very high.
After adopting the above scheme, the invention has the advantages that:
(1) it since FPGA has the characteristics that parallel processing, is greatly improved for the processing speed of service of algorithm, this
Two ROM memory modules are had invoked to FPGA in design, a module stores the pixel data of image, another ROM module
The parameters such as the gain, the estimated value that generate when then storing Kalman filtering module arithmetic, this more improves arithmetic speed；
(2) real-time pipeline operation can be carried out based on FPGA, realizes the processing operation of multitask, can reach highest real-time
Property, when being filtered noise reduction to dynamic image, it can be identified in real time, read in data and carry out calculation process, this will
Greatly improve the efficiency of work；
(3) high speed processing of image noise reduction process is realized by the design, and this system hardware itself has simply
Structure also has versatility, while the internal logic circuit by changing FPGA, energy for the otherwise processing of image
Realize the processing requirement different based on Kalman filtering algorithm, this makes Kalman's image noise reduction system based on FPGA, is locating
Reason aspect has greater flexibility, is with a wide range of applications.
Detailed description of the invention
Fig. 1 is structural block diagram of the invention；
Fig. 2 is that MATLAB generates .mif document image figure；
Fig. 3 is that image slices sketch map is shown in FPGA；
Fig. 4 is Kalman filtering module component figure；
Fig. 5 is Kalman filtering module flow diagram；
Fig. 6 is Kalman filtering modular simulation timing diagram；
Fig. 7 is serial communication protocol figure；
Fig. 8 is the filter result figure based on FPGA.
Specific embodiment
Below with reference to attached drawing, technical solution of the present invention and beneficial effect are described in detail.
As shown in Figure 1, the present invention provides a kind of discrete Kalman's self-adapting image denoising system based on FPGA, including base
It is protected in the Kalman Filtering for Discrete module of FPGA processing construction, the image data input module of image information collecting, sample image
The data that image is called after the clock frequency division module and noise reduction of the data memory module, the use of internal system timing control deposited
Output module is introduced separately below.
The main task of FPGA processor is to make FPGA under the control of timing by designing suitable timing, to having given birth to
At image pixel data deposit ROM module in；The image pixel information for being stored in register module is adjusted again later
It is passed to Kalman filtering module with reading, and by data, Kalman filtering processing is carried out, exports filtered data, finally
Picture after showing filtering noise reduction on computers.
Described image data input module is mainly based upon the filtering noise reduction that main direction of studying of the present invention is image, figure
Picture data are fixed value in the calculation process stage, therefore in terms of the acquisition of image data, directly read image slices using FPGA
The mode of the data such as element.Specific method is to be read in by MATLAB to the image for wanting noise reduction, and image pixel information is given birth to
As .mif formatted file, image data is stored by the memory ROM module in the module of the ready-made offer of FPGA later.Due to
Depth, the bit wide of ROM module etc. are restricted, so in mif paper formulation it is noted that the size to image is adjusted, so that
When FPGA handles image later, the reading of data will not be caused to lack because data are overflowed, to reduce
The effect of filtering processing；Later again by FPGA to the calling of ROM module, the extraction of data is carried out.When reading data,
FPGA each period will be updated once, so that data be allowed successively to flow out one by one, carry out the processing of next step in filter module
Operation.When storing pixel, the information such as parameter according to the size of image pixel data so that it is determined that register number number, such as
The .mif file that MATLAB shown in Fig. 2 is generated, the image that the present embodiment selection is filtered is gray level image, pixel data bits
8 (due to being gray level image, it is not absolutely required to 16 data), tonal range is 0-255, and image size is
260*195, data are shown as hexadecimal.And Fig. 3 is shown image data in FPGA, number is image pixel in figure
Binary representation, since requirement to data is generally binary form when handling data in FPGA, therefore here shown as two
Binary form.When program later reads data, then the reading of data, such as first number are carried out from first address of addr
According to being 1100000000, it is passed to filter module and carries out the processing of data.Then after next cycle starts, the is read
Pixel value in two addresses, then carry out operation.And after all data have been read, pointer can then be directed toward first again
A address.
The clock frequency division module main task is to carry out frequency dividing setting to externally input clock, so as to obtain
Clock required for AD control conversion module and Kalman filtering module in FPGA system.This project adopts image pixel value
Collect the mode directly read, and AD conversion module is not used, so the clock that frequency dividing obtains then is used to carry out periodically data
Reading, and carry out according to the period recursive calculation of discrete Kalman.
The Kalman filtering module, the as design of Kalman filter are in whole image noise reduction process module
Center portion point.The module is broadly divided into filter module and kalman gain calculates and filtering parameter modified module.Kalman filter
Design core be 5 filtering equations in filtering algorithm.It is addition subtraction multiplication and division arithmetic used in filtering equations, but same
When be not only plus and minus calculation directly carried out to data, but the value of parameter and each register is carried out to be converted to floating number, be become
For the addition subtraction multiplication and division operation to floating number, so filter module mainly has adder, multiplier, divider here.It is being transported
Related data is put into being further processed for the pending datas such as register after calculation, the filter module emulation element figure is as shown in Figure 4.
Input clock in Fig. 4, outside clk expression；Reset is system reset input；In is indicated from ROM module to card
The data output of Kalman Filtering module, but it is also the input port of the original digital image data of Kalman filtering module；Randn table
Show random number series, since number is random distribution, therefore the noise signal information instead of image can be used to；True is used to table
Show the true value of image data after noise is added, value can be expressed as true=randn+in；Ob is the measured value of module；
Out is that the final optimal estimated value of filter module and final data export result.
Also, as shown in Figure 4, the digit of output port is different, causes such the reason is that Kalman in order to prevent
Optimal estimation value generates overflow error.The digit of estimated value can make arithmetic speed reduce too much, and digit will make very little
The digit of optimal estimation value generates spilling more than setting digit, so that error is generated, so that filter effect is deteriorated.So estimation
The digit of value will take a suitable value.Data can be reduced to multiple appropriate here, so that last output valve will not produce
It is raw to overflow.And in FPGA, the mode of diminution is to move to left the binary representation number of data, and zero padding.It will in the present embodiment
Data reduce 8 times, move to left 3 according to binary representation, cause digit three more, therefore the delivery outlet digit of out and true
Setting is three more, is [0:10].
Fig. 5 be Kalman filtering flow chart, in FPGA program first to each port, operation when using the parameters arrived into
Row definition statement, includes for data input port, the statement of clock input port, the statement and data of each register port here
The definition of output port is stated.Since image data is deposited in ROM module, each period once calls ROM, reads
One of data carry out next filtering operation, therefore the number of recursive operation is arranged according to this, so that being deposited in ROM
In all image datas outflow, and Kalman filtering module carry out calculation processing.Recurrence number is judged, when
When recurrence number is lower than setting value, then calculation processing is filtered；If being higher than setting value, illustrate that image data is all passed through
At this moment calculation process terminates operation, and carry out the data output step of next step.By using quartus and modelsim etc.
Simulation software carries out simulating, verifying to Kalman filtering module, obtains modular simulation timing diagram, as shown in Figure 6.
The period it will be set as 100ps in the present embodiment, it can be seen from time stimulatiom figure as 100ps, rising edge clock
Triggering, Kalman filtering module are started to work, while the port the in periodically called data from ROM, and carry out the reading of data
It takes, first numerical value is 11000000, identical as the data that first address in .mif file is stored.The port true output simultaneously
After the actual value for the Randn for serving as noise is added, indicate that the image data after noise is added, ob port is that output filter is surveyed
Amount adds the image data value after making an uproar, and the port out outputs and exporting Kalman's optimal estimation value after filtering processing, that is, locates
Data value after reason.It can reflect out from figure, due to it joined random noise after, the value of measurement changes, and represents and adds
Noise information is entered.And after filtering, data change compared with the value that noise is added, and illustrate to be filtered.
The data outputting module task mainly after data carry out calculation process by Kalman filtering module, utilizes FPGA
Filtered image data is sent to computer, and generates .txt file by the serial communication between computer.Finally utilize
Image data in txt file is read out by MATLAB program, to generate filtered image result.As shown in fig. 7,
Serial port protocol starts the start bit triggered for low level, controls communication of the data between hardware and computer.Eight are number later
According to position, the data type of typical hardware calculation process is binary system, and eight bit data here is also binary type.Even-odd check
Position be for transmission data carry out error detection, this project data transmission do not need using.It is finally stop bit, represents number
According to transmission terminate.
Here the main start bit of the transmission of data and the periodically variable level triggers of stop bit control data transmission, often
A transmission period eight bit data is sent to computer terminal port by FPGA.Later by serial ports transmitting software to the image pixel value shape of transmission
File is read out at txt file, then by MATLAB program, image is ultimately formed and is shown, as shown in Figure 8.
In conclusion a kind of discrete Kalman's self-adapting image denoising system based on FPGA of the present invention, practicability is high, excellent
Point protrusion compensates for the domestic disadvantage not high in image noise reduction field computational efficiency now, and this system hardware itself has letter
Single structure also has versatility for the otherwise processing of image, passes through simultaneously without carrying out a large amount of cable wiring manufacture
The internal logic circuit for changing FPGA, can be achieved with the processing requirement different based on Kalman filtering algorithm, this to be based on
Kalman's image noise reduction system of FPGA has greater flexibility and feasibility in terms of processing, has a wide range of applications valence
Value.
The above described is only a preferred embodiment of the present invention, be not intended to limit the present invention in any form, though
So the present invention has been disclosed as a preferred embodiment, and however, it is not intended to limit the invention, any technology people for being familiar with this profession
Member, without departing from the scope of the present invention, when the technology contents using the disclosure above are modified or are modified
For the equivalent embodiment of equivalent variations, but anything that does not depart from the technical scheme of the invention content, according to the technical essence of the invention
Any simple modification, equivalent change and modification to the above embodiments, still falls within the range of technical solution of the present invention
It is interior.
Claims (5)
1. a kind of discrete Kalman's self-adapting image denoising system based on FPGA, it is characterised in that: including being handled based on FPGA
Kalman Filtering for Discrete module, image data input module, data memory module, clock frequency division module and the data that device constructs are defeated
Module out, for image data input module by the image pixel data deposit data memory module of acquisition, clock frequency division module is real
Existing timing control is exported after Kalman Filtering for Discrete module carries out noise reduction process to the image in data memory module by data
Module carries out image output.
2. a kind of discrete Kalman's self-adapting image denoising system based on FPGA as described in claim 1, it is characterised in that:
The course of work of described image data input module is: being read in by MATLAB to the image for wanting noise reduction, and by image slices
Prime information is generated as .mif formatted file, stores image data by the memory ROM module in FPGA later.
3. a kind of discrete Kalman's self-adapting image denoising system based on FPGA as described in claim 1, it is characterised in that:
The course of work of the clock frequency division module is: frequency dividing setting is carried out to externally input clock, for carrying out the period to data
The reading of property, and carry out according to the period recursive calculation of discrete Kalman.
4. a kind of discrete Kalman's self-adapting image denoising system based on FPGA as described in claim 1, it is characterised in that:
The Kalman filtering module includes filter module and kalman gain calculates and filtering parameter modified module.
5. a kind of discrete Kalman's self-adapting image denoising system based on FPGA as described in claim 1, it is characterised in that:
The data outputting module task is using the serial communication between FPGA and computer, after Kalman Filtering for Discrete module filtered
Image data is sent to computer, and generates .txt file；Then utilize MATLAB program, by the image data in txt file into
Row is read, to generate filtered image result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811317274.8A CN109544469A (en) | 2018-11-07 | 2018-11-07 | A kind of discrete Kalman's self-adapting image denoising system based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811317274.8A CN109544469A (en) | 2018-11-07 | 2018-11-07 | A kind of discrete Kalman's self-adapting image denoising system based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109544469A true CN109544469A (en) | 2019-03-29 |
Family
ID=65844933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811317274.8A Pending CN109544469A (en) | 2018-11-07 | 2018-11-07 | A kind of discrete Kalman's self-adapting image denoising system based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109544469A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111882587A (en) * | 2020-07-15 | 2020-11-03 | 广东欧谱曼迪科技有限公司 | FPGA (field programmable Gate array) implementation method and system for Kalman filtering, storage medium and terminal |
| CN113709324A (en) * | 2020-05-21 | 2021-11-26 | 武汉Tcl集团工业研究院有限公司 | Video noise reduction method, video noise reduction device and video noise reduction terminal |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103051829A (en) * | 2012-12-10 | 2013-04-17 | 天津天地伟业数码科技有限公司 | Noise reduction system and noise reduction method for original image data based on FPGA (Field Programmable Gate Array) platform |
-
2018
- 2018-11-07 CN CN201811317274.8A patent/CN109544469A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103051829A (en) * | 2012-12-10 | 2013-04-17 | 天津天地伟业数码科技有限公司 | Noise reduction system and noise reduction method for original image data based on FPGA (Field Programmable Gate Array) platform |
Non-Patent Citations (1)
| Title |
|---|
| 仲婷婷等: "基于FPGA的卡尔曼滤波器的设计与实现", 《电子技术应用》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113709324A (en) * | 2020-05-21 | 2021-11-26 | 武汉Tcl集团工业研究院有限公司 | Video noise reduction method, video noise reduction device and video noise reduction terminal |
| CN111882587A (en) * | 2020-07-15 | 2020-11-03 | 广东欧谱曼迪科技有限公司 | FPGA (field programmable Gate array) implementation method and system for Kalman filtering, storage medium and terminal |
| CN111882587B (en) * | 2020-07-15 | 2022-12-02 | 广东欧谱曼迪科技有限公司 | FPGA (field programmable Gate array) implementation method and system for Kalman filtering, storage medium and terminal |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Allred et al. | LMS adaptive filters using distributed arithmetic for high throughput | |
| CN106683171B (en) | GPU multithreading texture mapping SystemC modeling structure | |
| CN108229645B (en) | Convolution acceleration and calculation processing method and device, electronic equipment and storage medium | |
| KR20180080876A (en) | Convolution circuit, application processor having the same, and operating methoe thereof | |
| CN113313243B (en) | Neural network accelerator determining method, device, equipment and storage medium | |
| CN109871949A (en) | Convolutional neural networks accelerator and accelerated method | |
| CN111931925B (en) | Acceleration system of binary neural network based on FPGA | |
| CN109544469A (en) | A kind of discrete Kalman's self-adapting image denoising system based on FPGA | |
| CN102098509B (en) | Reconfigurable interpolation filter based on Farrow structure | |
| WO2023123919A1 (en) | Data processing circuit, data processing method, and related product | |
| CN111337890A (en) | LFMCW radar target echo signal simulation method | |
| CN101937423A (en) | Streamline FFT/IFFT processing system | |
| JP5798378B2 (en) | Apparatus, processing method, and program | |
| CN103956991A (en) | FIR filter parallel realization method based on CPU/GPU heterogeneous platform | |
| CN108647780B (en) | Reconfigurable pooling operation module structure facing neural network and implementation method thereof | |
| CN109976660A (en) | Any resampling methods and sampled-data system based on linear interpolation | |
| CN116578819A (en) | Sparse fraction Fourier transform FPGA implementation method and system | |
| CN117014057A (en) | Network slice resource allocation method, device and storage medium | |
| CN116227599A (en) | Inference model optimization method and device, electronic equipment and storage medium | |
| CN1189902A (en) | Semiconductor memory having arithmetic function, and processor using the same | |
| CN111429352B (en) | Image super-resolution reconstruction method and device based on neural network | |
| CN110348566B (en) | Method and system for generating digital signal for neural network training | |
| CN105578083B (en) | Low noise CCD image formation electronic system | |
| CN112734673B (en) | Low-illumination image enhancement method and system based on multi-expression fusion | |
| CN200976573Y (en) | Sample rate converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: The Olympic Avenue in Jianye District of Nanjing city of Jiangsu Province, No. 69 210019 Applicant after: Nanjing University of Information Science and Technology Address before: 211500 Yuting Square, 59 Wangqiao Road, Liuhe District, Nanjing City, Jiangsu Province Applicant before: Nanjing University of Information Science and Technology |
|
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 210032 No. 219 Ning six road, Jiangbei new district, Nanjing, Jiangsu Applicant after: Nanjing University of Information Science and Technology Address before: The Olympic Avenue in Jianye District of Nanjing city of Jiangsu Province, No. 69 210019 Applicant before: Nanjing University of Information Science and Technology |