CN110971481A - Method and device for testing cache address management logic - Google Patents
Method and device for testing cache address management logic Download PDFInfo
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- CN110971481A CN110971481A CN201911071658.0A CN201911071658A CN110971481A CN 110971481 A CN110971481 A CN 110971481A CN 201911071658 A CN201911071658 A CN 201911071658A CN 110971481 A CN110971481 A CN 110971481A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/50—Network services
- H04L67/56—Provisioning of proxy services
- H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
Abstract
The invention provides a test method of cache address management logic, which is used for ensuring the correctness of the realization of all the cache address management logic in a chip; the method can automatically identify all the cache address management logics in the chip and prove that all the cache address management logics are covered in the test; in addition, the method provides a means for detecting the working correctness of each cache address management logic in the test process in real time, and once address repeated distribution or repeated recovery errors occur, the address repeated distribution or repeated recovery errors can be reported and recorded in time; meanwhile, the method provides a means for checking whether the address is leaked.
Description
Technical Field
The invention relates to a method and a device for testing cache address management logic.
Background
At present, communication networks are increasingly used for processing service types and increasing transmission bandwidth, the amount of information required to be processed and calculated by each device in the network is exponentially increased, and the amount of data required to be stored by each corresponding device is also expanded. The increase of the storage data amount corresponds to the increase of cache addresses in a network processing chip in the equipment, and the complexity of cache address management logic is increased along with the increase of the cache addresses; if the logic implementation of the cache address management is not fully tested, more serious problems, such as address leakage, address repeated allocation, repeated recovery and the like, can occur to the produced chip during application; when the address management problem occurs, the chip computation speed is slow, the processing bandwidth is low, and even the chip is suspended, so that the abnormality of the whole network device and system is caused.
When the number of cache addresses is large, the problem of address management is difficult to find through conventional tests, or even if the problem occurs in the tests, the problem caused by address management errors is difficult to quickly locate; when the number of the caches in the chip is large, a certain cache is easy to miss and is not checked; or because the number of caches to be checked is too large, the workload caused by sequentially confirming the functional correctness one by one manually is too large, so that the test time before the production of the chip is increased, the development time of the chip is increased, and the development cycle of the whole network equipment and system is further prolonged.
For the correctness test of the network chip logic, the conventional test method is to equivalently convert the chip logic function into an FPGA (field Programmable Gate array) logic, download the logic into the FPGA of a test board card, butt the test board card with a test instrument, send a data packet to the FPGA by the test instrument, after the FPGA finishes processing the data packet, return the packet to the test instrument for comparison analysis and flow confirmation, and if the returned packets are correct and the flow confirmation is normal, the logic is considered to be correctly realized. For the cache address management test, the method has the following three problems:
1. the method can not ensure that the test covers all the cache address management logics in the logics, namely, the method can not ensure that the management logics corresponding to all the caches are distributed and recycled in the test process; if it cannot be confirmed that all the cache address management logics are covered by the test, the correctness of all the cache address management logics cannot be proved.
2. Whether address repeated allocation or repeated recovery errors occur in each cache cannot be monitored, namely if cache address management logic errors exist, the errors are not represented on a test result due to insufficient test time or low measurement precision and the like, and the problem cannot be found.
3. The problem of address leakage cannot be checked, if the address leakage only appears a few times in the whole test process, the test results such as packet flow and the like are not influenced, and the problem is missed.
Disclosure of Invention
In view of this, the present invention is directed to a method for testing a cache address management logic, which is used to ensure the correctness of the implementation of all the cache address management logics in a chip.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a test method of cache address management logic comprises the following steps:
(1) writing a public check module of cache address management logic;
(2) compiling scripts, and matching all caches in the logic according to keywords realized by the caches;
(3) tracking a cache address management logic according to the cached write input address;
(4) instantiating a common check module for each cache address management logic, and taking the address signals distributed and recycled by each cache address management logic as input signals of each instantiated common check module;
(5) the tester sends a package to the logic of the chip to be tested until the package sending test is finished;
(6) checking whether all cache management logics perform address allocation actions;
(7) checking whether all cache management logics perform address recovery actions;
(8) checking whether the same address is repeatedly allocated in the cache management logic;
(9) checking whether the same address is repeatedly recycled by cache management logic;
(10) and checking whether a cache address leaks.
Further, in the step (1), the common checking module is implemented as follows:
(11) setting a register group reg _ array with the same depth according to the depth of the cache corresponding to the address management logic, wherein each register in the register group corresponds to the occupation state of 1 cache address, and setting the initial value of each register in the register group to be 1 to indicate that all cache addresses are unoccupied;
(12) taking the distribution address of the tested address management logic as an input alloc _ addr _ in of the checking module, and setting a register reg _ array [ alloc _ addr _0] to be 0 when the address management logic inputs an alloc _ addr _ 0; meanwhile, setting the detected allocation indication register alloc _ flag to 1 to indicate that the detected logic has the address allocation action;
(13) taking the distribution address of the tested address management logic as an input alloc _ addr _ in of the checking module, and setting a register reg _ array [ alloc _ addr _0] to be 0 when the address management logic inputs an alloc _ addr _ 0; meanwhile, setting the detected allocation indication register alloc _ flag to 1 to indicate that the detected logic has the address allocation action;
(14) when the tested address management logic inputs an allocation address alloc _ addr _1, firstly judging whether a register reg _ array [ alloc _ addr _1] is 1, and if so, setting the register reg _ array [ alloc _ addr _1] to be 0; if the address is 0, the address repeated allocation error is considered to occur, reg _ array [ alloc _ addr _1] is kept to be 0, the repeated allocation error register re _ alloc _ err is set to be 1, and the repeatedly allocated address alloc _ addr _1 is recorded in the register alloc _ err _ addr;
(15) when the tested address management logic inputs a recovery address recy _ addr _1, firstly judging whether a register reg _ array [ recy _ addr _1] is 0, and if so, setting the reg _ array [ recy _ addr _1] to 1; if the address is 1, the address repeat recovery error is considered to occur, the reg _ array [ recy _ addr _1] is kept to be 1, the repeat recovery error register re _ rec _ err is set to be 1, and the address repeat _ addr _1 of the repeat recovery is recorded in the register recy _ err _ addr.
Further, the step (6) is specifically implemented as follows, reading the value of the register alloc _ flag in each instantiated checking module, and if the value is 1, proving that the tested cache address management logic has already performed the over-allocated address check; if the value is 0, the tested cache address management logic does not perform over-distribution address check, namely the tested logic does not perform address distribution action in the test process, and supplementary test or retest is performed according to the condition to confirm the logic implementation and the coverage condition of excitation.
Further, the step (7) is specifically realized as follows: reading the value of a register recy _ flag in each instantiated checking module, and if the value is 1, proving that the tested cache address management logic has already carried out recovery address checking; if the address is 0, the tested cache address management logic does not perform address recovery check, that is, the tested cache address management logic does not perform address recovery action in the test process, and performs supplementary test or retest according to the situation to confirm the logic implementation and the excited coverage situation.
Further, the step (8) is specifically realized as follows: reading the value of a register re _ alloc _ err in each instantiated check module, and if the value is 0, proving that no repeated allocation error occurs in the tested cache address management logic; if the number is 1, proving that the tested cache address management logic has the situation of repeated allocation, carrying out problem positioning and analysis according to the repeated allocation address recorded in the register alloc _ err _ addr, and retesting after modifying the logic.
Further, the step (9) is specifically realized as follows: reading the value of a register re _ recy _ err in each instantiated checking module, and if the value is 0, proving that the tested cache address management logic has no repeated recovery error; if the number is 1, proving that the tested cache address management logic has the situation of repeated recovery, problem positioning and analysis are required to be carried out according to the repeated distribution address recorded in the register recy _ err _ addr, and retesting is carried out after the logic is modified.
Further, the step (10) is specifically realized as follows: reading each register value of a register group reg _ array in each instantiated checking module, and if each register value is 1, proving that the tested cache address management logic has completely recycled the address; if at least 1 register is 0, it is proved that the tested cache address management logic does not recover all addresses, and an address leak occurs in the test process, the leaked address needs to be obtained according to the register with the register group reg _ array of 0, the problem location and analysis are carried out, and the retest is carried out after the logic is modified.
Another objective of the present invention is to provide a testing apparatus for cache address management logic, which is implemented as follows: comprises that
The public inspection module compiling module is used for compiling a public inspection module of the cache address management logic;
the cache matching module is used for matching all caches in the logic according to the keywords realized by the caches by compiling the script;
the cache address management logic tracking module is used for tracking the cache address management logic according to the cached write input address;
the instantiated common check module is used for instantiating a common check module for each cache address management logic, and takes the address signals distributed and recovered by each cache address management logic as input signals of each instantiated common check module;
the package sending module is used for sending a package to the logic of the chip to be tested by the tester until the package sending test is finished;
the address allocation action detection module is used for checking whether all the cache management logics perform address allocation actions;
the address recovery action detection module is used for checking whether all the cache management logics perform address recovery actions;
the same address repeated distribution detection module is used for checking whether the same address repeated distribution occurs in the cache management logic;
the same address repeated recovery module is used for checking whether the same address repeated recovery occurs in the cache management logic;
and the cache address leakage detection module is used for checking whether a cache address is leaked.
Compared with the prior art, the method and the device for testing the cache address management logic have the following advantages that:
1. the invention can automatically identify all caches in the chip, further track all cache address management logics in the chip and ensure the completeness of test coverage;
2. the invention identifies the cache address management logic which does not work in the test process, thereby ensuring the test comprehensiveness;
3. the invention checks whether the same address repeated distribution problem caused by incorrect implementation of the cache address management logic occurs in the test process, and can provide the repeated distribution address to facilitate problem positioning;
4. the invention checks whether the same address repeated recovery problem caused by incorrect implementation of the cache address management logic occurs in the test process, and can provide the repeated recovery address to facilitate problem positioning;
5. the invention checks whether the address leakage problem occurs in the test process, and can provide the leaked address for problem positioning;
6. the public inspection module can be used for repeatedly instantiating the address management logic corresponding to each cache, the inspection module has reusability, the inspection consistency is ensured, and the quick and unified replacement after the subsequent inspection module is updated is facilitated.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 and 2 are schematic diagrams illustrating a flow of a method for testing a cache address management logic according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a cache address management logic checking common module according to an embodiment of the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
The invention provides a test method of cache address management logic, which is used for ensuring the correctness of the realization of all the cache address management logic in a chip; the method can automatically identify all the cache address management logics in the chip and prove that all the cache address management logics are covered in the test; in addition, the method provides a means for detecting the working correctness of each cache address management logic in the test process in real time, and once address repeated distribution or repeated recovery errors occur, the address repeated distribution or repeated recovery errors can be reported and recorded in time; meanwhile, the method provides a means for checking whether the address is leaked.
The specific implementation steps of the invention are shown in fig. 1, and the specific steps are as follows:
the method comprises the following steps: the Common Check Module Common _ Check _ Module of the cache address management logic is written, the Module composition is shown in fig. 3, and the implementation is described as follows:
(1) setting a register group reg _ array with the same depth according to the depth of the cache corresponding to the address management logic, wherein each register in the register group corresponds to the occupation state of 1 cache address, and setting the initial value of each register in the register group to be 1 to indicate that all cache addresses are unoccupied.
(2) Taking the distribution address of the tested address management logic as an input alloc _ addr _ in of the checking module, and setting a register reg _ array [ alloc _ addr _0] to be 0 when the address management logic inputs an alloc _ addr _ 0; meanwhile, the detected allocation indication register alloc _ flag is set to 1, which indicates that the address allocation action of the logic under test has occurred.
(3) Taking the recovery address of the tested address management logic as an input recy _ addr _ in of the checking module, and setting a register reg _ array [ recy _ addr _0] to be 1 when the address management logic inputs a recovery address recy _ addr _ 0; meanwhile, the detected recovery indication register recy _ flag is set to 1, which indicates that the detected logic has the address recovery action.
(4) When the tested address management logic inputs an allocation address alloc _ addr _1, firstly judging whether a register reg _ array [ alloc _ addr _1] is 1, and if so, setting the register reg _ array [ alloc _ addr _1] to be 0; if the address is 0, the address repeated allocation error is considered to occur, reg _ array [ alloc _ addr _1] is kept to be 0, the repeated allocation error register re _ alloc _ err is set to be 1, and the repeatedly allocated address alloc _ addr _1 is recorded in the register alloc _ err _ addr;
(5) when the tested address management logic inputs a recovery address recy _ addr _1, firstly judging whether a register reg _ array [ recy _ addr _1] is 0, and if so, setting the reg _ array [ recy _ addr _1] to 1; if the address is 1, the address repeat recovery error is considered to occur, the reg _ array [ recy _ addr _1] is kept to be 1, the repeat recovery error register re _ rec _ err is set to be 1, and the address repeat _ addr _1 of the repeat recovery is recorded in the register recy _ err _ addr.
Step two: and compiling scripts, and matching all caches in the logic according to the keywords realized by the caches.
Step three: and tracking the cache address management logic according to the cached write input address.
Step four: for each cache address management logic, a Common Check Module is instantiated, and the address signals distributed and recovered by each cache address management logic are used as input signals of each instantiated Common Check Module, namely, each cache address management logic is matched with one Check Module.
Step five: and the tester sends a package to the logic of the chip to be tested until the package sending test is completed.
Step six: reading the value of a register alloc _ flag in each instantiated checking module, and if the value is 1, proving that the tested cache address management logic carries out over-distribution address checking; if the value is 0, the tested cache address management logic does not perform over-distribution address check, namely the tested logic does not perform address distribution action in the test process, and supplementary test or retest is performed according to the condition to confirm the logic implementation and the coverage condition of excitation.
Step seven: reading the value of a register recy _ flag in each instantiated checking module, and if the value is 1, proving that the tested cache address management logic has already carried out recovery address checking; if the address is 0, the tested cache address management logic does not perform address recovery check, that is, the tested cache address management logic does not perform address recovery action in the test process, and performs supplementary test or retest according to the situation to confirm the logic implementation and the excited coverage situation.
Step eight: reading the value of a register re _ alloc _ err in each instantiated check module, and if the value is 0, proving that no repeated allocation error occurs in the tested cache address management logic; if the number is 1, proving that the tested cache address management logic has the situation of repeated allocation, carrying out problem positioning and analysis according to the repeated allocation address recorded in the register alloc _ err _ addr, and retesting after modifying the logic.
Step nine: reading the value of a register re _ recy _ err in each instantiated checking module, and if the value is 0, proving that the tested cache address management logic has no repeated recovery error; if the number is 1, proving that the tested cache address management logic has the situation of repeated recovery, problem positioning and analysis are required to be carried out according to the repeated distribution address recorded in the register recy _ err _ addr, and retesting is carried out after the logic is modified.
Step ten: reading each register value of a register group reg _ array in each instantiated checking module, and if each register value is 1, proving that the tested cache address management logic has completely recycled the address; if at least 1 register is 0, it is proved that the tested cache address management logic does not recover all addresses, and an address leak occurs in the test process, the leaked address needs to be obtained according to the register with the register group reg _ array of 0, the problem location and analysis are carried out, and the retest is carried out after the logic is modified.
According to the invention, all caches are matched by compiling scripts, and then all cache management logics are tracked, so that possible omission caused by manual identification is avoided; whether all cache management logics perform address allocation and recovery actions is checked, and problem hiding caused by the fact that problematic logics do not work is avoided; checking whether the cache management logic has the same address repeated distribution error; checking whether the cache management logic has the same address repeated recovery error; checking whether a cache address leakage error exists; the inspection module is a public component and can be reused to each management logic, so that the inspection consistency is ensured.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (8)
1. A test method for cache address management logic is characterized in that: the method comprises the following steps:
(1) writing a public check module of cache address management logic;
(2) compiling scripts, and matching all caches in the logic according to keywords realized by the caches;
(3) tracking a cache address management logic according to the cached write input address;
(4) instantiating a common check module for each cache address management logic, and taking the address signals distributed and recycled by each cache address management logic as input signals of each instantiated common check module;
(5) the tester sends a package to the logic of the chip to be tested until the package sending test is finished;
(6) checking whether all cache management logics perform address allocation actions;
(7) checking whether all cache management logics perform address recovery actions;
(8) checking whether the same address is repeatedly allocated in the cache management logic;
(9) checking whether the same address is repeatedly recycled by cache management logic;
(10) and checking whether a cache address leaks.
2. The method for testing cache address management logic according to claim 1, wherein: in the step (1), the public inspection module is implemented as follows:
(11) setting a register group reg _ array with the same depth according to the depth of the cache corresponding to the address management logic, wherein each register in the register group corresponds to the occupation state of 1 cache address, and setting the initial value of each register in the register group to be 1 to indicate that all cache addresses are unoccupied;
(12) taking the distribution address of the tested address management logic as an input alloc _ addr _ in of the checking module, and setting a register reg _ array [ alloc _ addr _0] to be 0 when the address management logic inputs an alloc _ addr _ 0; meanwhile, setting the detected allocation indication register alloc _ flag to 1 to indicate that the detected logic has the address allocation action;
(13) taking the distribution address of the tested address management logic as an input alloc _ addr _ in of the checking module, and setting a register reg _ array [ alloc _ addr _0] to be 0 when the address management logic inputs an alloc _ addr _ 0; meanwhile, setting the detected allocation indication register alloc _ flag to 1 to indicate that the detected logic has the address allocation action;
(14) when the tested address management logic inputs an allocation address alloc _ addr _1, firstly judging whether a register reg _ array [ alloc _ addr _1] is 1, and if so, setting the register reg _ array [ alloc _ addr _1] to be 0; if the address is 0, the address repeated allocation error is considered to occur, reg _ array [ alloc _ addr _1] is kept to be 0, the repeated allocation error register re _ alloc _ err is set to be 1, and the repeatedly allocated address alloc _ addr _1 is recorded in the register alloc _ err _ addr;
(15) when the tested address management logic inputs a recovery address recy _ addr _1, firstly judging whether a register reg _ array [ recy _ addr _1] is 0, and if so, setting the reg _ array [ recy _ addr _1] to 1; if the address is 1, the address repeat recovery error is considered to occur, the reg _ array [ recy _ addr _1] is kept to be 1, the repeat recovery error register re _ rec _ err is set to be 1, and the address repeat _ addr _1 of the repeat recovery is recorded in the register recy _ err _ addr.
3. The method for testing cache address management logic according to claim 2, wherein: the step (6) is specifically realized by reading the value of a register alloc _ flag in each instantiated checking module, and if the value is 1, verifying that the tested cache address management logic performs over-distribution address checking; if the value is 0, the tested cache address management logic does not perform over-distribution address check, namely the tested logic does not perform address distribution action in the test process, and supplementary test or retest is performed according to the condition to confirm the logic implementation and the coverage condition of excitation.
4. The method for testing cache address management logic according to claim 2, wherein: the step (7) is specifically realized as follows: reading the value of a register recy _ flag in each instantiated checking module, and if the value is 1, proving that the tested cache address management logic has already carried out recovery address checking; if the address is 0, the tested cache address management logic does not perform address recovery check, that is, the tested cache address management logic does not perform address recovery action in the test process, and performs supplementary test or retest according to the situation to confirm the logic implementation and the excited coverage situation.
5. The method for testing cache address management logic according to claim 2, wherein: the step (8) is specifically realized as follows: reading the value of a register re _ alloc _ err in each instantiated check module, and if the value is 0, proving that no repeated allocation error occurs in the tested cache address management logic; if the number is 1, proving that the tested cache address management logic has the situation of repeated allocation, carrying out problem positioning and analysis according to the repeated allocation address recorded in the register alloc _ err _ addr, and retesting after modifying the logic.
6. The method for testing cache address management logic according to claim 2, wherein: the step (9) is specifically realized as follows: reading the value of a register re _ recy _ err in each instantiated checking module, and if the value is 0, proving that the tested cache address management logic has no repeated recovery error; if the number is 1, proving that the tested cache address management logic has the situation of repeated recovery, problem positioning and analysis are required to be carried out according to the repeated distribution address recorded in the register recy _ err _ addr, and retesting is carried out after the logic is modified.
7. The method for testing cache address management logic according to claim 2, wherein: the step (10) is specifically realized as follows: reading each register value of a register group reg _ array in each instantiated checking module, and if each register value is 1, proving that the tested cache address management logic has completely recycled the address; if at least 1 register is 0, it is proved that the tested cache address management logic does not recover all addresses, and an address leak occurs in the test process, the leaked address needs to be obtained according to the register with the register group reg _ array of 0, the problem location and analysis are carried out, and the retest is carried out after the logic is modified.
8. A testing device for cache address management logic is characterized in that: comprises that
The public inspection module compiling module is used for compiling a public inspection module of the cache address management logic;
the cache matching module is used for matching all caches in the logic according to the keywords realized by the caches by compiling the script;
the cache address management logic tracking module is used for tracking the cache address management logic according to the cached write input address;
the instantiated common check module is used for instantiating a common check module for each cache address management logic, and takes the address signals distributed and recovered by each cache address management logic as input signals of each instantiated common check module;
the package sending module is used for sending a package to the logic of the chip to be tested by the tester until the package sending test is finished;
the address allocation action detection module is used for checking whether all the cache management logics perform address allocation actions;
the address recovery action detection module is used for checking whether all the cache management logics perform address recovery actions;
the same address repeated distribution detection module is used for checking whether the same address repeated distribution occurs in the cache management logic;
the same address repeated recovery module is used for checking whether the same address repeated recovery occurs in the cache management logic;
and the cache address leakage detection module is used for checking whether a cache address is leaked.
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