CN114546749A - Chip random test case regression method, device, equipment and readable medium - Google Patents
Chip random test case regression method, device, equipment and readable medium Download PDFInfo
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Abstract
The invention discloses a regression method for a chip random test case, which comprises the following steps: setting the random times of each test case, and generating seed cases with the corresponding random times of each test case; submitting all the seed cases of each test case to a test in sequence based on a preset maximum operation number; in response to detecting that a certain seed case fails to test, stopping submitting other uncommitted seed cases generated by the corresponding test case to test; and acquiring the failure reason of the test failure seed case, and testing the test failure seed case again based on a preset strategy. The invention also discloses a chip random test case regression device, computer equipment and a readable storage medium. The random test is carried out on the random case for a fixed number of times, additional learning by a user is not needed, and the operation is simpler; the input content is simplified and clear, the result file is clear, and a better processing mode is provided for the case after the case fails.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a chip random test case regression method, device, equipment and readable medium.
Background
Chip verification plays an important role in the whole chip design process, and is the most important ring for ensuring the chip quality and shortening the chip period. With the increasing of chip scale, the modules inside the chip are also becoming more complex, and in order to ensure the sufficiency of verification, chip verification engineers often adopt a random test case mode to cover all possible excitation situations as much as possible. However, the more complicated the random test case is, the more random stimulus becomes. In order to ensure that the verification result is converged continuously, i.e. covers all situations as much as possible, a regression test is required to be performed continuously. The process of regression of the random test cases is usually simple and tedious, but a large amount of manpower and material resources have to be spent, so that a simple and efficient regression method of the random test cases is needed, the verification cost is greatly reduced, and the verification period is shortened.
At present, tools for managing test cases in the market, such as a mainstream EDA manufacturer Cadence, provide a VManger tool, which needs to prepare input files such as a CSV file and a vsif file of verification feature in advance, then manage regression test cases defined in the CSV file by calling the VManger tool, run the regression test cases by using the vsif file, simultaneously, react all the regression test cases to an interface, integrate various functions, and automatically merge results so as to check coverage rates of codes, overturns and the like. However, most of the tools for test case management in the market at present are expensive and complicated in use and configuration, and the verification personnel need to learn the use method in advance to complete the requirements of the verification personnel, so that the verification cost is high, and the use efficiency is low.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a method, an apparatus, a device, and a readable medium for regression of random test cases of chips, so as to perform random tests on random cases for a fixed number of times without additional learning by a user, and to make operations simpler than those of other tools on the market; the input content is simplified and clear, the result file is clear, and a better processing mode is provided for the case after the case fails.
Based on the above purpose, an aspect of the embodiments of the present invention provides a regression method for random test cases of chips, including the following steps: setting the random times of each test case, and generating seed cases with the corresponding random times of each test case; submitting all the seed cases of each test case to a test in sequence based on a preset maximum operation number; in response to the detection of the test failure of a certain seed case, stopping submitting the test of other uncommitted seed cases generated by the corresponding test case; and acquiring failure reasons of the test failure seed cases, and testing the test failure seed cases again based on a preset strategy.
In some embodiments, setting a random number of times of each test case, and generating a seed case corresponding to the random number of times of each test case includes: setting random times corresponding to different types of test cases; and acquiring the type of each test case, and generating seed cases with random times corresponding to the type of each test case.
In some embodiments, sequentially submitting all the seed use cases of each test use case to test based on a preset maximum running number comprises: submitting the seed cases with the preset maximum operation number to a test; and submitting a seed case to be submitted in response to detecting that the test of the seed case is completed.
In some embodiments, the method further comprises: storing the state of the seed case after the test into a log; if the seed case test is successful, directly storing; and if the test of the seed case fails, extracting the value of the seed case and storing the extracted value.
In some embodiments, in response to detecting that a seed case test fails, stopping other uncommitted seed case submission tests for which the corresponding test case was generated comprises: and in response to the detection that a certain seed case fails in testing, deleting other uncommitted seed cases generated by the corresponding test case from the seed cases to be submitted, and submitting the uncommitted seed cases generated by the other test cases to testing.
In some embodiments, obtaining the failure cause of the test failure seed case includes: and acquiring the failure reason of the test failure seed case, and recording the value of the seed case.
In some embodiments, retesting the test failure seed use case based on the preset policy includes: retesting all the test failure seed cases; or retesting the seed use case that specifies the cause of failure.
In another aspect of the embodiments of the present invention, a device for regression of random test cases of chips is further provided, including: the first module is configured to set the random times of each test case and generate seed cases with the corresponding random times of each test case; the second module is configured to submit all the seed cases of each test case to a test in sequence based on a preset maximum operation number; the third module is configured to stop submitting other uncommitted seed use cases generated by the corresponding test use case to the test in response to detecting that a certain seed use case fails to test; and the fourth module is configured to acquire the failure reason of the test failure seed case and test the test failure seed case again based on a preset strategy.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing steps of the method comprising: setting the random times of each test case, and generating seed cases with the corresponding random times of each test case; submitting all the seed cases of each test case to a test in sequence based on a preset maximum operation number; in response to detecting that a certain seed case fails to test, stopping submitting other uncommitted seed cases generated by the corresponding test case to test; and acquiring the failure reason of the test failure seed case, and testing the test failure seed case again based on a preset strategy.
In some embodiments, setting a random number of times of each test case, and generating a seed case corresponding to the random number of times of each test case includes: setting random times corresponding to different types of test cases; and acquiring the type of each test case, and generating seed cases with random times corresponding to the type of each test case.
In some embodiments, sequentially submitting all the seed use cases of each test use case to test based on a preset maximum running number comprises: submitting the seed cases with the preset maximum operation number to a test; and submitting a seed case to be submitted in response to detecting that the test of the seed case is completed.
In some embodiments, the method further comprises: storing the state of the seed case after the test into a log; if the seed case test is successful, directly storing; and if the test of the seed case fails, extracting the value of the seed case and storing the extracted value.
In some embodiments, in response to detecting that a seed case test fails, stopping other uncommitted seed case submission tests for which the corresponding test case was generated comprises: and in response to the detection that a certain seed case fails in testing, deleting other uncommitted seed cases generated by the corresponding test case from the seed cases to be submitted, and submitting the uncommitted seed cases generated by the other test cases to testing.
In some embodiments, obtaining the failure reason for the test failure seed case includes: and acquiring the failure reason of the test failure seed case, and recording the value of the seed case.
In some embodiments, retesting the test failure seed use case based on the preset policy includes: retesting all the test failure seed cases; or retesting the seed use case that specifies the cause of failure.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has at least the following beneficial technical effects: random testing is carried out on the random case for a fixed number of times, additional learning by a user is not needed, and the operation is simpler compared with other tools on the market; the input content is simplified and clear, the result file is clear, and a better processing mode is provided for the case after the case fails.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of an embodiment of a regression method for random test cases of chips according to the present invention;
FIG. 2 is a schematic diagram of an embodiment of a regression device for random test cases of chips according to the present invention;
FIG. 3 is a schematic diagram of an embodiment of a computer device provided by the present invention;
FIG. 4 is a schematic diagram of an embodiment of a computer-readable storage medium provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the above, a first aspect of the embodiments of the present invention provides an embodiment of a regression method for random test cases of chips. Fig. 1 is a schematic diagram illustrating an embodiment of a chip random test case regression method provided by the present invention. As shown in fig. 1, the regression method for random test cases of chips according to the embodiment of the present invention includes the following steps:
001. setting the random times of each test case, and generating seed cases with the corresponding random times of each test case;
002. submitting all the seed cases of each test case to test in sequence based on the preset maximum operation quantity;
003. in response to the detection of the test failure of a certain seed case, stopping submitting the test of other uncommitted seed cases generated by the corresponding test case; and
004. and acquiring the failure reason of the test failure seed case, and testing the test failure seed case again based on a preset strategy.
In this embodiment, a user defines a case to be tested randomly in the CSV, sets random number (random number) that is how many times this case is random, and then defines a preset maximum running number of cases, the tool collects the information, first generates a corresponding number of seed cases with a _ seed x suffix according to the random number, then submits the maximum running number of cases to the server, and then continuously detects the states of these cases, and if one of the seed cases has run, submits the next seed case. The use case of the operation end detects the simulation result, if PASS, the simulation result is directly reported in a result file, and if FAIL, the seed of the operation is extracted. After seeing the case failure, the user can select a run function, the tool can be re-executed according to the seed of the last operation failure for the user to analyze, and after modifying the error, the run function can be used for checking whether the code error is repaired.
In some embodiments of the present invention, setting the random number of times of each test case, and generating the seed case with the corresponding random number of times for each test case includes: setting random times corresponding to different types of test cases; and acquiring the type of each test case, and generating seed cases with random times corresponding to the type of each test case.
In some embodiments of the present invention, sequentially submitting all the seed use cases of each test use case to a test based on a preset maximum running number comprises: submitting the seed cases with the preset maximum operation number to a test; and submitting a seed case to be submitted in response to detecting that the test of the seed case is completed.
In this embodiment, the preset maximum operation number is taken as 5 as an example. First 5 seed cases are submitted for testing. And submitting the next seed case to be submitted in response to the completion of the test of one seed case. That is, 5 seed cases are always kept for parallel testing until all the seed cases to be submitted are tested completely.
In some embodiments of the invention, the method further comprises: storing the state of the seed case after the test into a log; if the seed case test is successful, directly storing; and if the test of the seed case fails, extracting the value of the seed case and storing the value.
In some embodiments of the present invention, in response to detecting that a seed case test fails, stopping submitting other uncommitted seed cases generated by its corresponding test case to a test includes: and in response to the detection that a certain seed case fails in testing, deleting other uncommitted seed cases generated by the corresponding test case from the seed cases to be submitted, and submitting the uncommitted seed cases generated by the other test cases to testing.
In some embodiments of the present invention, obtaining the failure reason of the test failure seed case includes: and acquiring the failure reason of the test failure seed case, and recording the value of the seed case.
In some embodiments of the present invention, retesting the test-failed seed use case based on the preset policy comprises: retesting all the test failure seed cases; or retesting the seed use case that specifies the cause of failure.
In this embodiment, the retest has at least two modes, one is retest according to the specified error type or fixed case, and the other is directly retest.
The following further illustrates embodiments of the invention in terms of specific examples. In the property function, the function description of the current module, whether random, the maximum running number of use cases and other key information are defined. The detailed name and description of each verification target, the measurement method, and the like are defined in the feature function. The CSV file is as follows:
from the parameters defined in the above CSV file, the tool extracts information that there are two types of test cases to be tested at random, where aa _ size _ test needs to be tested at random 10 times, bb _ size _ test needs to be tested at random 5 times, and the maximum number of concurrent commits is 5, then the tool generates two different test cases from aa _ size _ test _ seed0 to aa _ size _ test _ seed9, bb _ size0_ test _ seed0 to bb _ size0_ test _ seed4, bb _ size1_ test _ seed0 to bb _ size1_ test _ seed4, which respectively generate 10, 5, and 5 seed cases. The output result file mainly contains the regression result of the test case and the seed used when the case fails, and the specific steps are as follows:
aa_size_test_seed0 PASS
aa_size_test_seed1 PASS
aa_size_test_seed2 PASS
aa_size_test_seed3 PASS
aa_size_test_seed4 PASS
aa_size_test_seed5 PASS
aa_size_test_seed6 FAIL seed＝4356219 aaa_error
bb_size0_test_seed0 PASS
bb_size0_test_seed1 PASS
bb_size0_test_seed2 PASS
bb_size0_test_seed3 PASS
bb_size0_test_seed4 PASS
bb_size1_test_seed0 FAIL seed＝6490236 aaa_error
bb_size1_test_seed1 FAIL seed＝7854327 bbb_error
in the process of testing the random case, if the last seed is detected to be successful randomly, only recording PASS in a result file, and then testing the next seed of the case; if the last seed is detected to be in error, the following operations are executed:
stopping continuously testing the other seed conditions of the random case, for example, after the aa _ size _ test _ seed6 fails to test, the aa _ size _ test _ seed7 which should be operated is not tested any more, but the random test process of bb _ size0_ test is started until all PASS are tested, and then the case random test of bb _ size1_ test is started; taking out a seed value of the current operation from a result file of the case operation, for example, testing FAIL by aa _ size _ test _ seed6, and recording the seed value 4356219; and analyzing the probable reason of the simulation failure of the use case according to the result file for the user to check.
If the random case test fails, the following two problems need to be solved: firstly, how to quickly reproduce the reason for the tester to analyze the failure, and secondly, after the reason for the failure is clarified and relevant modification is made, quickly knowing whether the modification is correct, whether the problem is solved and whether a new problem is introduced; both of these problems are closely related to the seed value, and the present invention supports a fast run function after a fixed seed.
The re-running function has two modes, namely, re-testing is carried out according to the specified error type or the fixed case, and all re-testing is directly carried out. Taking the above result as an example, after the case failing due to the bbb _ error type is specified to be retested, testing bb _ size1_ test _ seed1 according to seed being 7854327, and testing only this case; if all cases are selected to be tested again directly, the three failed cases can be tested according to the seed which fails.
It should be particularly noted that, the steps in the embodiments of the above-mentioned chip random test case regression method may be mutually intersected, replaced, added, and deleted, so that these reasonable permutation and combination transformations applied to the chip random test case regression method should also belong to the scope of the present invention, and should not limit the scope of the present invention to the embodiments.
In view of the foregoing, a second aspect of the embodiments of the present invention provides a regression device for random test cases of chips. Fig. 2 is a schematic diagram illustrating an embodiment of a chip random test case regression apparatus provided in the present invention. As shown in fig. 2, the regression device for random test cases of chips according to the embodiment of the present invention includes the following modules: the first module 011 is configured to set the random number of times of each test case and generate seed cases corresponding to the random number of times of each test case; a second module 012 configured to submit all the seed cases of each test case to a test in sequence based on a preset maximum number of runs; a third module 013, configured to, in response to detecting that a certain seed case test fails, stop submitting other uncommitted seed cases generated by the corresponding test case to the test; and a fourth module 014 configured to obtain the failure reason of the test failure seed case, and retest the test failure seed case based on a preset strategy.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device. Fig. 3 is a schematic diagram of an embodiment of a computer device provided by the present invention. As shown in fig. 3, the computer apparatus of the embodiment of the present invention includes the following means: at least one processor 021; and a memory 022, the memory 022 storing computer instructions 023 executable on the processor, the instructions when executed by the processor implementing steps implementing a method comprising: setting the random times of each test case, and generating seed cases with the corresponding random times of each test case; submitting all the seed cases of each test case to test in sequence based on the preset maximum operation quantity; in response to detecting that a certain seed case fails to test, stopping submitting other uncommitted seed cases generated by the corresponding test case to test; and acquiring the failure reason of the test failure seed case, and testing the test failure seed case again based on a preset strategy.
In some embodiments of the present invention, setting the random number of times of each test case, and generating the seed case with the corresponding random number of times for each test case includes: setting random times corresponding to different types of test cases; and acquiring the type of each test case, and generating seed cases with random times corresponding to the type of each test case.
In some embodiments of the present invention, sequentially submitting all the seed use cases of each test use case to a test based on a preset maximum running number comprises: submitting the seed cases with the preset maximum operation number to a test; and submitting a seed case to be submitted in response to detecting that the test of the seed case is completed.
In some embodiments of the invention, the method further comprises: storing the state of the seed case after the test into a log; if the seed case test is successful, directly storing; and if the test of the seed case fails, extracting the value of the seed case and storing the value.
In some embodiments of the present invention, in response to detecting that a seed case test fails, stopping submitting other uncommitted seed cases generated by its corresponding test case to a test includes: and in response to the detection that a certain seed case fails in testing, deleting other uncommitted seed cases generated by the corresponding test case from the seed cases to be submitted, and submitting the uncommitted seed cases generated by the other test cases to testing.
In some embodiments of the present invention, obtaining the failure reason of the test failure seed case includes: and acquiring the failure reason of the test failure seed case, and recording the value of the seed case.
In some embodiments of the present invention, retesting the test-failed seed use case based on the preset policy comprises: retesting all the test failure seed cases; or retesting the seed cases specifying the cause of failure.
The invention also provides a computer readable storage medium. FIG. 4 is a schematic diagram illustrating an embodiment of a computer-readable storage medium provided by the present invention. As shown in fig. 4, the computer readable storage medium 031 stores a computer program 032 which, when executed by a processor, performs the method as described above.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate, all or part of the processes of the methods of the embodiments described above can be implemented by a computer program to instruct related hardware, and the program of the chip random test case regression method can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A regression method for random test cases of chips is characterized by comprising the following steps:
setting the random times of each test case, and generating seed cases with the corresponding random times of each test case;
submitting all the seed cases of each test case to a test in sequence based on a preset maximum operation number;
in response to detecting that a certain seed case fails to test, stopping submitting other uncommitted seed cases generated by the corresponding test case to test; and
and acquiring failure reasons of the test failure seed cases, and testing the test failure seed cases again based on a preset strategy.
2. The chip random test case regression method according to claim 1, wherein setting a random number of each test case, and generating a seed case corresponding to the random number of each test case comprises:
setting random times corresponding to different types of test cases;
and acquiring the type of each test case, and generating seed cases with random times corresponding to the type of each test case.
3. The chip random test case regression method according to claim 1, wherein submitting all the seed cases of each test case to a test in sequence based on a preset maximum number of runs comprises:
submitting the seed cases with the preset maximum operation number to a test;
and submitting a seed case to be submitted in response to detecting that the test of the seed case is completed.
4. The chip random test case regression method according to claim 3, further comprising:
storing the state of the seed case after the test into a log;
if the seed case test is successful, directly storing;
and if the test of the seed case fails, extracting the value of the seed case and storing the extracted value.
5. The method of claim 1, wherein stopping the submission of the test cases corresponding to the test cases to other uncommitted seed cases in response to detecting that a seed case fails to test comprises:
and in response to the detection that a certain seed case fails in testing, deleting other uncommitted seed cases generated by the corresponding test case from the seed cases to be submitted, and submitting the uncommitted seed cases generated by the other test cases to testing.
6. The method of claim 1, wherein obtaining the failure reason for the test failure seed case comprises:
and acquiring the failure reason of the test failure seed case, and recording the value of the seed case.
7. The chip random test case regression method according to claim 1, wherein retesting the test failure seed case based on the preset strategy comprises:
retesting all the test failure seed cases; or
The seed use case that specifies the reason for failure is retested.
8. A chip random test case regression device is characterized by comprising:
the first module is configured to set the random times of each test case and generate seed cases with the corresponding random times of each test case;
the second module is configured to submit all the seed cases of each test case to a test in sequence based on a preset maximum operation number;
the third module is configured to stop submitting other uncommitted seed use cases generated by the corresponding test use case to the test in response to detecting that a certain seed use case fails to test; and
and the fourth module is configured to acquire the failure reason of the test failure seed case and test the test failure seed case again based on a preset strategy.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 7.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.
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| CN115545677A (en) * | 2022-11-24 | 2022-12-30 | 云账户技术(天津)有限公司 | Online flow specification detection method and system based on automatic case execution condition |
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2022
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115545677A (en) * | 2022-11-24 | 2022-12-30 | 云账户技术(天津)有限公司 | Online flow specification detection method and system based on automatic case execution condition |
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