CN110957324A - Semiconductor memory - Google Patents
Semiconductor memory Download PDFInfo
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- CN110957324A CN110957324A CN201811130401.3A CN201811130401A CN110957324A CN 110957324 A CN110957324 A CN 110957324A CN 201811130401 A CN201811130401 A CN 201811130401A CN 110957324 A CN110957324 A CN 110957324A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 3
- 230000015654 memory Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7889—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
Abstract
The invention belongs to the technical field of semiconductor memories, and particularly discloses a semiconductor memory, which comprises: a semiconductor substrate, and located in the semiconductor substrate: at least one gate trench; the n-type drain region, the p-type base region and the n-type source region are respectively positioned on two sides of the gate trench from top to bottom; a control gate located at a lower portion of the gate trench; a program gate located on an upper portion of the gate trench and over the control gate; the two floating gates are positioned at the upper part of the gate groove and positioned at two sides of the programming gate respectively; the floating gate, the control gate, the programming gate and the semiconductor substrate are isolated by an insulating medium layer. The semiconductor memory can maintain a small chip area while realizing a long current channel, and can be manufactured by a self-aligned process with simple manufacturing process.
Description
Technical Field
The invention belongs to the technical field of semiconductor memories, and particularly relates to a semiconductor memory with a vertical current channel.
Background
Fig. 1 is a schematic cross-sectional view of a semiconductor memory according to the prior art, and as shown in fig. 1, the semiconductor memory according to the prior art includes: the semiconductor memory device comprises a semiconductor substrate 100, a p-type base region 10 located in the semiconductor substrate 100, an n-type source region 11 and an n-type drain region 12 located in the semiconductor substrate 100, wherein the surface part of the p-type base region 10 between the n-type source region 11 and the n-type drain region 12 is a current channel region of the semiconductor memory, and a floating gate structure and a control gate structure located above the current channel region. The floating gate structure comprises a gate dielectric layer 13 and a floating gate 14, and the floating gate 14 and the gate dielectric layer 13 are positioned above a current channel region at one side close to the n-type drain region 12. The control gate structure comprises an insulating medium layer 15 and a control gate 16, wherein the insulating medium layer 15 and the control gate 16 cover the floating gate 14 and extend towards one side of the n-type source region 11 to be above a current channel region close to one side of the n-type source region 11.
In the prior art semiconductor memory as shown in fig. 1, during programming, a high voltage is applied to the N-type drain region 12, channel hot electrons are injected into the floating gate 14 from the current channel region, during erasing, a strong electric field is generated by a high potential difference between the control gate 16 and the floating gate 14 to induce F-N tunneling, and electrons in the floating gate 14 are pulled toward the control gate 16. In order to ensure the performance of the semiconductor memory, the semiconductor memory needs a longer current channel region length, which makes the unit area of the semiconductor memory larger, which is not favorable for the development of the chip toward miniaturization.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a semiconductor memory to solve the problem of large chip area of the semiconductor memory in the prior art.
To achieve the above object of the present invention, the present invention provides a semiconductor memory comprising:
a semiconductor substrate, and located in the semiconductor substrate:
at least one gate trench;
the n-type drain region, the p-type base region and the n-type source region are respectively positioned on two sides of the gate trench from top to bottom;
a control gate located at a lower portion of the gate trench;
a program gate located on an upper portion of the gate trench and over the control gate;
the two floating gates are positioned at the upper part of the gate groove and positioned at two sides of the programming gate respectively;
the floating gate, the control gate, the programming gate and the semiconductor substrate are isolated by an insulating medium layer.
Optionally, in the semiconductor memory of the present invention, the control gate extends up to an upper portion of the gate trench.
Optionally, in the semiconductor memory of the present invention, a width of an upper portion of the gate trench is greater than a width of a lower portion of the gate trench.
Optionally, in the semiconductor memory of the present invention, the two floating gate structures are respectively located at two sides of the upper portion of the gate trench and at a width position between a sidewall of the lower portion of the gate trench and a sidewall of the upper portion of the gate trench.
Optionally, in the semiconductor memory of the present invention, the p-type base region and the n-type source region are both connected to a source voltage.
Optionally, the semiconductor memory further includes a p-type doped region located between the p-type base region and the n-type source region, and the p-type doped region and the n-type source region form a pn junction structure.
Optionally, the semiconductor memory further includes a source metal layer, the source metal layer is embedded into the p-type base region, and the source metal layer draws the p-type base region and the n-type source region to receive a source voltage.
Optionally, in the semiconductor memory of the present invention, the n-type source region extends downward to below the gate trench.
The invention provides a semiconductor memory:
firstly, a vertical current channel structure is adopted, and a long current channel structure can be realized under the condition that the size of a semiconductor memory device is not increased, so that the performance of the semiconductor memory device is ensured, and meanwhile, the small area of a semiconductor memory chip can be realized;
secondly, two floating gates are arranged in one gate groove, namely two storage units can be realized in one semiconductor memory unit cell, so that the storage density of the semiconductor memory is doubled;
and thirdly, the two floating gate structures are respectively positioned at two sides of the upper part of the gate trench and at two sides of the programming gate, and the floating gate structure, the programming gate structure and the control gate structure can be manufactured by a self-alignment process, so that the manufacturing process of the semiconductor memory is simple.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, a brief description is given below of the drawings used in describing the embodiments. It should be clear that the described figures are only views of some of the embodiments of the invention to be described, not all, and that for a person skilled in the art, other figures can be derived from these figures without inventive effort.
FIG. 1 is a schematic cross-sectional view of one embodiment of a semiconductor memory of the prior art;
FIG. 2 is a schematic cross-sectional view of a semiconductor memory according to a first embodiment of the present invention;
FIG. 3 is a cross-sectional view of a semiconductor memory according to a second embodiment of the present invention;
fig. 4 is a schematic cross-sectional structure diagram of a semiconductor memory according to a third embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, not all embodiments, and all other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without inventive efforts fall within the scope of the present invention.
It is to be understood that the terms "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof. Meanwhile, in order to clearly illustrate the embodiments of the present invention, the schematic diagrams listed in the drawings of the specification enlarge the thicknesses of the layers and regions of the present invention, and the sizes of the listed figures do not represent actual sizes; the drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure. The examples listed in the specification should not be limited to the specific shapes of the regions shown in the drawings of the specification, but include the resulting shapes such as deviations due to production and the like.
Fig. 2 is a schematic cross-sectional structure diagram of a semiconductor memory according to a first embodiment of the present invention. As shown in fig. 2, a semiconductor memory according to an embodiment of the present invention includes a semiconductor substrate 200, and the material of the semiconductor substrate 200 is typically silicon.
At least one gate trench 50 is formed in the semiconductor substrate 200, and fig. 2 exemplarily shows a 3-gate trench structure, and the gate trench 50 includes two parts, namely an upper part 51 of the gate trench 50 and a lower part 52 of the gate trench 50. An n-type drain region 22, a p-type base region 20 and an n-type source region 21 are formed in the semiconductor substrate 200 and located on two sides of the gate trench 50, the n-type source region 21 is located below the p-type base region 20, and the n-type drain region 22 is located above the p-type base region 20. The surface portion of the p-type base region 20 located between the n-type source region 21 and the n-type drain region 22 near the sidewall of the gate trench 50 is a current channel region of the semiconductor memory.
It should be noted that, when the semiconductor memory of the present invention is used to form a semiconductor memory array, the depth of the upper portion 51 of the gate trench 50 should be smaller than the depth of the shallow trench isolation structure in the semiconductor memory array (the shallow trench isolation structure is a common structure in the prior art, and is not described in detail in the embodiments of the present invention), and the depth of the lower portion 52 of the gate trench 50 should be larger than the depth of the shallow trench isolation structure in the semiconductor memory array.
The control gate 23 is located in the lower portion 52 of the gate trench 50, the programming gate 26 is located in the upper portion 51 of the gate trench 50 and above the control gate 23, the two floating gates 24 are located in the upper portion 51 of the gate trench 50 and located on two sides of the programming gate 26 respectively, and the floating gate 24, the control gate 23, the programming gate 26 and the semiconductor substrate 200 are separated by the insulating medium layer 25.
The insulating dielectric layer 25 is typically silicon oxide, and the floating gate 24, the control gate 23 and the program gate 26 are typically polysilicon.
Alternatively, the control gate 23 located in the lower portion 52 of the gate trench 50 may extend up to the upper portion 51 of the gate trench 50, such that the control gate 23 and the floating gate partially coincide in the current channel length direction, which is not specifically shown in the embodiments of the present invention.
In the length direction of the current channel, in the upper part 51 of the gate trench 50, the floating gate 24 covers the n-type drain region 22 and covers part of the p-type base region 20, and in the lower part of the gate trench 50, the control gate 23 covers the n-type source region 21 and covers part of the p-type base region 20, so that the floating gate 24 is used for controlling the opening and closing of a section of the current channel close to the n-type drain region 22 of the semiconductor memory of the invention, and the control gate 23 is used for controlling the opening and closing of a section of the current channel close to the n-type source region 21.
Alternatively, the n-type source region 21 may extend downward to below the gate trench 50, and this structure is not specifically shown in the embodiment of the present invention.
Alternatively, in a semiconductor memory of the present invention, the width of the upper portion 51 of the gate trench 50 may be greater than the width of the lower portion 52 of the gate trench 50, so that two floating gates 24 are respectively located at two sides of the upper portion 51 of the gate trench 50 and at a width position between the sidewall of the lower portion 52 of the gate trench 50 and the sidewall of the upper portion 51 of the gate trench 50, as shown in fig. 2.
The semiconductor memory of the invention is coupled with the floating gate 24 through the programming gate 26 and the overlapping part of the n-type drain region 22 and the floating gate 24, thereby ensuring that the floating gate 24 can be more effectively coupled with high potential.
The p-type base region in the semiconductor substrate in the prior art is usually grounded, and when the p-type base region of the semiconductor memory with the vertical current channel structure is grounded, an additional contact hole of the p-type base region needs to be added, so that the size of the semiconductor memory is increased, and the manufacturing difficulty of the semiconductor memory is increased.
Fig. 3 is a schematic cross-sectional structure diagram of a second embodiment of a semiconductor memory according to the present invention, and fig. 3 specifically shows a first structure of the semiconductor memory shown in fig. 2 when the p-type base region 20 and the n-type source region 21 are simultaneously connected to a source voltage, and as shown in fig. 3, the semiconductor memory according to the present invention further includes a source metal layer 29, wherein the source metal layer 29 draws the n-type source region 21 to the source voltage, and the source metal layer 29 is embedded in the p-type base region 20, so that the source metal layer 29 also draws the p-type base region 20 to the source voltage.
Fig. 4 is a schematic cross-sectional structure diagram of a third embodiment of a semiconductor memory according to the present invention, and fig. 4 shows a second structure of the semiconductor memory according to the present invention when a p-type base region 20 is connected to a source voltage, as shown in fig. 3, in the semiconductor memory according to the present invention, a p-type doped region 30 with a high doping concentration is further formed between the p-type base region 20 and an n-type source region 21, a pn junction structure is formed between the p-type doped region 30 and the n-type source region 21, tunneling occurs between the p-type doped region 30 with a high doping concentration and the n-type source region with a high doping concentration, that is, tunneling short circuit occurs between the n-type source region 21 and the p-type base region 20, so that when the n-type source region 21 is connected to a source voltage, the p-type base region 20 is. Therefore, the additional contact hole for leading out the p-type base region can be avoided, and the increase of the size of the semiconductor memory and the increase of the manufacturing difficulty of the semiconductor memory can be further avoided.
According to the semiconductor memory, firstly, the current channel region between the n-type source region and the n-type drain region is of a vertical current channel structure, so that a long current channel can be realized under the condition that the size of a semiconductor memory device is not increased, namely, the performance of the semiconductor memory is ensured, and meanwhile, the small chip area of the semiconductor memory can be realized; secondly, two floating gate structures are formed in the same gate trench, so that two storage units can be realized in one semiconductor memory cell, and the storage density of the semiconductor memory is doubled; and thirdly, the two floating gate structures are respectively positioned at two sides of the upper part of the gate trench and at two sides of the programming gate structure, and the floating gate structure, the programming gate structure and the control gate structure can be manufactured by a self-aligned process, so that the manufacturing process of the semiconductor memory is simple.
The above embodiments and examples are specific supports for the technical idea of the semiconductor memory proposed by the present invention, and the protection scope of the present invention is not limited thereby, and any equivalent changes or equivalent changes made on the basis of the technical solution according to the technical idea proposed by the present invention still belong to the protection scope of the technical solution of the present invention.
While embodiments of the invention have been described above, it is not limited to the applications set forth in the description and the embodiments, which are fully applicable in various fields of endeavor to which the invention pertains, and further modifications may readily be made by those skilled in the art, it being understood that the invention is not limited to the details shown and described herein without departing from the general concept defined by the appended claims and their equivalents.
Claims (8)
1. A semiconductor memory, comprising:
a semiconductor substrate, and located in the semiconductor substrate:
at least one gate trench;
the n-type drain region, the p-type base region and the n-type source region are respectively positioned on two sides of the gate trench from top to bottom;
a control gate located at a lower portion of the gate trench;
a program gate located on an upper portion of the gate trench and over the control gate;
the two floating gates are positioned at the upper part of the gate groove and positioned at two sides of the programming gate respectively;
the floating gate, the control gate, the programming gate and the semiconductor substrate are isolated by an insulating medium layer.
2. A semiconductor memory according to claim 1, wherein said control gate extends up to an upper portion of said gate trench.
3. A semiconductor memory according to claim 1, wherein a width of an upper portion of the gate trench is larger than a width of a lower portion of the gate trench.
4. A semiconductor memory according to claim 3, wherein the two floating gate structures are respectively located on both sides of the upper portion of the gate trench at a width position between the sidewall of the lower portion and the sidewall of the upper portion of the gate trench.
5. A semiconductor memory device according to claim 1, wherein said p-type base region and said n-type source region are both connected to a source voltage.
6. A semiconductor memory according to claim 5, further comprising a p-type doped region between said p-type base region and said n-type source region, said p-type doped region and said n-type source region forming a pn junction structure.
7. A semiconductor memory according to claim 5, further comprising a source metal layer embedded in said p-type base region, said source metal layer drawing said p-type base region and said n-type source region to a source voltage.
8. A semiconductor memory as in claim 1, wherein said n-type source region extends down to below said gate trench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811130401.3A CN110957324B (en) | 2018-09-27 | 2018-09-27 | Semiconductor memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811130401.3A CN110957324B (en) | 2018-09-27 | 2018-09-27 | Semiconductor memory |
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| CN110957324A true CN110957324A (en) | 2020-04-03 |
| CN110957324B CN110957324B (en) | 2022-05-17 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5399516A (en) * | 1992-03-12 | 1995-03-21 | International Business Machines Corporation | Method of making shadow RAM cell having a shallow trench EEPROM |
| US5616510A (en) * | 1992-11-02 | 1997-04-01 | Wong; Chun C. D. | Method for making multimedia storage system with highly compact memory cells |
| US6144064A (en) * | 1996-12-24 | 2000-11-07 | Samsung Electronics Co., Ltd. | Split-gate EEPROM device having floating gate with double polysilicon layer |
| CN102169896A (en) * | 2010-02-26 | 2011-08-31 | 苏州东微半导体有限公司 | Manufacturing method of groove-type power MOS (Metal Oxide Semiconductor) transistor |
| CN104952718A (en) * | 2015-06-12 | 2015-09-30 | 苏州东微半导体有限公司 | Manufacturing method of split-gate power device |
| CN104979355A (en) * | 2014-04-01 | 2015-10-14 | 苏州东微半导体有限公司 | Semi-floating-gate memory unit and semi-floating-gate memory array |
-
2018
- 2018-09-27 CN CN201811130401.3A patent/CN110957324B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5399516A (en) * | 1992-03-12 | 1995-03-21 | International Business Machines Corporation | Method of making shadow RAM cell having a shallow trench EEPROM |
| US5616510A (en) * | 1992-11-02 | 1997-04-01 | Wong; Chun C. D. | Method for making multimedia storage system with highly compact memory cells |
| US6144064A (en) * | 1996-12-24 | 2000-11-07 | Samsung Electronics Co., Ltd. | Split-gate EEPROM device having floating gate with double polysilicon layer |
| CN102169896A (en) * | 2010-02-26 | 2011-08-31 | 苏州东微半导体有限公司 | Manufacturing method of groove-type power MOS (Metal Oxide Semiconductor) transistor |
| CN104979355A (en) * | 2014-04-01 | 2015-10-14 | 苏州东微半导体有限公司 | Semi-floating-gate memory unit and semi-floating-gate memory array |
| CN104952718A (en) * | 2015-06-12 | 2015-09-30 | 苏州东微半导体有限公司 | Manufacturing method of split-gate power device |
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