US20140246720A1 - Integrated circuit protected from short circuits caused by silicide - Google Patents

Integrated circuit protected from short circuits caused by silicide Download PDF

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US20140246720A1
US20140246720A1 US14/194,345 US201414194345A US2014246720A1 US 20140246720 A1 US20140246720 A1 US 20140246720A1 US 201414194345 A US201414194345 A US 201414194345A US 2014246720 A1 US2014246720 A1 US 2014246720A1
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doped region
spacer
edge
transistor
gate structure
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US14/194,345
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Arnaud Regnier
Stephan Niel
Francesco La Rosa
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STMicroelectronics Rousset SAS
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STMicroelectronics Rousset SAS
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Assigned to STMICROELECTRONICS (ROUSSET) SAS reassignment STMICROELECTRONICS (ROUSSET) SAS ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NIEL, STEPHAN, REGNIER, ARNAUD, LA ROSA, FRANCESCO
Publication of US20140246720A1 publication Critical patent/US20140246720A1/en
Priority to US14/806,432 priority Critical patent/US9666484B2/en
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
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    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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Definitions

  • the present disclosure relates to an integrated circuit protected from short circuits caused by silicide, and to a method of fabricating such an integrated circuit.
  • FIG. 1 is a cross-sectional view of an integrated circuit IC comprising a pair of memory cells C 1 , C 2 .
  • Each memory cell C 1 , C 2 comprises a floating gate transistor FGT 1 , FGT 2 and a selection transistor ST 1 , ST 2 respectively in series.
  • the integrated circuit is formed in/on a substrate comprising a P-type doped well PW of a semiconductor wafer WF.
  • the well PW is isolated from the rest of the wafer WF by an N-doped isolation layer NISO that surrounds the entire well.
  • a trench 1 extends from the surface of the well PW to the isolation layer NISO.
  • the sidewalls and bottom of the trench 1 are covered by an isolating layer 2 (such as oxide) and the remaining volume of the trench is filled with a semiconductor material 3 , such as polycrystalline silicon or “polysilicon”.
  • a semiconductor material 3 such as polycrystalline silicon or “polysilicon”.
  • the floating gate transistors FGT 1 , FGT 2 are formed on opposite sides of the trench conductor CT, on the surface of the substrate.
  • Each floating gate transistor comprises a first doped region R 1 , a second doped region R 2 , a horizontal channel CH 1 , a transistor gate structure TGS, and spacers SP 1 , SP 2 .
  • Regions R 1 , R 2 are N-type doped and respectively comprise shallow lightly doped portions n 1 , n 2 and deeper higher doped portions n 1 ′, n 2 ′ respectively.
  • the first region R 1 extends in the well PW from a first edge E 1 of the transistor gate structure to the upper edge of the trench conductor CT, and forms the transistor source region (S).
  • the second region R 2 extends in the well PW from a second edge E 2 , opposite the first, of the transistor gate structure to an edge of a transistor gate structure of an adjacent memory cell (not shown), and forms the transistor drain region (D).
  • the channel CH 1 extends in the well PW between the regions R 1 , R 2 and has a length L 1 .
  • the transistor gate structure TGS is formed above the channel CH 1 and comprises a stack of a first oxide layer O 1 (tunnel oxide), a first polycrystalline silicon layer P 1 (floating gate FG), a second oxide layer O 2 (gate oxide), and a second polycrystalline layer P 2 (control gate CG).
  • the first spacer SP 1 is formed on the first edge E 1 of the gate structure TGS above the first doped region R 1
  • the second spacer SP 2 is formed on the second edge E 2 of the gate structure above the second doped region R 2 .
  • the selection transistors ST 1 , ST 2 each comprise the first doped region R 1 , a third doped region R 3 , the trench conductor CT, and a vertical channel CH 2 .
  • the region R 3 is N-type doped and formed in the layer NISO. Regions R 1 , R 3 respectively form the transistor drain (D) and source (S) regions of the selection transistors.
  • the semiconductor material 3 of the trench conductor CT forms a “buried” or “vertical” select gate SG that is common to both selection transistors ST 1 , ST 2 , with the isolating layer 2 forming a gate oxide.
  • the channels CH 2 extend in the well PW between the regions R 1 , R 3 , on opposite sides of the trench conductor CT, and have a length L 2 .
  • Silicides SI are formed on the top surfaces of the doped regions R 1 , R 2 , the semiconductor material 3 of the trench conductor CT, and the control gates CG.
  • a dielectric isolating material (not shown for the sake of clarity) covers the memory cells C 1 , C 2 .
  • the doped regions R 2 of transistors FGT 1 , FGT 2 are coupled to a metal track M 1 formed in a first metal layer or “metall” by means of a contact CN traversing the dielectric isolating material.
  • the metal track M 1 serves as a bitline
  • the layer NISO serves as a source line
  • the trench conductor CT serves as a wordline.
  • Another contact may be made to the semiconductor material 3 of the trench conductor for the application of wordline voltages. Additional pairs of memory cells extend to the left and the right of the figure, and are coupled to the same bitline and to different wordlines.
  • Shallow trench isolations or STI may be formed parallel to the plane of the figure, on opposite sides of the memory cells. These isolations separate columns of memory cells linked to adjacent bitlines.
  • Each memory cell C 1 , C 2 thus has a width (not shown) defined by the width of the doped regions plus two times half the distance of each shallow trench isolation.
  • Each memory cell C 1 , C 2 has a length defined by distances D 1 to D 5 .
  • Distance D 1 corresponds to the distance from the first edge E 1 of the transistor gate structure TGS to the upper edge of the trench conductor CT
  • distance D 2 corresponds to the distance from the second edge E 2 of the transistor gate structure TGS to the edge of the contact CN
  • distance D 3 corresponds to half the width of the trench conductor CT
  • distance D 4 corresponds to the length of the transistor gate structure TGS from edge to edge
  • distance D 5 corresponds to half the width of the contact CN.
  • the width of each cell is equal to 260 nm, for a total cell size of 0.96 micrometers squared.
  • a memory cell comprising a buried vertical gate thus provides a smaller surface area as compared to a conventional memory cell, wherein both the floating gate transistor and the selection transistor are formed on the surface of the substrate for a cell length of 715 nanometers. For a same width of 260 nm, the cell size is 0.18 micrometers squared for the same semiconductor fabrication technology.
  • Silicidation is commonly performed by a “self-aligned” silicide or “salicide” process in order to reduce resistance of the silicided areas R 1 , R 2 , CG, CT. Nevertheless, there is a high risk that a silicide short circuit or “bridge” will form above the isolating layer 2 between the doped regions R 1 and the semiconductor material 3 , in the encircled zones. This risk mainly arises due to the thin dimension, for example 10 nm or less, of the isolating layer 2 . Such a silicide short disrupts the operation of the memory cell.
  • Another solution is to form a silicidation protection feature covering only the encircled zone of the junction between the doped region R 1 , the isolating layer 2 , and the semiconductor material 3 .
  • this method also requires additional masks and processing steps, and may be difficult to implement due to minimum feature sizes and proper alignment.
  • Embodiments of the disclosure relate to an integrated circuit formed on a semiconductor substrate and comprising a trench conductor and a first transistor formed on the surface of the substrate.
  • the trench conductor comprises a trench formed in the substrate, an isolating layer on at least the sidewalls of the trench, and a semiconductor material filling the trench.
  • the transistor comprises: a transistor gate structure; a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor; and a first spacer formed on the first edge of the gate structure and above the first doped region.
  • the first spacer completely covers the first doped region and a silicide is present on the surface of the semiconductor material of the trench conductor but is not present on the surface of the first doped region.
  • the integrated circuit further comprises a second doped region extending in the substrate from a second edge, opposite of the first, of the gate structure; and a second spacer formed on the second edge of the gate structure and above the second doped region.
  • the trench conductor forms a buried gate of a second transistor
  • the integrated circuit further comprises a third doped region that extends along lower edges of the buried gate and forms a source or drain region of the second transistor, such that the second transistor has a vertical channel extending on one side of the buried gate, between the first and the third doped regions.
  • the first transistor is a charge storage transistor and the second transistor is a selection transistor, the transistors forming a first memory cell.
  • the integrated circuit further comprises a second memory cell comprising a charge storage transistor formed on the surface of the substrate on the opposite side of the trench conductor and a selection transistor comprising a vertical channel extending on an opposite side of the trench conductor, the trench conductor forming a common buried gate of the first and second memory cells.
  • a first distance between the first edge of the transistor gate structure and the upper edge of the trench conductor is approximately half a second distance between the second edge of the transistor gate structure and a contact formed to the second doped region.
  • the first spacer has a length greater than or equal to the first distance, and the second spacer has approximately the same length as the first spacer.
  • a first distance between the first edge of the transistor gate structure and the upper edge of the trench conductor is approximately equal a second distance between the second edge of the transistor gate structure and a contact formed to the second doped region.
  • the first spacer is approximately twice as long as the second spacer.
  • the first spacer is a double-spacer structure comprising a first portion that partially covers the first doped region and a second portion that covers the remainder of the first doped region.
  • the second doped region comprises a shallow, lightly doped portion and a deeper, more highly doped portion
  • the first doped region only comprises a shallow, lightly doped portion
  • a silicide is also present on at least one of the control gate and the second doped region.
  • Embodiments of the disclosure also relate to a device comprising an integrated circuit according to one embodiment.
  • Embodiments of the disclosure also relate to a method of fabricating an integrated circuit on a semiconductor substrate comprising the steps of: forming at least one trench in the substrate; forming an isolating layer on at least the sidewalls of the trench; filling the trench with a semiconductor material to form a trench conductor; forming a first transistor gate structure on the surface of the substrate; implanting a first doped region extending between a first edge of the gate structure and an upper edge of the trench conductor; forming a first spacer on the first edge of the gate structure and above the first doped region, wherein the first spacer completely covers the first doped region and prevents it from being silicided; and forming a silicide on the top surface of the semiconductor material of the trench conductor but not on the surface of the first doped region.
  • the method further comprises implanting a second doped region extending from a second edge, opposite of the first, of the gate structure; and forming a second spacer on the second edge of the gate structure and above the second doped region.
  • the trench conductor is a buried gate of a second transistor, the method further comprising the step of forming a third doped region extending along lower edges of the buried gate and forming a source or drain region of the second transistor, such that the second transistor has a vertical channel extending on one side of the buried gate, between the first and the third doped regions.
  • the steps of forming the spacers further comprise: forming a first spacer above the first doped region and a second spacer above the second region, wherein the first spacer only partially covers the first doped region; removing the second spacer; forming an additional first spacer covering the remainder of the first doped region; and forming an additional second spacer above the second doped region.
  • the step of forming the spacers comprises: depositing a uniform spacer layer; and patterning and etching the uniform spacer layer in order to form the first and second spacers.
  • the method further comprises a step of implanting dopants into the second doped region, without implanting dopants into the first doped region.
  • FIG. 1 previously described, is a cross-sectional view of a conventional integrated circuit
  • FIG. 2 is a cross-sectional view of an integrated circuit according to a first embodiment of the disclosure
  • FIGS. 3A to 3F are cross-sectional views of steps of a method of fabrication of an integrated circuit according to the first embodiment of the disclosure
  • FIG. 4 is a cross-sectional view of an integrated circuit according to a second embodiment of the disclosure.
  • FIGS. 5A to 5D are cross-sectional views of steps of a method of fabrication of an integrated circuit according to the second embodiment of the disclosure.
  • FIG. 6 is a cross-sectional view of an integrated circuit according to a third embodiment of the disclosure.
  • FIGS. 7A and 7B are cross-sectional views of steps of a method of fabrication of an integrated circuit according to the third embodiment of the disclosure.
  • FIG. 8 shows a device comprising an integrated circuit according to an embodiment of the disclosure.
  • the disclosure is based on the following mutually independent observations about the first doped regions R 1 of the integrated circuit shown in FIG. 1 : the length of the doped region R 1 may be reduced without adverse effects on the operation of the transistors; a second implantation of dopants to form the deeper higher doped portions n 1 ′ is not necessary; and it is not necessary to silicide the doped regions R 1 as they are relatively small and no contact is made thereto.
  • FIG. 2 is a cross-sectional view of an integrated circuit IC 1 according to a first embodiment of the disclosure.
  • the integrated circuit IC 1 comprises a pair of memory cells C 11 , C 12 , each comprising a floating gate transistor FGT 11 , FGT 12 and a selection transistor ST 11 , ST 12 respectively.
  • the structure of the memory cells C 11 , C 12 is similar to that of memory cells C 1 , C 2 , described in relation with FIG. 1 , with same references designating the same features.
  • the integrated circuit IC 1 shown in FIG. 2 differs from the integrated circuit IC shown in FIG. 1 in that the distance between the first edge E 1 of the transistor gate structure TGS and the upper edge of the trench conductor CT and has been reduced to a distance D 1 ′.
  • the layout parameters are adjusted during the conception of the integrated circuit IC 1 such that the distance D 1 ′ is equal to the width of the first spacer SP 1 to be formed above the first doped region R 1 .
  • the spacers SP 1 completely cover the doped regions R 1 , thereby preventing a silicide from forming on the doped regions R 1 ; consequently, a silicide short circuit cannot form between the doped region R 1 and the semiconductor material 3 of the trench conductor CT. Furthermore, silicides SI may still form on the semiconductor material 3 , control gates CG, and the second doped regions R 2 . Bitline and wordline contacts (not shown) may be made as desired to the doped region R 2 and to the trench conductor CT, and no additional masks or process steps are required. The distances D 2 , D 3 , D 4 , and D 5 (not shown in FIG. 2 ) are not modified but the overall cell size is further reduced with respect to that shown in FIG.
  • D 1 75/2 nm
  • D 2 75 nm
  • D 3 75 nm
  • D 4 100 nm
  • D 5 45 nm, for a total length of 332.5 nm, and a same width of 260 nm, for a cell size of 0.86 microns squared.
  • the spacers SP 1 completely cover the doped regions R 1 , deeper higher doped portions (n 1 ′ of FIG. 1 ) are not formed in the first doped regions R 1 . Consequently, the doped regions R 1 only comprise a shallow lightly doped portion n 1 , whereas the doped regions R 2 comprise both a shallow lightly doped portion n 2 and a deeper higher doped portion n 2 ′.
  • the vertical channels CH 2 between regions R 1 , R 3 of the selection transistors ST 11 , ST 12 have increased channel lengths L 2 ′.
  • the increased channel length L 2 ′ of the selection transistors helps prevent “punchthrough” due to parasitic current paths between the drain region R 1 and the source region R 3 of the selection transistors.
  • the first spacer SP 1 and the second spacer SP 2 are approximately the same length, within the variances of conventional semiconductor manufacturing procedures, for example ⁇ 5%, and the first distance D 1 ′ is approximately half the distance D 2 .
  • FIGS. 3A to 3E show cross-sectional views of steps of a method of fabrication of the integrated circuit IC 1 according to the first embodiment of the disclosure.
  • FIG. 3A shows preliminary steps S 1 , comprising:
  • FIG. 3B shows a step S 2 , wherein a first implantation of N-type dopants into the top surface of the wafer WF is performed.
  • the first doped regions R 1 are formed between the edges of the transistor gate structure TGS and the upper edges of the trench conductor CT, and the second doped regions R 2 are formed between the edges of adjacent transistor gate structures without a trench conductor therebetween. Regions R 1 , R 2 each comprise shallow lightly doped portions.
  • FIG. 3C shows a step S 3 , wherein a spacer layer SL 1 , such as silicon dioxide SiO2, is deposited in a conformal manner on the top surface of the wafer WF.
  • the spacer layer SL 1 covers the transistor gate structures TGS, the doped regions R 1 , R 2 , and the trench conductors CT.
  • FIG. 3D shows a step S 4 , wherein the spacer layer SL 1 is etched by means of an anisotropic process to form the spacers SP 1 , SP 2 on the edges of the transistor gate structures TGS. It may be noted in FIG. 3D that the spacers SP 1 completely cover the doped regions R 1 , whereas the spacers SP 2 do not completely cover the doped regions R 2 , thus allowing a second implantation of the doped regions R 2 .
  • FIG. 3E shows a step S 5 , wherein a second implantation of N-type dopants into the top surface of the wafer is performed.
  • the second doped regions R 2 now further comprise a deeper higher doped portion.
  • the first doped regions R 1 are not implanted a second time, as they are covered by the spacers SP 1 .
  • FIG. 3F shows a step S 6 , wherein the top surface of the wafer WF is silicided, either by direct deposition or by deposition and reaction in a self-aligned process.
  • the surfaces of the semiconductor material 3 in the trench conductor CT, the doped regions R 2 , and the control gates CG are thus covered by silicide SI.
  • silicide SI it may be noted in FIG. 3F that no silicide forms on the first doped regions R 1 , which are protected by the spacers SP 1 .
  • no silicide short occurs between the doped regions R 1 and the semiconductor material 3 of the trench conductor CT.
  • FIG. 4 is a cross-sectional view of an integrated circuit IC 2 according to a second embodiment of the disclosure.
  • the integrated circuit IC 2 comprises a pair of memory cells C 11 , C 12 , each comprising a floating gate transistor FGT 11 , FGT 12 and a selection transistor ST 11 , ST 12 respectively.
  • the structure of the memory cells C 11 , C 12 is similar to that of memory cells C 1 , C 2 , described in relation with FIG. 1 , with same references designating the same features.
  • Integrated circuit IC 2 differs from the integrated circuit IC 1 shown in FIG. 2 in that rather than the distance between the first edge E 1 of the transistor gate structure TGS and the edge of the trench conductor CT being reduced to the size of a spacer, the size of the spacer is increased to the distance between the first edge E 1 of the transistor gate structure TGS and the edge of the trench conductor CT. Thus, a large first spacer SP 11 is formed that completely covers the first doped region R 1 .
  • the spacer SP 11 is of the “double-spacer” type, and comprises a first spacer SP 1 that only partially covers the first doped region R 1 , for example half of the distance D 1 , and an additional spacer SP 1 ′ that covers the remainder of the first doped region R 1 , that is to say, from the outer edge of the first spacer SP 1 to the edge of the doped region.
  • FIGS. 5A to 5D show cross-sectional views of steps of a method of fabrication of the integrated circuit IC 2 according to the second embodiment of the disclosure.
  • the fabrication steps S 1 to S 4 as shown and described in relation with FIGS. 3A to 3D were performed, with the exception that the spacer SP 1 only partially covers the doped region R 1 .
  • FIG. 5A shows a step S 7 , wherein a mask layer ML 1 is deposited over the top surface of the wafer WF.
  • the mask layer ML 1 is then patterned to expose the spacers SP 2 and to cover the spacers SP 1 .
  • FIG. 5B shows a step S 8 , wherein the spacers SP 2 are removed, then the mask layer ML 1 is removed.
  • the first spacers SP 1 remain, partially covering the first doped regions R 1 .
  • a spacer layer SL 2 such as silicon dioxide SiO2, is then deposited in a conformal manner on the top surface of the wafer WF, covering the transistor gate structures TGS, the spacers SP 1 , the doped regions R 1 , R 2 , and the trench conductors CT.
  • FIG. 5C shows a step S 9 , wherein the spacer layer SL 2 is etched in an anisotropic manner, forming the additional spacers SP 1 ′, SP 2 ′.
  • the spacer SP 1 ′ extends from the edge of the first spacer SP 1 to the edge of the first doped region R 1 , such that the doped region R 1 is completely covered by the double-spacer structure SP 1 , SP 1 ′.
  • the second spacer SP 2 ′ extends from the second edge of the transistor gate structure above the second doped region R 2 .
  • a second dopant implantation is then performed, wherein dopants implanted in the second doped region R 2 are self-aligned with the edges of the second spacers SP 2 ′.
  • the first doped regions R 1 are protected from a second implantation by the double spacer structure SP 1 , SP 1 ′. It may be noted that if it is nevertheless desired to form a deeper highly doped portion of region R 1 , the second implantation may be performed before the step shown in FIG. 5A , in order to implant both regions R 1 , R 2 .
  • FIG. 5D shows a step S 10 , wherein the top surface of the wafer WF is silicided, either by direct deposition or by deposition and reaction in a self-aligned process.
  • the surfaces of the semiconductor material 3 in the trench conductor CT, the doped regions R 2 , and the control gates CG are thus covered by silicide SI.
  • silicide SI it may be noted in FIG. 5D that no silicide forms on the first doped regions R 1 , which are protected by the first spacers. Thus, no silicide short occurs between the doped regions R 1 and the semiconductor material 3 of the trench conductor CT.
  • FIG. 6 is a cross-sectional view of an integrated circuit IC 3 according to a third embodiment of the disclosure.
  • the integrated circuit IC 3 comprises a pair of memory cells C 11 , C 12 , each comprising a floating gate transistor FGT 11 , FGT 12 and a selection transistor ST 11 , ST 12 respectively.
  • the structure of the memory cells C 11 , C 12 is similar to that of memory cells C 1 , C 2 , described in relation with FIG. 1 , with same references designating the same features.
  • Integrated circuit IC 3 differs from the integrated circuit IC 1 shown in FIG. 2 in that rather than the distance between the first edge E 1 of the transistor gate structure TGS and the edge of the trench conductor CT being reduced, a large first spacer SP 21 is formed that completely covers the first doped region R 1 .
  • a spacer SP 22 is formed on the opposite side, partially covering the second doped region R 2 such that a second implantation of dopants may be performed in doped region R 2 .
  • FIGS. 7A and 7B show cross-sectional views of steps of fabricating an integrated circuit IC 3 according to the third embodiment of the disclosure. Prior to the step shown in FIG. 7A , the fabrication steps S 1 and S 2 as shown and described in relation with FIGS. 3A and 3B were performed.
  • FIG. 7A shows a step S 11 , wherein a spacer layer SL 3 is deposited in a uniform manner over the top surface of the wafer WF, covering the transistor gate structures TGS, the doped regions R 1 , R 2 , and the trench conductors CT. A mask layer ML 2 is then deposited over the spacer layer SL 3 .
  • FIG. 7B shows a step S 12 , wherein the mask layer ML 2 is patterned and etched, followed by an etching of the spacer layer SL 3 .
  • the mask layer ML 2 is then removed and the spacer layer material SL 3 extending above the transistor gate structures is removed.
  • the second implantation of dopants in the doped regions R 2 is then performed, followed by silicidation of the wafer.
  • FIG. 8 shows an application example of a device DV according to embodiments of the disclosure.
  • the device DV comprises a memory MEM, which in turn comprises an integrated circuit IC′ (IC 1 , IC 2 , IC 3 ) according to an embodiment of the disclosure.
  • the device DV may further comprise a processor and a communication interface circuit.
  • the device may be a portable device such as a mobile telephone, a chipcard, etc.
  • the disclosure has been described in relation with a pair of memory cells C 11 , C 12 , each comprising a floating gate transistor and a selection transistor, wherein the selection transistors comprise a common buried gate, the disclosure is not limited to such an application.
  • the disclosure is indeed applicable to a memory cell comprising a selection transistor not having its buried gate in common with that of another selection transistor.
  • the disclosure is further applicable to any transistor formed adjacent to a trench conductor, with a thin oxide layer separating a doped region of the transistor and a semiconductor material of the trench, wherein a risk of a silicide short exists between the doped region and the semiconductor material.
  • the length of the spacer SP 1 , SP 11 , SP 21 formed above the first doped region R 1 is equal to or greater than the distance D 1 , D 1 ′ between the first edge E 1 of the transistor gate structure TGS and the upper edge of the trench conductor CT.
  • the outer edge of the first spacer SP 1 , SP 11 , SP 21 may extend beyond the junction of the doped region R 1 and the trench conductor CT such that it slightly overlaps the isolating layer 2 or the semiconductor material 3 . This may be the unavoidable result of the spacer formation process, or deliberate to ensure that the doped region R 1 is completely covered despite any variances of the semiconductor fabrication process.
  • N-type doped regions R 1 , R 2 , R 3 , NISO, and a P-type doped well PW it is equally applicable to P-type doped regions R 1 , R 2 , R 3 , a P-doped isolation layer, and an N-type doped well.
  • the transistors formed on the surface of the substrate have been described as floating gate or “charge storage” transistors, they may instead simply comprise a control gate and a gate oxide, or comprise for example silicon nanocrystals instead of a floating gate of polysilicon material.
  • the doped regions R 1 , R 2 may extend slightly beneath the transistor gate structure TGS rather than stopping exactly at the edge of the gate structure. This may be due for example to a tilted implantation process.
  • spacers SP 2 may be left in place over the doped region R 2 . Consequently, a double-spacer may be formed on both sides of the transistor gate structure.

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Abstract

An integrated circuit is formed on a semiconductor substrate and includes a trench conductor and a first transistor formed on the surface of the substrate. The transistor includes: a transistor gate structure, a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor, and a first spacer formed on the first edge of the gate structure and above the first doped region. The first spacer completely covers the first doped region and a silicide is present on the trench conductor but is not present on the surface of the first doped region.

Description

    BACKGROUND
  • 1. Technical Field
  • The present disclosure relates to an integrated circuit protected from short circuits caused by silicide, and to a method of fabricating such an integrated circuit.
  • 2. Detailed Description
  • FIG. 1 is a cross-sectional view of an integrated circuit IC comprising a pair of memory cells C1, C2. Each memory cell C1, C2 comprises a floating gate transistor FGT1, FGT2 and a selection transistor ST1, ST2 respectively in series. The integrated circuit is formed in/on a substrate comprising a P-type doped well PW of a semiconductor wafer WF. The well PW is isolated from the rest of the wafer WF by an N-doped isolation layer NISO that surrounds the entire well.
  • A trench 1 extends from the surface of the well PW to the isolation layer NISO. The sidewalls and bottom of the trench 1 are covered by an isolating layer 2 (such as oxide) and the remaining volume of the trench is filled with a semiconductor material 3, such as polycrystalline silicon or “polysilicon”. Together, the trench 1, isolating layer 2, and conductive material 3 form a trench conductor CT.
  • The floating gate transistors FGT1, FGT2 are formed on opposite sides of the trench conductor CT, on the surface of the substrate. Each floating gate transistor comprises a first doped region R1, a second doped region R2, a horizontal channel CH1, a transistor gate structure TGS, and spacers SP1, SP2.
  • Regions R1, R2 are N-type doped and respectively comprise shallow lightly doped portions n1, n2 and deeper higher doped portions n1′, n2′ respectively. The first region R1 extends in the well PW from a first edge E1 of the transistor gate structure to the upper edge of the trench conductor CT, and forms the transistor source region (S). The second region R2 extends in the well PW from a second edge E2, opposite the first, of the transistor gate structure to an edge of a transistor gate structure of an adjacent memory cell (not shown), and forms the transistor drain region (D). The channel CH1 extends in the well PW between the regions R1, R2 and has a length L1.
  • The transistor gate structure TGS is formed above the channel CH1 and comprises a stack of a first oxide layer O1 (tunnel oxide), a first polycrystalline silicon layer P1 (floating gate FG), a second oxide layer O2 (gate oxide), and a second polycrystalline layer P2 (control gate CG). The first spacer SP1 is formed on the first edge E1 of the gate structure TGS above the first doped region R1, and the second spacer SP2 is formed on the second edge E2 of the gate structure above the second doped region R2.
  • The selection transistors ST1, ST2 each comprise the first doped region R1, a third doped region R3, the trench conductor CT, and a vertical channel CH2. The region R3 is N-type doped and formed in the layer NISO. Regions R1, R3 respectively form the transistor drain (D) and source (S) regions of the selection transistors. The semiconductor material 3 of the trench conductor CT forms a “buried” or “vertical” select gate SG that is common to both selection transistors ST1, ST2, with the isolating layer 2 forming a gate oxide. The channels CH2 extend in the well PW between the regions R1, R3, on opposite sides of the trench conductor CT, and have a length L2.
  • Silicides SI are formed on the top surfaces of the doped regions R1, R2, the semiconductor material 3 of the trench conductor CT, and the control gates CG. A dielectric isolating material (not shown for the sake of clarity) covers the memory cells C1, C2. The doped regions R2 of transistors FGT1, FGT2 are coupled to a metal track M1 formed in a first metal layer or “metall” by means of a contact CN traversing the dielectric isolating material.
  • The metal track M1 serves as a bitline, the layer NISO serves as a source line, and the trench conductor CT serves as a wordline. Another contact (not shown) may be made to the semiconductor material 3 of the trench conductor for the application of wordline voltages. Additional pairs of memory cells extend to the left and the right of the figure, and are coupled to the same bitline and to different wordlines.
  • Shallow trench isolations or STI (not shown) may be formed parallel to the plane of the figure, on opposite sides of the memory cells. These isolations separate columns of memory cells linked to adjacent bitlines. Each memory cell C1, C2 thus has a width (not shown) defined by the width of the doped regions plus two times half the distance of each shallow trench isolation.
  • Each memory cell C1, C2 has a length defined by distances D1 to D5. Distance D1 corresponds to the distance from the first edge E1 of the transistor gate structure TGS to the upper edge of the trench conductor CT, distance D2 corresponds to the distance from the second edge E2 of the transistor gate structure TGS to the edge of the contact CN, distance D3 corresponds to half the width of the trench conductor CT, distance D4 corresponds to the length of the transistor gate structure TGS from edge to edge, and distance D5 corresponds to half the width of the contact CN.
  • As a numerical example, for a semiconductor fabrication technology of 90 nm, distances D1=D2=75 nm, D3=75 nm, D4=100 nm, and D5=45 nm for a total cell length of 370 nm. The width of each cell is equal to 260 nm, for a total cell size of 0.96 micrometers squared.
  • A memory cell comprising a buried vertical gate thus provides a smaller surface area as compared to a conventional memory cell, wherein both the floating gate transistor and the selection transistor are formed on the surface of the substrate for a cell length of 715 nanometers. For a same width of 260 nm, the cell size is 0.18 micrometers squared for the same semiconductor fabrication technology.
  • Silicidation is commonly performed by a “self-aligned” silicide or “salicide” process in order to reduce resistance of the silicided areas R1, R2, CG, CT. Nevertheless, there is a high risk that a silicide short circuit or “bridge” will form above the isolating layer 2 between the doped regions R1 and the semiconductor material 3, in the encircled zones. This risk mainly arises due to the thin dimension, for example 10 nm or less, of the isolating layer 2. Such a silicide short disrupts the operation of the memory cell.
  • One solution to prevent such silicide shorts is to mask the doped region R1 and the semiconductor material 3, such that no silicide forms on these surfaces. Consequently, only the doped regions R2 and the control gates CG are silicided. Nevertheless, this method requires an additional mask and processing steps, and leaves the doped region R1 and the semiconductor material 3 un-silicided. Accordingly, contacts cannot be made to the trench conductor CT between the memory cells C1, C2 and must be placed at the exterior of an array of memory cells. Further, the resistance of the semiconductor material 3 is greatly increased, such that the total length of the trench conductor is reduced.
  • Another solution is to form a silicidation protection feature covering only the encircled zone of the junction between the doped region R1, the isolating layer 2, and the semiconductor material 3. However, this method also requires additional masks and processing steps, and may be difficult to implement due to minimum feature sizes and proper alignment.
  • Yet another solution is to silicide the top surface of the semiconductor material 3 before forming the floating gate transistors. Nevertheless, the silicidation process is generally performed during the “back end of line” processing, once the transistors have been completed, in order to avoid contamination of the transistors.
    • BRIEF SUMMARY
  • It may therefore be desired to provide an alternative method for preventing a silicide short circuit between two semiconductor regions.
  • Embodiments of the disclosure relate to an integrated circuit formed on a semiconductor substrate and comprising a trench conductor and a first transistor formed on the surface of the substrate. The trench conductor comprises a trench formed in the substrate, an isolating layer on at least the sidewalls of the trench, and a semiconductor material filling the trench. The transistor comprises: a transistor gate structure; a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor; and a first spacer formed on the first edge of the gate structure and above the first doped region. According to one embodiment, the first spacer completely covers the first doped region and a silicide is present on the surface of the semiconductor material of the trench conductor but is not present on the surface of the first doped region.
  • According to one embodiment, the integrated circuit further comprises a second doped region extending in the substrate from a second edge, opposite of the first, of the gate structure; and a second spacer formed on the second edge of the gate structure and above the second doped region.
  • According to one embodiment, the trench conductor forms a buried gate of a second transistor, and the integrated circuit further comprises a third doped region that extends along lower edges of the buried gate and forms a source or drain region of the second transistor, such that the second transistor has a vertical channel extending on one side of the buried gate, between the first and the third doped regions.
  • According to one embodiment, the first transistor is a charge storage transistor and the second transistor is a selection transistor, the transistors forming a first memory cell.
  • According to one embodiment, the integrated circuit further comprises a second memory cell comprising a charge storage transistor formed on the surface of the substrate on the opposite side of the trench conductor and a selection transistor comprising a vertical channel extending on an opposite side of the trench conductor, the trench conductor forming a common buried gate of the first and second memory cells.
  • According to one embodiment, a first distance between the first edge of the transistor gate structure and the upper edge of the trench conductor is approximately half a second distance between the second edge of the transistor gate structure and a contact formed to the second doped region.
  • According to one embodiment, the first spacer has a length greater than or equal to the first distance, and the second spacer has approximately the same length as the first spacer.
  • According to one embodiment, a first distance between the first edge of the transistor gate structure and the upper edge of the trench conductor is approximately equal a second distance between the second edge of the transistor gate structure and a contact formed to the second doped region.
  • According to one embodiment, the first spacer is approximately twice as long as the second spacer.
  • According to one embodiment, the first spacer is a double-spacer structure comprising a first portion that partially covers the first doped region and a second portion that covers the remainder of the first doped region.
  • According to one embodiment, the second doped region comprises a shallow, lightly doped portion and a deeper, more highly doped portion, and the first doped region only comprises a shallow, lightly doped portion.
  • According to one embodiment, a silicide is also present on at least one of the control gate and the second doped region.
  • Embodiments of the disclosure also relate to a device comprising an integrated circuit according to one embodiment.
  • Embodiments of the disclosure also relate to a method of fabricating an integrated circuit on a semiconductor substrate comprising the steps of: forming at least one trench in the substrate; forming an isolating layer on at least the sidewalls of the trench; filling the trench with a semiconductor material to form a trench conductor; forming a first transistor gate structure on the surface of the substrate; implanting a first doped region extending between a first edge of the gate structure and an upper edge of the trench conductor; forming a first spacer on the first edge of the gate structure and above the first doped region, wherein the first spacer completely covers the first doped region and prevents it from being silicided; and forming a silicide on the top surface of the semiconductor material of the trench conductor but not on the surface of the first doped region.
  • According to one embodiment, the method further comprises implanting a second doped region extending from a second edge, opposite of the first, of the gate structure; and forming a second spacer on the second edge of the gate structure and above the second doped region.
  • According to one embodiment, the trench conductor is a buried gate of a second transistor, the method further comprising the step of forming a third doped region extending along lower edges of the buried gate and forming a source or drain region of the second transistor, such that the second transistor has a vertical channel extending on one side of the buried gate, between the first and the third doped regions.
  • According to one embodiment, the steps of forming the spacers further comprise: forming a first spacer above the first doped region and a second spacer above the second region, wherein the first spacer only partially covers the first doped region; removing the second spacer; forming an additional first spacer covering the remainder of the first doped region; and forming an additional second spacer above the second doped region.
  • According to one embodiment, the step of forming the spacers comprises: depositing a uniform spacer layer; and patterning and etching the uniform spacer layer in order to form the first and second spacers.
  • According to one embodiment, the method further comprises a step of implanting dopants into the second doped region, without implanting dopants into the first doped region.
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • Embodiments of an integrated circuit and a method of fabricating such an integrated circuit according to the disclosure will be described in the following in a non-limiting manner, in relation with the appended drawings in which:
  • FIG. 1, previously described, is a cross-sectional view of a conventional integrated circuit,
  • FIG. 2 is a cross-sectional view of an integrated circuit according to a first embodiment of the disclosure,
  • FIGS. 3A to 3F are cross-sectional views of steps of a method of fabrication of an integrated circuit according to the first embodiment of the disclosure,
  • FIG. 4 is a cross-sectional view of an integrated circuit according to a second embodiment of the disclosure,
  • FIGS. 5A to 5D are cross-sectional views of steps of a method of fabrication of an integrated circuit according to the second embodiment of the disclosure,
  • FIG. 6 is a cross-sectional view of an integrated circuit according to a third embodiment of the disclosure,
  • FIGS. 7A and 7B are cross-sectional views of steps of a method of fabrication of an integrated circuit according to the third embodiment of the disclosure, and
  • FIG. 8 shows a device comprising an integrated circuit according to an embodiment of the disclosure.
    •  DETAILED DESCRIPTION
  • The disclosure is based on the following mutually independent observations about the first doped regions R1 of the integrated circuit shown in FIG. 1: the length of the doped region R1 may be reduced without adverse effects on the operation of the transistors; a second implantation of dopants to form the deeper higher doped portions n1′ is not necessary; and it is not necessary to silicide the doped regions R1 as they are relatively small and no contact is made thereto.
  • FIG. 2 is a cross-sectional view of an integrated circuit IC 1 according to a first embodiment of the disclosure. The integrated circuit IC 1 comprises a pair of memory cells C11, C12, each comprising a floating gate transistor FGT11, FGT12 and a selection transistor ST11, ST12 respectively. The structure of the memory cells C11, C12 is similar to that of memory cells C1, C2, described in relation with FIG. 1, with same references designating the same features.
  • The integrated circuit IC1 shown in FIG. 2 differs from the integrated circuit IC shown in FIG. 1 in that the distance between the first edge E1 of the transistor gate structure TGS and the upper edge of the trench conductor CT and has been reduced to a distance D1′. In particular, the layout parameters are adjusted during the conception of the integrated circuit IC1 such that the distance D1′ is equal to the width of the first spacer SP1 to be formed above the first doped region R1.
  • Consequently, the spacers SP1 completely cover the doped regions R1, thereby preventing a silicide from forming on the doped regions R1; consequently, a silicide short circuit cannot form between the doped region R1 and the semiconductor material 3 of the trench conductor CT. Furthermore, silicides SI may still form on the semiconductor material 3, control gates CG, and the second doped regions R2. Bitline and wordline contacts (not shown) may be made as desired to the doped region R2 and to the trench conductor CT, and no additional masks or process steps are required. The distances D2, D3, D4, and D5 (not shown in FIG. 2) are not modified but the overall cell size is further reduced with respect to that shown in FIG. 1. As a numerical example, D1=75/2 nm, D2=75 nm, D3=75 nm, D4=100 nm, D5=45 nm, for a total length of 332.5 nm, and a same width of 260 nm, for a cell size of 0.86 microns squared.
  • Additionally, as the spacers SP1 completely cover the doped regions R1, deeper higher doped portions (n1′ of FIG. 1) are not formed in the first doped regions R1. Consequently, the doped regions R1 only comprise a shallow lightly doped portion n1, whereas the doped regions R2 comprise both a shallow lightly doped portion n2 and a deeper higher doped portion n2′. As a result, the vertical channels CH2 between regions R1, R3 of the selection transistors ST11, ST12 have increased channel lengths L2′. The increased channel length L2′ of the selection transistors helps prevent “punchthrough” due to parasitic current paths between the drain region R1 and the source region R3 of the selection transistors.
  • Furthermore, in this embodiment, the first spacer SP1 and the second spacer SP2 are approximately the same length, within the variances of conventional semiconductor manufacturing procedures, for example ±5%, and the first distance D1′ is approximately half the distance D2.
  • FIGS. 3A to 3E show cross-sectional views of steps of a method of fabrication of the integrated circuit IC 1 according to the first embodiment of the disclosure.
  • FIG. 3A shows preliminary steps S1, comprising:
      • implanting the N-doped isolation layer NISO in the wafer WF to delimit the P-type well PW;
      • forming the doped region R3 (not shown in the following figures) in the layer NISO;
      • implanting (optional) a P-doped layer in the well PW, above the layer NISO, to adjust the threshold voltages of the selection transistors ST11, ST12;
      • etching the trenches 1 from the top surface of the substrate sufficiently deep to reach the layer NISO;
      • depositing the isolating layer 2 on the sidewalls and bottom of the trenches 1;
      • filling the trenches 1 with the semiconductor material 3, such as a first polycrystalline silicon or “poly1” layer;
      • forming the tunnel oxides on the surface of the substrate PW by depositing and etching the first oxide layer O1, for example of the silicon dioxide SiO2 type;
      • forming the floating gates FG above the tunnel oxides by depositing and etching the first polycrystalline silicon or “poly1” layer P1;
      • forming the gate oxides above the floating gates FG by depositing and etching the second oxide layer O2, for example of the ONO (Oxide-Nitride-Oxide) type; and
      • forming the control gates CG above the gate oxides by depositing and etching the second polycrystalline silicon or “poly2” layer P2.
  • It will be understood by the skilled person that several of these steps may be performed in a different order or conjointly according to conventional semiconductor fabrication methods, such as the etching of more than one layer at a time.
  • FIG. 3B shows a step S2, wherein a first implantation of N-type dopants into the top surface of the wafer WF is performed. The first doped regions R1 are formed between the edges of the transistor gate structure TGS and the upper edges of the trench conductor CT, and the second doped regions R2 are formed between the edges of adjacent transistor gate structures without a trench conductor therebetween. Regions R1, R2 each comprise shallow lightly doped portions.
  • FIG. 3C shows a step S3, wherein a spacer layer SL1, such as silicon dioxide SiO2, is deposited in a conformal manner on the top surface of the wafer WF. The spacer layer SL1 covers the transistor gate structures TGS, the doped regions R1, R2, and the trench conductors CT.
  • FIG. 3D shows a step S4, wherein the spacer layer SL1 is etched by means of an anisotropic process to form the spacers SP1, SP2 on the edges of the transistor gate structures TGS. It may be noted in FIG. 3D that the spacers SP1 completely cover the doped regions R1, whereas the spacers SP2 do not completely cover the doped regions R2, thus allowing a second implantation of the doped regions R2.
  • FIG. 3E shows a step S5, wherein a second implantation of N-type dopants into the top surface of the wafer is performed. The second doped regions R2 now further comprise a deeper higher doped portion. The first doped regions R1 are not implanted a second time, as they are covered by the spacers SP1.
  • FIG. 3F shows a step S6, wherein the top surface of the wafer WF is silicided, either by direct deposition or by deposition and reaction in a self-aligned process. The surfaces of the semiconductor material 3 in the trench conductor CT, the doped regions R2, and the control gates CG are thus covered by silicide SI. It may be noted in FIG. 3F that no silicide forms on the first doped regions R1, which are protected by the spacers SP1. Thus, no silicide short occurs between the doped regions R1 and the semiconductor material 3 of the trench conductor CT.
  • FIG. 4 is a cross-sectional view of an integrated circuit IC2 according to a second embodiment of the disclosure. The integrated circuit IC2 comprises a pair of memory cells C11, C12, each comprising a floating gate transistor FGT11, FGT12 and a selection transistor ST11, ST12 respectively. The structure of the memory cells C11, C12 is similar to that of memory cells C1, C2, described in relation with FIG. 1, with same references designating the same features.
  • Integrated circuit IC2 differs from the integrated circuit IC1 shown in FIG. 2 in that rather than the distance between the first edge E1 of the transistor gate structure TGS and the edge of the trench conductor CT being reduced to the size of a spacer, the size of the spacer is increased to the distance between the first edge E1 of the transistor gate structure TGS and the edge of the trench conductor CT. Thus, a large first spacer SP11 is formed that completely covers the first doped region R1. The spacer SP11 is of the “double-spacer” type, and comprises a first spacer SP1 that only partially covers the first doped region R1, for example half of the distance D1, and an additional spacer SP1′ that covers the remainder of the first doped region R1, that is to say, from the outer edge of the first spacer SP1 to the edge of the doped region. A second spacer SP2′ is formed above the second doped region R2. Consequently, in this embodiment, distance D1=D2, and the other distances D3, D4, and D5 (not shown in FIG. 4) are not modified.
  • FIGS. 5A to 5D show cross-sectional views of steps of a method of fabrication of the integrated circuit IC2 according to the second embodiment of the disclosure. Prior to the step shown in FIG. 5A, the fabrication steps S1 to S4 as shown and described in relation with FIGS. 3A to 3D were performed, with the exception that the spacer SP1 only partially covers the doped region R1.
  • FIG. 5A shows a step S7, wherein a mask layer ML1 is deposited over the top surface of the wafer WF. The mask layer ML1 is then patterned to expose the spacers SP2 and to cover the spacers SP1.
  • FIG. 5B shows a step S8, wherein the spacers SP2 are removed, then the mask layer ML1 is removed. The first spacers SP1 remain, partially covering the first doped regions R1. A spacer layer SL2, such as silicon dioxide SiO2, is then deposited in a conformal manner on the top surface of the wafer WF, covering the transistor gate structures TGS, the spacers SP1, the doped regions R1, R2, and the trench conductors CT.
  • FIG. 5C shows a step S9, wherein the spacer layer SL2 is etched in an anisotropic manner, forming the additional spacers SP1′, SP2′. The spacer SP1′ extends from the edge of the first spacer SP1 to the edge of the first doped region R1, such that the doped region R1 is completely covered by the double-spacer structure SP1, SP1′. The second spacer SP2′ extends from the second edge of the transistor gate structure above the second doped region R2. A second dopant implantation is then performed, wherein dopants implanted in the second doped region R2 are self-aligned with the edges of the second spacers SP2′. The first doped regions R1 are protected from a second implantation by the double spacer structure SP1, SP1′. It may be noted that if it is nevertheless desired to form a deeper highly doped portion of region R1, the second implantation may be performed before the step shown in FIG. 5A, in order to implant both regions R1, R2.
  • FIG. 5D shows a step S10, wherein the top surface of the wafer WF is silicided, either by direct deposition or by deposition and reaction in a self-aligned process. The surfaces of the semiconductor material 3 in the trench conductor CT, the doped regions R2, and the control gates CG are thus covered by silicide SI. It may be noted in FIG. 5D that no silicide forms on the first doped regions R1, which are protected by the first spacers. Thus, no silicide short occurs between the doped regions R1 and the semiconductor material 3 of the trench conductor CT.
  • FIG. 6 is a cross-sectional view of an integrated circuit IC3 according to a third embodiment of the disclosure. The integrated circuit IC3 comprises a pair of memory cells C11, C12, each comprising a floating gate transistor FGT11, FGT12 and a selection transistor ST11, ST12 respectively. The structure of the memory cells C11, C12 is similar to that of memory cells C1, C2, described in relation with FIG. 1, with same references designating the same features.
  • Integrated circuit IC3 differs from the integrated circuit IC1 shown in FIG. 2 in that rather than the distance between the first edge E1 of the transistor gate structure TGS and the edge of the trench conductor CT being reduced, a large first spacer SP21 is formed that completely covers the first doped region R1. A spacer SP22 is formed on the opposite side, partially covering the second doped region R2 such that a second implantation of dopants may be performed in doped region R2. Spacer SP21 is significantly longer than spacer SP22, for example twice as long. Consequently, in this embodiment, distance D1=D2, and the other distances D3, D4, and D5 (not shown in FIG. 6) are not modified.
  • FIGS. 7A and 7B show cross-sectional views of steps of fabricating an integrated circuit IC3 according to the third embodiment of the disclosure. Prior to the step shown in FIG. 7A, the fabrication steps S1 and S2 as shown and described in relation with FIGS. 3A and 3B were performed.
  • FIG. 7A shows a step S11, wherein a spacer layer SL3 is deposited in a uniform manner over the top surface of the wafer WF, covering the transistor gate structures TGS, the doped regions R1, R2, and the trench conductors CT. A mask layer ML2 is then deposited over the spacer layer SL3.
  • FIG. 7B shows a step S12, wherein the mask layer ML2 is patterned and etched, followed by an etching of the spacer layer SL3. The mask layer ML2 is then removed and the spacer layer material SL3 extending above the transistor gate structures is removed. The second implantation of dopants in the doped regions R2 is then performed, followed by silicidation of the wafer.
  • FIG. 8 shows an application example of a device DV according to embodiments of the disclosure. The device DV comprises a memory MEM, which in turn comprises an integrated circuit IC′ (IC1, IC2, IC3) according to an embodiment of the disclosure. The device DV may further comprise a processor and a communication interface circuit. The device may be a portable device such as a mobile telephone, a chipcard, etc.
  • Although the disclosure has been described in relation with a pair of memory cells C11, C12, each comprising a floating gate transistor and a selection transistor, wherein the selection transistors comprise a common buried gate, the disclosure is not limited to such an application. The disclosure is indeed applicable to a memory cell comprising a selection transistor not having its buried gate in common with that of another selection transistor. The disclosure is further applicable to any transistor formed adjacent to a trench conductor, with a thin oxide layer separating a doped region of the transistor and a semiconductor material of the trench, wherein a risk of a silicide short exists between the doped region and the semiconductor material.
  • It will be understood that the length of the spacer SP1, SP11, SP21 formed above the first doped region R1 is equal to or greater than the distance D1, D1′ between the first edge E1 of the transistor gate structure TGS and the upper edge of the trench conductor CT. In particular, the outer edge of the first spacer SP1, SP11, SP21 may extend beyond the junction of the doped region R1 and the trench conductor CT such that it slightly overlaps the isolating layer 2 or the semiconductor material 3. This may be the unavoidable result of the spacer formation process, or deliberate to ensure that the doped region R1 is completely covered despite any variances of the semiconductor fabrication process.
  • Furthermore, though the disclosure has been described in relation with N-type doped regions R1, R2, R3, NISO, and a P-type doped well PW, it is equally applicable to P-type doped regions R1, R2, R3, a P-doped isolation layer, and an N-type doped well. Additionally, though the transistors formed on the surface of the substrate have been described as floating gate or “charge storage” transistors, they may instead simply comprise a control gate and a gate oxide, or comprise for example silicon nanocrystals instead of a floating gate of polysilicon material.
  • It will also be understood that the doped regions R1, R2 may extend slightly beneath the transistor gate structure TGS rather than stopping exactly at the edge of the gate structure. This may be due for example to a tilted implantation process.
  • In one embodiment, rather than removing the spacers SP2 as shown in FIGS. 5A, 5B, spacers SP2 may be left in place over the doped region R2. Consequently, a double-spacer may be formed on both sides of the transistor gate structure.
  • Finally, the materials described above, such as silicon dioxide and polysilicon, may be replaced by any other material commonly implemented in semiconductor fabrication.
  • The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Claims (26)

1. An integrated circuit, comprising:
a trench conductor that includes:
a trench formed in a semiconductor substrate;
an isolating layer on sidewalls of the trench; and
a semiconductor material filling the trench;
a first transistor formed on a surface of the substrate, the transistor including:
a transistor gate structure;
a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor; and
a first spacer formed on the first edge of the gate structure and above the first doped region, the first spacer completely covering a surface the first doped region, extending beyond the first doped region, and overlapping the insulating layer; and
a silicide layer on a surface of the semiconductor material of the trench conductor but is not present on the surface of the first doped region.
2. The integrated circuit according to claim 1, further comprising:
a second doped region extending in the substrate from a second edge of the gate structure, the second edge being on an opposite side of the gate structure with respect to the first edge; and
a second spacer formed on the second edge of the gate structure and above the second doped region.
3. The integrated circuit according to claim 2, wherein the first spacer has a length greater than a length of the second spacer.
4. The integrated circuit according to claim 3, wherein the first spacer is approximately twice as long as the second spacer.
5. The integrated circuit according to claim 3, wherein the first spacer is a double-spacer structure comprising a first portion that partially covers the first doped region and a second portion that covers the remainder of the first doped region.
6. The integrated circuit according to claim 2, comprising a contact formed on the second doped region, wherein a first distance between the first edge of the transistor gate structure and the upper edge of the trench conductor is approximately half of a second distance between the second edge of the transistor gate structure and the contact.
7. The integrated circuit according to claim 6, wherein the first spacer has a length greater than or equal to the first distance, and the second spacer has approximately the same length as the first spacer.
8. The integrated circuit according to claim 2, comprising a contact formed on the second doped region, wherein a first distance between the first edge of the transistor gate structure and the upper edge of the trench conductor is approximately equal to a second distance between the second edge of the transistor gate structure and the contact.
9. The integrated circuit according to claim 2, wherein the second doped region comprises a shallow, lightly doped portion and a deeper, more highly doped portion, and the first doped region only comprises a shallow, lightly doped portion.
10. The integrated circuit according to claim 2, wherein a silicide is also present on at least one of the control gate and the second doped region.
11. The integrated circuit according to claim 1, comprising a second transistor the includes:
a buried gate formed by the trench conductor;
a source or drain region formed by a third doped region that extends along lower edges of the buried gate; and
a first vertical channel extending on one side of the buried gate, between the first and the third doped regions.
12. The integrated circuit according to claim 11, wherein the first transistor is a first charge storage transistor and the second transistor is a first selection transistor, the transistors forming a first memory cell.
13. The integrated circuit according to claim 12, further comprising a second memory cell comprising a second charge storage transistor formed on the surface of the substrate on the opposite side of the trench conductor and a selection transistor comprising a second vertical channel extending on an opposite side of the trench conductor with respect to the first vertical channel, the trench conductor forming a common buried gate of the first and second memory cells.
14. A device comprising:
an integrated circuit that includes:
a trench conductor that includes:
a trench formed in a semiconductor substrate;
an isolating layer on sidewalls of the trench; and
a semiconductor material filling the trench;
a first transistor formed on a surface of the substrate, the transistor including:
a transistor gate structure;
a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor; and
a first spacer formed on the first edge of the gate structure and above the first doped region, the first spacer completely covering a surface the first doped region, extending beyond the first doped region, and overlapping the insulating layer; and
a silicide layer on a surface of the semiconductor material of the trench conductor but is not present on the surface of the first doped region.
15. The device according to claim 14, wherein the integrated circuit includes:
a second doped region extending in the substrate from a second edge of the gate structure, the second edge being on an opposite side of the gate structure with respect to the first edge; and
a second spacer formed on the second edge of the gate structure and above the second doped region.
16. The device according to claim 15, wherein the integrated circuit includes a contact formed on the second doped region, wherein a first distance between the first edge of the transistor gate structure and the upper edge of the trench conductor is approximately equal to a second distance between the second edge of the transistor gate structure and the contact.
17. The device according to claim 16, wherein the first spacer is a double-spacer structure comprising a first portion that partially covers the first doped region and a second portion that covers the remainder of the first doped region.
18. The device according to claim 15, wherein the first spacer has a length greater than a length of the second spacer.
19. The device according to claim 14, wherein the integrated circuit includes a second transistor the includes:
a buried gate formed by the trench conductor;
a source or drain region formed by a third doped region that extends along lower edges of the buried gate; and
a first vertical channel extending on one side of the buried gate, between the first and the third doped regions.
20. A method, comprising:
fabricating an integrated circuit, the fabricating including:
forming a trench in a semiconductor substrate;
forming an isolating layer on sidewalls of the trench;
filling the trench with a semiconductor material to form a trench conductor;
forming a first transistor gate structure on a surface of the substrate;
implanting a first doped region extending between a first edge of the gate structure and an upper edge of the trench conductor;
forming a first spacer on the first edge of the gate structure and above the first doped region, wherein the first spacer completely covers the first doped region, extends beyond the first doped region, and overlaps the insulating layer; and
forming a silicide on the top surface of the semiconductor material of the trench conductor while the first spacer prevents the first doped region from being silicided.
21. The method according to claim 20, wherein the fabricating includes:
implanting a second doped region extending from a second edge of the gate structure, the second edge being on an opposite side of the gate structure with respect to the first edge; and
forming a second spacer on the second edge of the gate structure and above the second doped region.
22. The method according to claim 21, wherein the first spacer has a length greater than a length of the second spacer.
23. The method according to claim 21, wherein the trench conductor is a buried gate of a second transistor, the fabricating including forming a third doped region extending along lower edges of the buried gate and forming a source or drain region of the second transistor, such that the second transistor has a vertical channel extending on one side of the buried gate, between the first and the third doped regions.
24. The method according to claim 23, wherein forming the first spacer includes forming the first spacer only partially covering the first doped region, the fabricating including:
removing the second spacer;
forming a third spacer covering a portion of the first doped region not covered by the first spacer; and
forming a fourth spacer above the second doped region.
25. The method according to claim 21, wherein forming the first and second spacers includes:
depositing a uniform spacer layer; and
patterning and etching the uniform spacer layer to form the first and second spacers.
26. The method according to 21, wherein the fabricating includes implanting dopants into the second doped region, without implanting dopants into the first doped region.
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