CN110957266A - 集成电路制造方法 - Google Patents

集成电路制造方法 Download PDF

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Publication number
CN110957266A
CN110957266A CN201910894266.8A CN201910894266A CN110957266A CN 110957266 A CN110957266 A CN 110957266A CN 201910894266 A CN201910894266 A CN 201910894266A CN 110957266 A CN110957266 A CN 110957266A
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China
Prior art keywords
air gap
layer
integrated circuit
dummy
contact
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CN201910894266.8A
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English (en)
Inventor
李凯璿
赖柏宇
杨世海
杨丰诚
林益安
陈燕铭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种集成电路的制造方法，包括：提供元件结构包括基底，在基底上的源极/漏极部件，在基底上的栅极堆叠，于源极/漏极部件上方的接触孔，以及于源极/漏极部件上方并在栅极堆叠和接触孔之间的虚置部件。制造方法还包括：在接触孔中形成接触插塞，并电性耦合至源极/漏极部件，在形成接触插塞后，选择性移除虚置部件，以形成气隙延伸高于栅极堆叠顶面。制造方法还包括：于接触插塞上方形成密封层，并覆盖气隙。

Description

集成电路制造方法
技术领域
本发明实施例涉及半导体元件的形成方法，特别涉及气隙的形成方法。
背景技术
半导体集成电路工业经历了快速的成长。集成电路材料和设计的技术进步产生了集成电路元件的世代，而每个世代都具有相较于前一代更小和更复杂的电路。在集成电路进化的历程中，功能密度(即每晶粒面积的互连元件数量)总体而言增加，而几何尺寸(即可用制造过程创造出的最小组件(或走线))则减少。通过增加量产效率和降低相关成本，此微缩化的制程总体而言提供了效益。但是，这些进步也增加了集成电路元件制造过程的复杂性。
举例来说，元件几何缩小同时，耦合电容值倾向增加在互连结构(如源极/漏极接触插塞与邻近栅极)之间。增加的耦合电容值降低元件性能。欲降低耦合电容值，使用有相对低介电常数(k)，如低k介电质和气隙的绝缘材料在源极/漏极部件和邻近栅极之间。但是这些材料被证实在制造上很困难。在某些实例中，低k介电材料的沉积很易脆、不稳定、难以沉积，或对于如蚀刻、退火、研磨的制程敏感，而气隙的形成则很难控制。由于这些和其他理由，期望可改善于互连结构之间的介电质制造技术，以减少耦合电容值，并同时维持集成电路中的高整体晶体管密度。
发明内容
本发明实施例提供一种集成电路的制造方法，包括：提供元件结构，包括：基底，在基底上的源极/漏极部件，在基底上的栅极堆叠，于源极/漏极部件上方的接触孔，以及于源极/漏极部件上方，并在栅极堆叠和接触孔之间，的虚置部件；在接触孔中形成接触插塞，并电性耦合至源极/漏极部件；形成接触插塞后，选择性移除虚置部件以形成气隙，气隙延伸高于栅极堆叠顶面；以及形成密封层于接触插塞之上并盖住气隙。
本发明实施例提供一种集成电路的制造方法，包括：提供元件结构，包括：基底；在基底上的第一和第二栅极堆叠，在第一和第二栅极堆叠之间的第一和第二虚置部件，以及在第一和第二虚置部件之间的接触插塞；蚀刻第一和第二虚置部件以分别形成第一和第二气隙；以及形成密封层于接触插塞之上以密封住第一和第二气隙，其中密封层与第一和第二气隙交界于第一和第二栅极堆叠顶面之上的高度。
本发明实施例提供一种集成电路元件，包括：基底；置于基底上的源极/漏极部件；置于源极/漏极部件上方的接触插塞，并电性耦合至源极/漏极部件；置于源极/漏极部件上方，并与接触插塞相邻的栅极堆叠；置于接触插塞和栅极堆叠之间的气隙；以及密封层盖住气隙，其中密封层和气隙之间的接口高于栅极堆叠的顶面。
附图说明
以下将配合说明书附图详述本公开的各面向。应注意的是，依据在业界的标准做法，各种特征并未按照比例绘制。事实上，可任意地放大或缩小元件的尺寸，以清楚地表现出本公开的特征。
图1是根据本发明的不同实施例所示出形成集成电路元件方法的流程图。
图2A、图2B、图2C、图2D、图2E、图2F、图2G、图2H、图2I、和图2J是根据本发明的不同实施例，在不同制造阶段中所示出的剖面示意图。
图3A、图3B、和图3C是根据本发明的不同实施例，示出气隙的垂直深度控制能力的示意图。
图4A和图4B是根据本发明的不同实施例，示出气隙的侧向宽度控制能力的示意图。
图5A、图5B、和图5C是根据本发明的不同实施例，所示出气隙的对位偏移适应性的示意图。
附图标记说明：
10～方法
12、14、16、18、20、22、24、26、28～步骤
100～集成电路元件
102～基底
106～源极或漏极部件
110～层间介电层
112～栅极间隔物
116a～(第一)栅极堆叠
116b～(第二)栅极堆叠
117～蚀刻停止层
118～接触蚀刻停止层
120～层间介电层
130～接触孔
132～侧壁表面
134～底面
136～接触插塞
140～虚置层
140a～(第一)虚置部件
140b～(第二)虚置部件
142～氮化物衬层
142a～(第一)氮化物衬层
142b～(第二)氮化物衬层
146～金属层
148～金属硅化物
149～接触层
150a～(第一)气隙
150b～(第二)气隙
152～密封层
154a～(第一)接口
154b～(第二)接口
200～集成电路元件
210a～(第一)气隙
210b～(第二)气隙
300～集成电路元件
310a～(第一)气隙
310b～(第二)气隙
350～集成电路元件
360a～(第一)气隙
360b～(第二)气隙
400～集成电路元件
410a～(第一)气隙
410b～(第二)气隙
450～集成电路元件
460a～(第一)气隙
460b～(第二)气隙
500～集成电路元件
510a～(第一)气隙
510b～(第二)气隙
550～集成电路元件
560a～(第一)气隙
560b～(第二)气隙
580～集成电路元件
590a～(第一)气隙
590b～(第二)气隙
具体实施方式
以下公开提供了许多不同的实施例或范例，用于实施本发明实施例的不同部件。组件和配置的具体范例描述如下，以简化本发明实施例。当然，这些仅仅是范例，并非用以限定本发明实施例。举例来说，叙述中提及第一部件形成于第二部件之上，可包括形成第一和第二部件直接接触的实施例，也可包括额外的部件形成于第一和第二部件之间，使得第一和第二部件不直接接触的实施例。另外，本发明实施例可在各种范例中重复元件符号及/或字母。这样重复是为了简化和清楚的目的，其本身并非主导所讨论各种实施例及/或配置之间的关系。此外，为了简化和清楚的目的，不同部件可被任意绘制在不同规格下。
再者，此处可使用空间上相关的用语，如“在……之下”、“下方的”、“低于”、“在……上方”、“上方的”、和类似用语可用于此，以便描述如图所示一元件或部件和其他元件或部件之间的关系。这些空间用语除了包括附图示出的方位外，也企图包括使用或操作中的装置的不同方位。举例来说，如果图中的装置被反过来，原本被形容为“低于”或在其他元件或部件“下方”的元件，就会被转为“高于”其他元件或部件。所以，例示性用语“下方”可同时具有“上方”和“下方”的方位。当装置被转至其他方位(旋转90°或其他方位)，则在此所使用的空间相对描述可同样依旋转后的方位来解读。
本发明实施例总体而言与集成电路元件和制造方法相关，且特别涉及在源极/漏极接触插塞和邻近金属栅极之间的气隙形成。当鳍式场效晶体管技术进展至更小的技术节点(如16nm、10nm、7nm、5nm、以及更低)，减少鳍节距严重限制了可使用在金属栅极和连接至源极/漏极部件的邻近接触插塞之间的材料。要最小化在金属栅极和接触插塞之间的耦合电容值，气隙可帮助减少耦合电容值，因为空气具有比其他介电材料低的介电常数(k＝1)。但是，当气隙形成在接触插塞之前，气隙容易被后续接触插塞的形成所破坏。举例来说，当形成接触插塞时，如果用来图案化接触插塞的遮罩没有完全对准下层组件，可能发生对位偏移。对位偏移时，接触孔的位置可能非常接近，如果不是碰触到，邻近的金属栅极。在这样的情况下，蚀刻接触孔会将已经被密封的气隙暴露，而在蚀刻接触孔之后形成的氮化物衬层可部分或全部填充被暴露的气隙。因此，气隙会失去其减少耦合电容值的目的。
通过在接触插塞形成之后(不是之前或同时)再形成气隙，本发明实施例可以避免这样的问题。举例来说，通过选择性移除置于接触插塞旁边的虚置部件以形成气隙。通过虚置部件材料相较于其他直接接触虚置部件的材料所具有的蚀刻选择比，可实现虚置部件的选择性移除。于此公开的气隙在插塞后形成导致自我对准气隙，因为它们的位置取决于虚置部件的位置。此外，这样的气隙具有精准地可控轮廓。气隙的高度延伸于金属栅极顶面之上。如此一来，可有效地减少在金属堆叠和接触插塞之间的耦合电容值。元件可靠度得以改善，而最佳交流/直流增益可在没有潜在气隙破坏的情形下来实现。
图1是根据本发明实施例的不同面向所制造集成电路元件(或元件结构)的方法10流程图。方法10仅仅是范例，并非用以对本发明实施例作出超过权利要求以外的限定。额外步骤可以于方法10之前、之中、之后提供，有些所述的步骤可以为了方法10的额外实施例被取代、移除、或移动。在接下来的讨论中，方法10的描述可参考图2A至图2J，其为根据本发明的不同实施例，在不同制造阶段中，集成电路元件100部分或完整的局部剖面示意图。
集成电路元件100可以是或包括鳍式场效晶体管元件(以鳍为主的晶体管)，其可被包括在微处理器、存储器单元、及/或其他集成电路元件中。集成电路元件100可以是集成电路芯片、系统单芯片、或其部分于制程中所制造的中间元件，其包括不同被动和主动微电子元件，如电阻、电容、电感、二极管、P型场效晶体管、N型场效晶体管、金属氧化半导体场效晶体管、互补式金属氧化物半导体晶体管、双极性晶体管、高压晶体管、高频率晶体管、其他合适装置、或其组合。图2A至图2J为了清楚的目的被简化，以优选理解本发明实施例的发明概念。在集成电路元件100中可加入额外部件，并且在集成电路元件100的其他实施例中，某些下述的部件可以被取代、修改、或移除。
在步骤12，方法10提供，或配置有，起始集成电路元件100。如图2A所示，起始集成电路元件100包括基底102、源极或漏极部件106、层间介电层110、栅极间隔物112、栅极堆叠116a和116b、蚀刻停止层117、接触蚀刻停止层118、层间介电层120、以及接触孔130，其形成横跨集成电路元件100的多层膜。集成电路元件100可包括没有在图2A绘出的不同的其他部件。以下描述集成电路元件100的装置。
在本实施例中，基底102是半导体基底(例如硅晶圆)。或者，基底102可包括另一个元素半导体，如锗，化合物半导体包括碳化硅、氮化镓、砷化镓、磷化镓、磷化铟、砷化铟、以及锑化铟，合金半导体包括锗化硅、砷磷化镓、磷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、以及砷磷化镓铟，或其组合。基底102可是绝缘层上半导体基底，如绝缘层上硅晶基底、绝缘层上硅锗晶基底、或绝缘层上锗晶基底。可使用氧气注入隔离(separation by implantationof oxygen)、晶圆接合、及/或其他合适方法制造绝缘层上半导体基底。基底102可依照集成电路元件100的设计需求，包括不同掺杂区(未绘出)。在一些执行过程中，基底102包括掺杂P型掺质，如硼、铟、其他P型掺质或其组合的P型掺杂区(例如P型井)。在一些实施方式中，基底102包括掺杂N型掺质，如磷、砷、其他N型掺质或其组合的N型掺杂区(例如N型井)。在一些实施方式中，基底102包括以P型掺质和N型掺质的组合所形成的掺杂区。可在基底102上，及/或其中直接形成不同的掺杂区，例如，提供P井结构、N井结构、双井结构、提高结构、或其组合。可进行离子植入制程、扩散制程、及/或其他合适的掺杂制程以在基底102中形成不同的掺杂区。
源极/漏极部件106置于基底102中，并可包括N型掺杂硅晶的N型场效晶体管、P型掺杂硅锗晶的P型场效晶体管、或其他合适的材料。通过蚀刻在主动区中邻近栅极间隔物112的凹陷，然后在凹陷中外延成长半导体材料，可形成源极/漏极部件106。可在外延成长的半导体材料原位(in-situ)或异位(ex-situ)掺杂适当的掺质。源极/漏极部件106可有任何合适的形状，并可全部或部分埋置于主动区中。举例来说，依照外延成长的量，源极/漏极部件106可升至高于、等于、或低于鳍顶面。
层间介电层110置于基底102上。层间介电层110可包括四乙氧基硅烷氧化物(tetraethylorthosilicate oxide)、未掺杂硅酸盐玻璃、或掺杂硅氧化物，如硼磷硅酸玻璃、熔硅石玻璃(fused silica glass)、磷硅酸玻璃、硼掺杂硅玻璃、及/或其他合适的介电材料。通过等离子体促进化学气相沉积、流动性化学气相沉积、或其他合适方法，可形成各层间介电层。
栅极堆叠116a和116b可各包括栅极介电层于底端，和置于栅极介电层上的栅极电极层。栅极介电层可包括二氧化硅或高k介电材料，如硅氧化铪、二氧化铪、氧化铝、二氧化锆、氧化镧、氧化钛、氧化钇、钛酸锶(strontium titanate)、或其组合。可使用化学气相沉积、物理气相沉积、原子层沉积、及/或其他合适的方法沉积栅极介电层。栅极堆叠116a和116b的栅极电极层可包括多晶硅及/或一或多个金属层。举例来说，栅极电极层可包括功函数金属层、导电阻障层、和金属填充层。功函数金属层，依照元件种类，可是P型或N型功函数层。P型功函数层可包括氮化钛铝、氮化钛、氮化钽、钌、钼、钨、铂、另一个合适金属、或其组合。N型功函数层可包括钛、铝、碳化钽、碳氮化钽、硅氮化钽、氮化钛铝、硅氮化钛、另一个合适金属、或其组合。金属填充层可包括铝、钨、钴、及/或其他合适材料。可使用如化学气相沉积、物理气相沉积、电镀、及/或其他合适制程的方法沉积栅极电极层。栅极堆叠116a和116b可还包括于栅极介电层底下的接口层。接口层可包括，如二氧化硅或氮氧化硅的介电材料，并可通过化学氧化、热氧化、原子层沉积、化学气相沉积、及/或其他合适的方法形成。
各栅极间隔物112可被视为其邻近栅极堆叠的侧壁，或者是耦合至其邻近栅极堆叠。各栅极间隔物112可是单膜层或是多膜层结构。举例来说，栅极间隔物112可包括，如氧化硅、氮化硅、氮氧化硅、其他介电材料，或其组合的介电材料。可通过沉积(例如化学气相沉积或物理气相沉积)和蚀刻制程形成栅极间隔物112。
可通过任何合适制程，如栅极先制制程或栅极后制制程形成栅极堆叠116a和116b。在一栅极先制制程范例中，在形成源极/漏极部件106之前，沉积和图案化不同材料层来变成栅极堆叠116a和116b。在一栅极后制制程(也被称为栅极取代制程)范例中，首先形成临时栅极结构(有时被称为“虚置”栅极)。然后，在形成晶体管源极/漏极部件106之后，移除临时栅极结构，并以栅极堆叠116a和116b所取代。在图2A所示的实施例中，栅极堆叠116a和116b可被置于晶体管的通道区上方，以作为栅极终端。虽然没有在此剖面示意图所示出，金属插塞可被置于这个栅极堆叠上方，例如，施予可调整电压至栅极堆叠以控制在源极/漏极部件106和另一个没有在图2A所示出的源极/漏极部件之间的通道区。
蚀刻停止层117邻近于，并环绕，栅极间隔物112。蚀刻停止层117可包括氮化硅、氧化硅、氧氮化硅、及/或其他材料。于制程中，在形成层间介电层110和栅极堆叠116a和116b之前，形成蚀刻停止层117于栅极间隔物112上方。可通过一或多种方法，如等离子体促进化学气相沉积、原子层沉积、及/或其他合适方法形成蚀刻停止层117。接触蚀刻停止层118位在，并围绕，层间介电层110和栅极堆叠116a和116b上方。接触蚀刻停止层118可包括氮化硅、氧化硅、氧氮化硅、及/或其他材料。不同于在层间介电层110和栅极堆叠116a和116b之前形成的蚀刻停止层117，接触蚀刻停止层118在层间介电层110和栅极堆叠116a和116b之后形成。可通过一或多种方法，包括等离子体促进化学气相沉积、原子层沉积、及/或其他合适方法形成接触蚀刻停止层118。
在一些实施例中，在接触蚀刻停止层118上方形成层间介电层120。层间介电层120可包括，如四乙氧基硅烷氧化物(tetraethylorthosilicate oxide)、未掺杂硅酸盐玻璃、或掺杂硅氧化物，如硼磷硅酸玻璃、熔硅石玻璃(fused silica glass)、磷硅酸玻璃、硼掺杂硅玻璃、低k介电质材料、及/或其他合适介电质的材料。可通过流动性化学气相沉积、等离子体促进化学气相沉积、或其他合适方法形成层间介电层120。层间介电层120可具有与层间介电层110相同或不同的厚度。
接触孔130处在栅极堆叠116a和116b之间。由顶部至底部，接触孔130贯穿层间介电层120、接触蚀刻停止层118、层间介电层110。如图2A所示，接触孔130暴露了源极/漏极部件106的顶部。接触孔130包括侧壁表面132和底面134，其底面134有效地等同于源极/漏极部件106的顶面。方法10接着在接触孔130中形成接触插塞136。此步骤涉及不同的制程，如以下所述。
在步骤14，方法10(图1)按序沉积多层膜─包括虚置层140和氮化物衬层142─于集成电路元件100(图2B)上方。虚置层140覆盖至少接触孔130的底面134和侧壁表面132，但也可覆盖集成电路元件100(如图2B所示)的最顶面。在一实施例中，均匀地沉积虚置层140横跨集成电路元件100的顶面。虚置层140包括硅、锗、锗化硅、低密度氮化硅、低密度氧化硅、及/或其他合适的材料。由于虚置层140之后会被选择性蚀刻以形成气隙(在步骤26)，可对于此选择性蚀刻制程，调整或最佳化虚置层140的成分。可通过一或多种方法，如等离子体促进化学气相沉积、原子层沉积、及/或其他合适沉积或氧化制程形成虚置层140。在一些实施例中，虚置层140的尺寸，包括如图2B所示其高度(H)和宽度(W1或W2)，被调整以控制在集成电路元件100(于下方描述)中形成的气隙尺寸。如图2B所指出，虚置层140可延伸至栅极堆叠116a和116b顶面上方，也可延伸至栅极堆叠116a和116b底面下方。在一实施例中，虚置层140的高度约20至50nm，其宽度约1至5nm。虚置层140的合适宽度可与接触孔130(如图2A所示)的宽度相关。在一实施例中，虚置层140和接触孔130的宽度之间的比例约1:10至1:5。举例来说，若接触孔130为15nm宽，虚置层140可约1.5nm至3nm宽(在接触孔130各一边上)。此范围的决定是因为虚置层140应该足够宽，以创造出充分的气隙宽度(描述于下)，但也需要足够窄，以容许在接触孔130之中所形成可靠的接触部件具有充分的体积。举例来说，若在接触孔130各一边上的虚置层140占据了接触孔130宽度的40％，则只剩于小于20％的空间以填充接触部件(而氮化物衬层142也另外具有其宽度的空间需求)。
氮化物衬层142可包括不同材料，如碳掺杂氮化硅、高密度氮化硅、及/或其他合适的材料。可通过一或多种方法，如等离子体促进化学气相沉积、原子层沉积、及/或其他合适沉积或氧化制程形成氮化物衬层142。在一些实施例中，氮化物衬层142总体而言具有横跨集成电路元件100顶部的顺应厚度的薄层。通过侧壁表面132的氮化物衬层142的顺应性质有助于避免从接触插塞136(在步骤24形成)至栅极堆叠116a和116b(反之亦然)的漏电流路径。在一些实施例中，可重复执行步骤14以实现氮化物衬层142的预定厚度。
在步骤16，方法10(图1)进行选择性蚀刻以移除部分虚置层140和氮化物衬层142，从而在侧壁表面132(图2C)上个别产生虚置部件140a和140b，以及氮化物衬层142a和142b。应注意的是，虚置部件140a和140b在三维集成电路元件100中可代表同一个虚置部件，但它们为了清楚的目的在此剖面示意图被分开标示。相同的考量亦套用在其他标示，如氮化物衬层142a和142b(和更下方所述的气隙150a和150b)。由于要暴露源极/漏极部件106的顶面，所进行的选择性蚀刻制程是要蚀刻穿于底面134上和于集成电路元件100最顶面上的氮化物衬层142和虚置层140。但是选择性蚀刻制程不会蚀刻穿氮化物衬层142a和142b，其为氮化物衬层142的侧壁线段。此外，在选择性蚀刻制程中，步骤16可“薄化”(移除一部分厚度的)氮化物衬层142a和142b。的确，若氮化物衬层142a和142b太厚，它们可阻碍后续制程所需的侧向空间。因此，此薄化为接触插塞136的沉积开启了更多空间。但是步骤16的控制，是以在氮化物衬层142a和142b被蚀刻穿透之前停止。氮化物衬层142a和142b的剩余厚度保留在最终产品中。在一些实施例中，氮化物衬层142a和142b各约1至5nm厚。如上所述，虚置部件140a和140b的合适厚度或宽度和氮化物衬层142a和142b的合适厚度或宽度是为了容许在接触孔130中形成可靠的接触部件所需要的充足空间或体积来决定。另外，虚置部件140a和140b(位于侧壁表面132上和底面134边缘上)被氮化物衬层142a和142b所遮护，以免于受到选择性蚀刻制程的影响。举例来说，如图2C所示的剖面示意图，虚置部件140a和140b可在接触孔130底部各自采取L状的形式。
在步骤18，方法10(图1)于集成电路元件100(图2D)上方形成金属层146。金属层146至少覆盖接触孔130的底面134，但也可覆盖侧壁表面132和集成电路元件100(如图2D所示)的最顶面。举例来说，可使用原子层沉积制程，在集成电路元件100上方，均匀地沉积金属层146。金属层146可包括不同材料，如镍、钴、钨、钽、或钛、其组合、或其他合适材料。
在步骤20，方法10(图1)，通过选择性蚀刻和转换金属层146(图2E)，在接触孔130的底面134上形成金属硅化物148。在形成金属硅化物148的一实施例中，首先在升高温度退火金属层146，使金属层146与源极/漏极部件106中的半导体材料反应以形成金属硅化物。然后，移除金属层146(在侧壁表面132和集成电路元件100的最顶面上)的未反应部分，从而在底面134上留下金属硅化物148。金属硅化物148可包括镍硅化物、钴硅化物、钛硅化物、或其他合适硅化或锗硅化物。金属硅化物148可覆盖源极/漏极部件106的重掺杂区，而且在某些情况可被视为源极/漏极部件106的一部分。举例来说，在P型源极/漏极部件106中，其重掺杂区可包括锗化硅(SiGe)，因此金属硅化物148可包括锗镍化硅(SiGeNi)、锗钴化硅(SiGeCo)、锗钨化硅(SiGeW)、锗钽化硅(SiGeTa)、或锗钛化硅(SiGeTi)。在N型源极/漏极部件106中，其重掺杂区可包括磷化硅(SiP)，因此金属硅化物148可包括镍化硅磷(SiPNi)、钴化硅磷(SiPCo)、钨化硅磷(SiPW)、钽化硅磷(SiPTa)、或钛化硅磷(SiPTi)。
在步骤22，方法10(图1)于集成电路元件100(图2F)上方形成接触层149。接触层149可包括铝、钨、铜、钴、钛、其组合、或其他合适材料。应注意的是，于此公开的接触或金属层，如金属层146和接触层149，也可包含非金属材料。例如，接触层149可包括由如氮化钽或氮化钛的导电氮化物所制成的阻障层。可通过物理气相沉积、化学气相沉积、原子层沉积、电镀、或其他合适方法形成接触层149。如图2F所示，接触层149贯穿层间介电层120、接触蚀刻停止层118、和层间介电层110。此外，接触层149通过金属硅化物148电性耦合至源极/漏极部件106。在一替代实施例中，接触层149可直接连接至源极/漏极部件106，没有中间硅化物部件。
在步骤24，方法10(图1)从接触层149(图2G)形成接触插塞136。在一实施例中，使用化学机械平坦化制程以移除集成电路元件100的顶厚度，其包括接触层149、层间介电层120、虚置部件140a和140b、和氮化物衬层142a和142b的顶部。接触插塞有时也被称为导孔、导孔插塞、金属接触、或金属插塞。为了简化步骤28，化学机械平坦化制程时间足够长，以确保虚置部件140a和140b的暴露。
在步骤26，方法10(图1)通过蚀刻移除虚置部件140a和140b的剩余部分，以形成气隙150a和150b(图2H)。特别是，在接触插塞136和栅极堆叠116a之间形成气隙150a以减少其间的第一电容值，而在接触插塞136和栅极堆叠116b之间形成气隙150b以减少其间的第二电容值。电容值得以减少是因为空气具有约1的介电常数(k)，其介电常数低于其他介电材料。在一些实施例(例如当没有对位偏移)中，气隙150a和150b具有约相同尺寸，而第一和第二电容值约等同。但是若有对位偏移(如以下图5A至图5C中所述)，气隙150a和150b可具有不同尺寸，而第一和第二电容值可不同。在接触插塞136两边上的不相等电容值可不等地冲击相关电路，但是由于第一和第二电容值在此均减少，其对电路的整体冲击跟着减少。
应该注意的是，于此公开的方法10是在形成接触插塞136之后形成气隙150a和150b。这不同于一般气隙的形成方式，其方式在形成对应接触孔(和接触插塞)之前形成气隙。这样顺序中的改变是有违直觉的，例如，因为气隙于插塞后形成促使独特的蚀刻选择性考量(于下所述)，而一般方式不能达到这样的蚀刻选择性。但是气隙于插塞后形成，如此处所公开，促使了不同的效益。举例来说，一般在接触插塞之前形成的气隙，在接触插塞和邻近的栅极堆叠之间，具有短路的高风险。那是因为，当在两个密封气隙之间蚀刻接触孔时，蚀刻可暴露此密封气隙。如此一来，在于接触孔中形成氮化物衬层的下一个步骤中，氮化物衬层很容易填充已暴露的气隙(打穿)，尤其如果有对位偏移。气隙的体积显着地被减少，更糟的是，氮化物衬层可在接触插塞(在氮化物衬层之后形成)和邻近的栅极堆叠之间导致短路，其可造成元件失效。
本发明实施例通过在接触插塞136形成于其中之后，再形成气隙150a和150b，以避免这样的问题。首先，气隙150a和150b是自我对准，因为它们的侧相位置和轮廓取决于虚置部件140a和140b的侧相位置和轮廓，其置于接触插塞136附近。第二，在气隙150a和150b周围没有蚀刻，因此任何打穿问题得以避免。这样反而改善元件可靠度，并得到更高的崩溃电压。第三，由于可通过调整虚置部件的高度及/或宽度精准控制气隙的体积，栅极堆叠116a或116b和接触插塞136之间的耦合电容值可被有效的控制。最佳交流/直流增益可在没有潜在气隙破坏的情形下来实现。第四，不像一般方式，其气隙低于栅极堆叠顶面，于此公开的气隙150a和150b延伸至栅极堆叠116a或116b的顶面之上。因此，在栅极堆叠116a上部和接触插塞136之间，以及在栅极堆叠116b上部和接触插塞136之间，允许了更多耦合电容值的减少。另外，如图2H的剖面示意图所示，气隙150a和150b(像是形成气隙150a和150b所出自于的虚置部件140a和140b)可各自在接触孔130底部采取L状的形式。气隙150a的L状水平部分可具有一宽度，其大致等同虚置部件140a和氮化物衬层142a的总宽度。气隙150b的L状水平部分可具有一宽度，其大致等同虚置部件140b和氮化物衬层142b的总宽度。由于气隙150a和150b在氮化物衬层142a和142b之下的水平部分相对小，氮化物衬层142a和142b(贴附在接触插塞136)不具有结构支撑的问题。
在一实施例中，虚置部件140a和140b的材料对于氮化物衬层142和层间介电层120具有蚀刻选择性，这样可充分移除虚置部件140a和140b，却基本上不冲击到层间介电层120、或氮化物衬层142a和142b、或栅极堆叠116a或116b。在一实施例中，通过蚀刻虚置部件140a和140b比和虚置部件140a和140b接触的其他材料快至少10倍(或20倍，或50倍)的蚀刻制程，选择性移除虚置部件140a和140b。这样的蚀刻选择性取决于虚置层140、氮化物衬层142、层间介电层120、和栅极堆叠116a或116b的材料选择。因此，这些层的材料成分是以一起的方式做考量。举例来说，虚置层140可使用的材料选自硅、锗、锗化硅、低密度氮化物如氮化硅、和低密度氧化物如氧化硅所组成的族群。于此同时，氮化物衬层142使用材料选自碳掺杂氮化物如氮化硅和高密度氮化物如氮化硅所组成的族群。于此同时，层间介电层120使用流动性化学气相沉积形成的氧化物或掺质掺杂的氧化物(例如氧化硅掺杂硼，于1019至1020的掺杂浓度)。栅极堆叠116a或116b可使用钴及/或其他合适材料。蚀刻选择性是基于对同一种蚀刻剂的不同反应性。举例来说，当虚置层140使用低密度氮化硅，氮化物衬层142使用高密度氮化硅，虚置层140具有较快的蚀刻率，因为低密度氮化硅相较于高密度氮化硅更容易被蚀刻剂氧化。此外，应该理解的是，“低密度”和“高密度”是相关的用语，以便表明掺杂浓度的不同。举例来说，虚置层140掺杂适当的掺质(例如氟)至1至9×1013的掺杂浓度(单位是每平方厘米)，而氮化物衬层142掺杂适当的掺质(例如碳)至不小于1×1015的掺杂浓度。
在步骤26的选择性蚀刻制程可包括干蚀刻、湿蚀刻、反应式离子蚀刻、及/或其他合适制程。举例来说，干蚀刻制程可使用含氧气体、含氟气体(例如四氟化碳、六氟化硫、二氟甲烷、三氟甲烷、及/或六氟乙烷)、含氯气体(例如氯气、三氯甲烷、四氯化碳、及/或三氯化硼)、含溴气体(例如溴化氢及/或三溴甲烷)、含碘气体、其他合适气体及/或等离子体、及/或其组合。在一实施例中，等离子体蚀刻制程是在流动率约每分钟500标准立方厘米至每分钟2000标准立方厘米下进行。举另一个例子，湿蚀刻制程可包括在稀释氢氟酸、氢氧化钾溶液、氨水、含氢氟酸溶液、硝酸、及/或醋酸、或其他合适湿蚀刻剂中蚀刻。湿蚀刻制程可在任何合适的方式下进行，如沉浸集成电路元件100于湿蚀刻剂中一段时间(例如小于1小时)。
在步骤28，方法10(图1)通过形成覆盖气隙150a和150b的密封层152(图2I)，以密封住气隙150a和150b。可使用化学气相沉积、物理气相沉积、原子层沉积、及/或其他合适的方法沉积密封层152。密封层152可使用任何合适的材料，只要其确保气隙150a和150b的完整封闭，以防止其他材料进入气隙150a和150b。密封层152形成之时，气隙150a和150b的体积最终确定。如图2I所示，密封层152与气隙150a和150b(经由个别接口154a和154b)交界于栅极堆叠116a或116b顶面上方的高度。在一些实施例中，接口154a(或154b)和栅极堆叠116a或116b顶面之间的高度差为接触孔130高度的约20％至40％。举例来说，当接触孔130的高度约30nm，高度差约6至12nm。接口154a和154b也可略低于层间介电层120顶面，因为在其形成过程中，密封层152略贯穿进入气隙150a和150b(例如1至4nm)。在一些实施例中，气隙150a和150b具有非常小的宽度(例如不大于10nm、5nm、3nm、或2nm)，因此并没有密封层152贯穿深入气隙150a和150b的风险。
如图2I所示出，密封层152可交界气隙150a和150b于约同一高度。然而，在一些实施例中，于气隙150a和150b顶端的接口可具有不同的高度及/或表面轮廓。如图2J所示出，其代表图2I的变化例，密封层152交界气隙150a于接口154a，交界气隙150b于接口154b，其接口154a高于接口154b。这情况可发生，例如，当气隙150a的宽度小于气隙150b的宽度。此外，接口154a、接口154b、或两者可具有平坦面(如图2I所示)或曲面(如图2J所示)。曲面的形成，是以密封层152贯穿进入气隙150a和150b空间的自然结果。
在方法10中，可形成具合适尺寸(例如厚度、高度、深度、或宽度)的各个物件。举例来说，在一实施例中，栅极间隔物112和栅极堆叠116a或116b各具有于15至25nm之间(例如约20nm)的厚度，层间介电层120具有于50至80nm之间(例如约65nm)的厚度。在步骤24，化学机械平坦化制程可减少层间介电层120的厚度至10至20nm(例如约15nm)。在步骤28，密封层152可为几纳米厚(例如约2至10nm)。
虽然没有于此阐述，在步骤28之后，方法10对集成电路元件100进行额外制程。举例来说，另一个接触插塞可形成于接触插塞136上方(并与其电性连接)。可形成其他蚀刻停止层、层间介电层、和金属线路。配置金属线路以互连上方插塞，以及其他电路部件。
方法10不只可被用来制造集成电路元件100(如图2I所示)，也可以制造其变化例。举例来说，图3A、图3B、图3C、图4A、图4B、图5A、图5B、和图5C示出了不同集成电路元件实施例的剖面示意图。由于这些图所示的集成电路元件与上述集成电路元件100共享各种的共同特征，为了简化起见，这些共同特征不会重复描述。
图3A至图3C，根据本发明的一些实施例，示出了于此公开的气隙的垂直深度控制。特别是，图3A示出了集成电路元件200的剖面示意图，图3B示出了集成电路元件300的剖面示意图，图3C示出了集成电路元件350的剖面示意图。相较于集成电路元件100，其具有垂直延伸至源极/漏极部件106顶面(或平行对准栅极堆叠116a或116b底面)的气隙150a和150b，集成电路元件200、300、350具有相对较浅或较短的气隙。特别是，集成电路元件200具有不垂直延伸至其源极/漏极部件顶面的的气隙210a和210b。集成电路元件300具有不垂直延伸至其源极/漏极部件顶面的的气隙310a和310b。换句话说，气隙310a和310b的最低部分高于栅极堆叠116a或116b底面(例如，有接触孔130高度的5％至10％高度差)。集成电路元件350具有分别比气隙310a和310b还更浅或更短的气隙360a和360b(例如，有接触孔130高度的20％至40％高度差)。应注意的是，气隙310a和310b的最高部分仍然高于栅极堆叠116a或116b顶面。气隙的高度可相等或不同(例如气隙310a和310b的最高部分可具有与气隙150a和150b以及气隙360a和360b的最高部分不同的高度)。如上所述，精准地控制气隙深度的能力有助于在没有潜在气隙破坏的情形下达到最佳交流/直流增益。
要实现如图3A至图3C所示出的气隙的深度控制，在方法10中调节或调整虚置层140的轮廓。可使用不同方式以控制气隙深度。如图3A所示的第一种方式中，在步骤26移除虚置部件140a和140b，使其剩余高度是可控制的。举例来说，当蚀刻虚置部件140a和140b时，可控制蚀刻制程的时间或持久，以掌握蚀刻深度，因此掌握了剩余高度。虚置部件140a和140b的蚀刻率可为常数或可在蚀刻制程中变换，但蚀刻时间是多少虚置部件140a和140b的厚度被蚀刻的可靠指标。在第一种方式中，虚置部件140a和140b的未蚀刻部分分别遗留在气隙210a和210b的底部，如图3A所示。
深度控制的第二种方式利用这样一个事实：由于可通过全部移除虚置部件140a和140b(从虚置层140形成)以形成气隙，虚置层140的初始轮廓可基本上决定气隙的轮廓。因此，第二种方式形成不伸到接触孔130底部的初始虚置层140。举例来说，在步骤12中，起始集成电路元件可已经具有分层的(tiered)侧壁表面132的接触孔130。侧壁表面132可使用任何合适制程(例如多重遮罩和蚀刻步骤)取得分层轮廓，使其上分层比其下分层宽(如图3B和图3C所示)。接着，可在侧壁表面132的上分层上形成虚置部件140a和140b，形成氮化物衬层142a和142b，与虚置部件140a和140b相邻。如图3B和图3C所示，氮化物衬层142a和142b仍伸到在接触孔130底部的源极/漏极部件106。之后，在步骤26中，移除虚置部件140a和140b以形成气隙310a和310b，如图3B所示(或360a和360b，如图3C所示)。在第二种方式中，由于虚置部件140a和140b被全部移除，在气隙下层的可以是蚀刻停止层117，如图3B和图3C所示(而不是虚置部件140a和140b的剩余部分，如在图3A所示的第一种方式中)。
图4A和图4B，根据本发明的一些实施例，示出了于此公开的气隙的侧向宽度控制。特别是，图4A示出了集成电路元件400的剖面示意图，图4B示出了集成电路元件450的剖面示意图。相较于具有相对窄的气隙150a和150b(例如其宽度为约接触孔130宽度的10％至20％)的集成电路元件100，其气隙150a和150b与间隔物112被蚀刻停止层117侧向分隔开，集成电路元件400和450具有相对宽的气隙(例如其宽度为约接触孔130宽度的20％至25％)。特别是，集成电路元件400具有与间隔物112直接接触的气隙410a和410b，没有介于中间的蚀刻停止层117。集成电路元件450具有分别比气隙410a和410b又更宽的气隙460a和460b(例如其宽度为约接触孔130宽度的25％至35％)。在一实施例中，气隙460a和460b可分别伸到栅极堆叠116a和116b的导电部分。具有充足空间或体积以将接触部件填充进入接触孔130的需求，如所述，可限制如气隙460a和460b的气隙最大化。举例来说，当接触孔130的整体宽度为约15nm，接触部件可约5nm宽，而在接触部件各边上的气隙可约5nm宽。精准地控制气隙宽度的能力有助于在没有潜在气隙破坏的情形下达到最佳交流/直流增益。应注意的是，暴露栅极堆叠于气隙，如图4B所示，不带有如短路的不利风险，因为气隙并不包含任何导电，或除此之外有害的材料。
要实现如图4A和图4B所示出的气隙的宽度控制，在方法10中调节或调整虚置层140的轮廓。由于可通过移除虚置部件140a和140b(从虚置层140形成)以形成气隙，虚置层140的轮廓基本上决定了气隙的轮廓。举例来说，在步骤12中，可移除蚀刻停止层117，使接触孔130直接接触间隔物112。在步骤12中，可移除间隔物112上部，使接触孔130伸到栅极堆叠116a和116b的导电部分的上角。在步骤14中，虚置层140和氮化物衬层142以上述所形成。之后，在步骤26中，选择性移除虚置层140以形成气隙410a和410b，如图4A所示(或460a和460b，如图4B所示)。
图5A至图5C，根据本发明的一些实施例，示出了于此公开的气隙的对位偏移适应性。当用来定义上层的遮罩没有与下层物件完美地匹配，而此些物件是在纳米尺寸下(例如当用来形成接触孔130的遮罩没有坐落在栅极堆叠116a和116b的正中间)，会发生对位偏移。特别是，图5A示出了集成电路元件500的剖面示意图，图5B示出了集成电路元件550的剖面示意图，而图5C示出了集成电路元件580的剖面示意图。相较于集成电路元件100，其接触插塞136坐落在约栅极堆叠116a和116b之间的中间点(假设没有对位偏移)，集成电路元件500和550具有从栅极堆叠116a和116b之间的中间点偏移(假设对位偏移至左边)的气隙。在集成电路元件500和550中，接触插塞136比起栅极堆叠116b更接近栅极堆叠116a。集成电路元件500具有相对窄的气隙510a和510b，而集成电路元件550具有相对更宽的气隙560a和560b。在图5A中，气隙510a直接接触间隔物112(但是没有侧向延伸于栅极堆叠116a上方)，而气隙510b与间隔物112至少被蚀刻停止层117(也可能被部分层间介电层110)分隔开。在图5B中，气隙560a直接接触间隔物112，直接接触栅极堆叠116a的一导电部分，并侧向延伸于栅极堆叠116a上方。应注意的是，暴露栅极堆叠116a于气隙560a不带有如短路的不利风险，因为气隙560a并不包含任何导电，或除此之外有害的材料。另一方面，气隙560b直接接触间隔物112，但是没有接触，或侧向延伸于栅极堆叠116b上方。
图5C与图5B类似，如同气隙560a，气隙590a直接接触间隔物112，直接接触栅极堆叠116a的一导电部分，并侧向延伸于栅极堆叠116a上方。另一方面，气隙590b直接接触间隔物112，但是没有接触，或侧向延伸于栅极堆叠116b上方。如图5C中所示，在一些实施例中，当栅极堆叠116a直接暴露至气隙590a，用来形成气隙590a的湿蚀刻可移除栅极堆叠116a的一角落部分和其间隔物112，从而创造出圆化角轮廓。圆化角轮廓的形状取决于不同变因，如栅极堆叠116a和间隔物112的材料，以及气隙590a的形成条件(例如蚀刻剂、持久时间等)。
如上所述，本发明实施例允许气隙的对位偏移适应性，因为于此气隙在形成接触插塞136之后形成。如果在接触插塞136的形成之前，或同时，形成气隙，气隙容易被后续制程填充(打穿)。在本发明实施例中，在栅极堆叠116a或116b和接触插塞136之间有一安全余裕，即便有对位偏移。气隙的打穿没有促使接触蚀刻，这样改善了元件可靠度，并得到更高的崩溃电压。
如上所示出，在本发明实施例中，在气隙形成中的时间点改变造成不同物件的结构和位置的改变。举例来说，气隙现在延伸至栅极堆叠顶面上方。在一些实施例中，气隙的形成，其最低部分位在与环绕栅极堆叠底面等高的地方(图2I)。在其他实施例中，气隙的形成，其最低部分位在高于环绕栅极堆叠底面的位置(图3B和图3C)。在一些实施例中，第二气隙与第二栅极电极层被至少第二栅极间隔物(例如图5B中的气隙560b)分隔开，而第一气隙直接接触第一栅极间隔物和第一栅极电极层上部(例如图5B中的气隙560a)。在图5B中，气隙560a甚至侧向延伸于第一栅极堆叠的第一栅极电极层上方。
本发明的一或多个实施例对于半导体元件和其形成提供了许多效益，但未以此为限。举例来说，于此公开的气隙形成技术实现了含可控性轮廓的自我对准气隙。栅极堆叠和接触插塞之间的藕合电容值能被有效地控制。没有打穿的问题，所以元件可靠度得以改善，并有更高的崩溃电压。因此，在没有潜在气隙破坏的情形下可达到最佳交流/直流增益。公开方法的实施例可以很容易地整合进现有制造过程和技术，如中段和后段制程。
在一范例中，本发明实施例提供了一种集成电路的制造方法，其包括提供元件结构，包括：基底、在基底上的源极/漏极部件、在基底上的栅极堆叠、于源极/漏极部件上方的接触孔、和于源极/漏极部件上方并介于栅极堆叠和接触孔之间的虚置部件。此方法还包括：在接触孔中形成接触插塞，并电性藕合至源极/漏极部件，以及，在形成接触插塞之后，选择性移除虚置部件以形成延伸至高于栅极堆叠顶面的气隙。此方法还包括于接触插塞上方形成覆盖气隙的密封层。
在一实施例中，元件结构还包括第一和第二栅极堆叠，其中在接触插塞和第一栅极堆叠之间形成第一气隙以减少其间的第一电容值，而在接触插塞和第二栅极堆叠之间形成第二气隙以减少其间的第二电容值。在一实施例中，密封层交界第一和第二气隙于第一和第二栅极堆叠顶面上方的高度。在一实施例中，形成第一和第二气隙，其第一和第二气隙的底面位在高于第一和第二栅极堆叠底面的位置。在一实施例中，第一栅极堆叠包括栅极电极层和与栅极电极层接触的间隔物。第一气隙与间隔物至少被一或多介电层分隔开。在一实施例中，第二栅极堆叠包括栅极电极层和与栅极电极层接触的间隔物，而第二气隙直接接触间隔物和栅极电极层上部。在一实施例中，第二气隙侧向延伸于第二栅极堆叠的栅极电极层上方。在一实施例中，形成接触插塞包括沉积金属层覆盖元件结构，和使用化学机械平坦化制程移除金属层上部。化学机械平坦化制程也暴露了第一和第二虚置部件，并在接触插塞的形成之后，促进第一和第二虚置部件的选择性移除。在一实施例中，第一和第二虚置部件具有在蚀刻制程中的蚀刻选择性，通过蚀刻第一和第二虚置部件比与第一和第二虚置部件接触的其他材料快至少10倍的蚀刻制程，选择性移除第一和第二虚置部件。在一实施例中，从第一虚置部件形成的第一气隙直接接触置于接触孔和第一虚置部件之间的第一氮化物衬层。
在另一范例中，本发明实施例提供元件结构，包括：基底、在基底上的第一和第二栅极堆叠、在第一和第二栅极堆叠之间的第一和第二虚置部件、在第一和第二虚置部件之间的接触插塞。一种方法包括蚀刻第一和第二虚置部件以分别形成第一和第二气隙，和形成密封层于接触插塞上方以密封第一和第二气隙。密封层交界第一和第二气隙于第一和第二栅极堆叠顶面上方的高度。在一实施例中，基于第一和第二虚置部件的轮廓以控制第一和第二气隙的轮廓。在一实施例中，形成第一和第二气隙，其第一和第二气隙底面位在高于第一和第二栅极堆叠底面的位置。在一实施例中，形成第一气隙，其第一气隙与第一栅极堆叠的第一栅极电极层至少被第一间隔物分隔开。形成第二气隙，其第二气隙直接接触第二间隔物和第二栅极堆叠的导电部分，而第二气隙侧向延伸于第二栅极堆叠上方。在一实施例中，元件结构还包括于接触插塞和第一虚置部件之间的第一氮化物衬层，和层间介电层直接接触第一虚置部件。蚀刻第一和第二虚置部件比第一氮化物衬层和层间介电层快，其第一氮化物衬层的一或多个材料选自碳掺杂氮化硅和高密度氮化硅所组成的族群，其第一和第二虚置部件的一或多个材料选自硅、锗、锗化硅、低密度氮化硅、和低密度氧化硅所组成的族群，而其层间介电层的一或多个材料是流动性化学气相沉积形成的氧化物或掺质掺杂的氧化物。
在另一范例中，本发明实施例提供集成电路元件，包括：基底、置于基底上的源极/漏极部件、置于源极/漏极部件上方并电性耦合至源极/漏极部件的接触插塞、置于源极/漏极部件上方并与接触插塞相邻的栅极堆叠、置于接触插塞和栅极堆叠之间的气隙、和覆盖气隙的密封层。在密封层和气隙之间的接口高于栅极堆叠顶面。在一实施例中，集成电路元件还包括在接触插塞和气隙之间的氮化物衬层，而氮化物衬层直接接触接触插塞和气隙，没有任何介于中间的介电层。在一实施例中，氮化物衬层的一或多个材料选自碳掺杂氮化硅和高密度氮化硅所组成的族群。在一实施例中，集成电路元件还包括层间介电层直接接触气隙。层间介电层的一或多个材料是流动性化学气相沉积形成的氧化物或掺质掺杂的氧化物。在一实施例中，栅极堆叠包括栅极电极层和触碰到栅极电极层的间隔物。气隙触碰到间隔物和栅极电极层上部，而气隙侧向延伸于栅极电极层上方。
以上概述数个实施例的部件，以便在本发明实施例所属技术领域中技术人员可以更加理解本发明实施例的观点。在本发明实施例所属技术领域中技术人员应理解，他们能轻易地以本发明实施例为基础，设计或修改其他制程和结构，以达到与在此介绍的实施例相同的目的及/或优势。在本发明实施例所属技术领域中技术人员也应理解，此类等效的结构并无悖离本发明实施例的精神与范围，且他们能在不违背本发明实施例的精神和范围下，做各式各样的改变、取代和替换。

Claims (1)

1.一种集成电路的制造方法，包括：
提供一元件结构，包括：
一基底；
一源极/漏极部件，于该基底上；
一栅极堆叠，于该基底上；
一接触孔，于该源极/漏极部件上方；以及
一虚置部件，于该源极/漏极部件上方并介于该栅极堆叠和该接触孔之间；
形成一接触插塞于该接触孔中并电性耦合至该源极/漏极部件；
形成该接触插塞后，选择性移除该虚置部件以形成一气隙，该气隙延伸高于该栅极堆叠顶面；以及
形成一密封层于该接触插塞之上并盖住该气隙。
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