CN110945605B - Method for manufacturing laminated electronic component - Google Patents
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- CN110945605B CN110945605B CN201880048740.9A CN201880048740A CN110945605B CN 110945605 B CN110945605 B CN 110945605B CN 201880048740 A CN201880048740 A CN 201880048740A CN 110945605 B CN110945605 B CN 110945605B
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- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
- H01C7/18—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material comprising a plurality of layers stacked between terminals
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- H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
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Abstract
Description
技术领域technical field
本发明涉及各种电子设备中使用的层叠电子部件的制造方法。The present invention relates to a method of manufacturing laminated electronic components used in various electronic devices.
背景技术Background technique
近年来,表面安装用的电子部件中除了层叠陶瓷电容器、层叠陶瓷压敏电阻,还有各种电子部件。在这些电子部件的尺寸较小的情况下不会特别产生问题,但是若由于应对大容量或者大电流等导致电子部件的尺寸变大,则可能由于电路基板材料与陶瓷的线膨胀率之差导致产生机械应力,电子部件达到损坏。因此,在现有的电子部件中,在电子部件的两端面的外部电极安装将金属板加工而成的导线端子,经由该导线端子来安装于电路基板。In recent years, electronic components for surface mounting include various types of electronic components in addition to multilayer ceramic capacitors and multilayer ceramic varistors. There is no particular problem when the size of these electronic parts is small, but if the size of the electronic parts becomes large due to handling large capacity or high current, etc., it may be caused by the difference in linear expansion coefficient between the circuit board material and ceramics. Mechanical stress is generated and electronic components are damaged. Therefore, in a conventional electronic component, a lead terminal processed from a metal plate is attached to external electrodes on both end surfaces of the electronic component, and the lead terminal is mounted on a circuit board via the lead terminal.
例如,专利文献1中公开了与上述电子部件类似的现有的电子部件。For example, Patent Document 1 discloses a conventional electronic component similar to the above-mentioned electronic component.
在先技术文献prior art literature
专利文献patent documents
专利文献1:JP特开2000-306764号公报Patent Document 1: JP-A-2000-306764
发明内容Contents of the invention
获得将陶瓷层与内部电极交替层叠的烧结体。在烧结体的侧面形成与内部电极连接的第1外部电极。对形成有第1外部电极的烧结体整体进行玻璃涂层。在进行了玻璃涂层的烧结体的侧面形成第2外部电极。通过该方法,在层叠电子部件,能够使内部电极与外部电极的电连接稳定。A sintered body in which ceramic layers and internal electrodes were alternately laminated was obtained. A first external electrode connected to the internal electrode is formed on the side surface of the sintered body. Glass coating is performed on the entire sintered body on which the first external electrodes are formed. A second external electrode was formed on the side surface of the glass-coated sintered body. According to this method, the electrical connection between the internal electrodes and the external electrodes can be stabilized when the electronic component is laminated.
附图说明Description of drawings
图1A是实施方式中的层叠电子部件的立体图。FIG. 1A is a perspective view of a laminated electronic component in the embodiment.
图1B是图1A所示的层叠电子部件的线1B-1B处的剖视图。FIG. 1B is a cross-sectional view at
图2是表示实施方式中的层叠电子部件的制造方法的剖视图。2 is a cross-sectional view illustrating a method of manufacturing a laminated electronic component in the embodiment.
图3是表示实施方式中的层叠电子部件的制造方法的剖视图。3 is a cross-sectional view illustrating a method of manufacturing a laminated electronic component in the embodiment.
图4是表示实施方式中的层叠电子部件的制造方法的剖视图。4 is a cross-sectional view illustrating a method of manufacturing a laminated electronic component in the embodiment.
图5是表示实施方式中的层叠电子部件的制造方法的剖视图。5 is a cross-sectional view illustrating a method of manufacturing a laminated electronic component in the embodiment.
图6是表示实施方式中的层叠电子部件的制造方法的剖视图。6 is a cross-sectional view showing a method of manufacturing a laminated electronic component in the embodiment.
图7是表示实施方式中的层叠电子部件的制造方法的剖视图。7 is a cross-sectional view showing a method of manufacturing a laminated electronic component in the embodiment.
图8是表示实施方式中的层叠电子部件的制造方法的剖视图。8 is a cross-sectional view illustrating a method of manufacturing a laminated electronic component in the embodiment.
具体实施方式detailed description
图1A是实施方式中的层叠电子部件1000的立体图。图1B是图1A所示的层叠电子部件1000的线1B-1B处的剖视图。在实施方式中,层叠电子部件1000是层叠陶瓷压敏电阻。FIG. 1A is a perspective view of a laminated
层叠电子部件1000具备:烧结体11、被设置在烧结体11上的绝缘层15、被设置在烧结体11上的外部电极13A、13B、被设置在外部电极13A上的外部电极14A、被设置在外部电极13B上的外部电极14B、被设置在外部电极14A上的镀敷层16A、被设置在外部电极14B上的镀敷层16B、被设置在镀敷层16A上的接合材料18A、被设置在镀敷层16B上的接合材料18B、通过接合材料18A而与镀敷层16A即外部电极14A接合的导线端子17A、通过接合材料18B而与镀敷层16B即外部电极14B接合的导线端子17B。烧结体11具备相互被交替层叠的多个绝缘层22和内部电极12A、12B。烧结体11具有:内部电极12A露出的侧面11A;内部电极12B露出的侧面11B;与侧面11A、11B连结的安装面11C;与侧面11A、11B连结并且是安装面11C的相反侧的对面11D;连结于侧面11A、11B、安装面11C和对面11D的表面11E;连结于侧面11A、11B、安装面11C和对面11D并且是表面11E的相反侧的表面11F。绝缘层15被设置在烧结体11的安装面11C、对面11D和表面11E、11F上。层叠电子部件1000构成为通过在电路基板等的安装物2001连接导线端子17A、17B而被安装于安装物2001。The laminated
以下说明层叠电子部件1000的制造方法。图2至图8是用于对层叠电子部件1000的制造方法进行说明的剖视图。A method for manufacturing the laminated
将向氧化锌添加氧化铋等并将增塑剂、粘合剂等混合而得到的混合材料成形为片状,从而形成多个生片122。向银粉混合粘合剂等从而形成内部电极用糊膏112。在多个生片122印刷内部电极用糊膏112并层叠为生片122与内部电极用糊膏112交替排列后,通过单片化来形成图2所示的多个层叠体111。通过以约900℃烧制多个层叠体111从而得到多个烧结体11。此时,生片122与内部电极用糊膏112同时被烧制并分别成为绝缘层22和内部电极12A、12B。通过使多个烧结体11与研磨剂混合并搅拌来进行倒角,从而进行烧结体11的角部的倒角,并且使内部电极12A、12B分别在烧结体11的相互相反侧的侧面11A、11B露出。由此,可得到图2所示的烧结体11。内部电极12A在侧面11B不露出,内部电极12B在侧面11A不露出。烧结体11的大小为宽度约7mm、长度约9mm、高度约3mm。A mixed material obtained by adding bismuth oxide or the like to zinc oxide and mixing a plasticizer, a binder, and the like is formed into a sheet to form a plurality of
准备在银粉混合粘合剂等而得到的导体糊膏。接下来,使多个烧结体11排列以使得内部电极12A露出的侧面11A对齐并且内部电极12B露出的侧面11B对齐,在烧结体11的侧面11A、11B印刷导体糊膏以使得分别覆盖露出的内部电极12A、12B,通过以约800℃进行烧制来形成外部电极13A、13B从而得到中间部件1001。此时,由于在从侧面11A、11B露出的内部电极12A、12B将外部电极13A、13B形成为直接接触,因此能够使内部电极12A、12B与外部电极13A、13B的电连接稳定。外部电极13A、13B的厚度约为20μm。被内部电极12A、12B彼此夹着的绝缘层22的区域决定层叠电子部件1000的电特性。由于外部电极13A、13B使用使银粉与粘合剂等混合的导体糊膏,能够防止作为导体的银粉以外的电介质等影响层叠电子部件1000的电特性的额外的物质向该区域扩散,能够使电特性稳定化。A conductor paste obtained by mixing a binder or the like with silver powder is prepared. Next, a plurality of
如图4所示,准备例如由亚微米尺寸的二氧化硅粉末502和二氧化硅粉末502分散的介质液503构成的二氧化硅粉末502的悬浊液即玻璃涂层用的涂层液501。接下来,如图4所示,将形成有外部电极13A、13B的烧结体11即中间部件1001浸渍于涂层液501,对中间部件1001整体进行玻璃涂层。此时,在外部电极13A、13B的表面和烧结体11的表面11C~11F(参照图1A和图1B)附着有二氧化硅粉末502。之后,通过以约900℃对整体被玻璃涂层的中间部件1001进行热处理,从而形成图5所示的中间部件1002。在烧结体11的氧化锌的坯体即表面11C~11F附着的二氧化硅粉末502与绝缘层22的氧化锌的锌进行反应,在烧结体11的表面11C~11F的整体形成稳定的绝缘层15。通过将这样的稳定的绝缘层15形成于外部电极13A、13B以外的从外部电极13A、13B露出的表面11C~11F的整体,能够得到可靠性优良的层叠电子部件1000。在图5所示的中间部件1002中,在外部电极13A、13B的表面附着二氧化硅并分别形成二氧化硅层51A、51B。As shown in FIG. 4 , for example, a suspension of
准备在银粉和玻璃料中混合粘合剂等而得到的混合糊膏。接下来,使多个烧结体11即中间部件1002排列以使得形成有外部电极13A的侧面对齐并且形成有外部电极13B的侧面对齐,在外部电极13A、13B涂敷混合糊膏以使得按照外部电极13A、13B不露出的方式完全覆盖外部电极13A、13B,通过以约700℃进行烧制从而形成图6所示的外部电极14A、14B。外部电极14A、14B具有比外部电极13A、13B大的面积,分别包围外部电极13A、13B的周围。此时,在外部电极13A、13B的表面附着的二氧化硅层51A、51B的二氧化硅的一部分向混合糊膏即外部电极14A、14B中的玻璃料扩散。由此,外部电极13A、13B与外部电极14A、14B可靠地电连接。作为涂敷混合糊膏的方法,优选使用印刷工艺,但也可以使用浸入工艺。但是,即使在该情况下也优选仅涂敷于中间部件1002的几乎侧面。由于为了形成外部电极14A、14B而使用加入有玻璃料的银糊膏,因此外部电极14A、14B能够以充分的强度固定于外部电极13A、13B以及烧结体11。A mixed paste obtained by mixing a binder and the like with silver powder and glass frit is prepared. Next, a plurality of
接下来,通过电镀,在外部电极14A、14B上分别形成镀敷层16A、16B从而形成图7所示的单独部件1003。镀敷层16A(16B)具有:包含形成在外部电极14A(14B)上的镀镍层和形成在镀镍层上的镀锡层的双层构造。在实施方式中,镀镍层的厚度约为3μm,镀锡层的厚度约为5μm。Next, by electroplating, plating
将铁或者磷青铜的板穿孔为规定的形状后,折弯为L字状从而准备导线端子17A、17B。在导线端子17A、17B形成镍以及锡的镀敷层,在与外部电极14A、14B抵接的区域,通过焊料等的接合材料来分别设置接合层18A、18B。接下来,如图8所示,在镀敷层16A、16B即外部电极14A、14B分别连接导线端子17A、17B。使导线端子17A、17B抵接于外部电极14A、14B和接合层18A、18B,通过激光等进行加热来将接合层18A、18B的焊料熔融,在外部电极14A、14B连接导线端子17A、17B,从而能够得到附带导线端子的层叠电子部件1000。通过印刷来形成外部电极13A、13B和外部电极14A、14B,从而能够使与导线端子17A、17B相接的外部电极14A、14B(镀敷层16A、16B)的表面平坦,能够将接合层18A、18B沿着导线端子17A、17B从烧结体11的侧面11A、11B超过安装面11C并向安装物2001扩展。通过这样构成,能够分散从导线端子17A、17B侧的应力,能够进一步提高层叠电子部件1000的可靠性。
图7和图8所示的单独部件1003具有:在层叠电子部件1000被安装于电路基板等的安装物2001(参照图1B)时与安装物2001对置的安装面53C、和与安装面53C相反的一侧的对面53D。在将导线端子17A、17B与外部电极14A、14B连接的情况下,配置为将单独部件1003的对面53D设为下方并与基准面54抵接,使导线端子17A、17B的端部117A、117B与基准面54抵接并与对面53D对位的状态下将导线端子17A、17B与外部电极14A、14B连接。通过上述方法而形成的外部电极14A、14B能够几乎不附于单独部件1003的对面53D。因此通过上述的对位,能够使导线端子17A、17B的安装位置稳定,能够容易将层叠电子部件1000高精度地安装于安装物2001,能够提高安装性。
在上述的现有的电子部件中,若在安装导线端子时产生位置偏移,则在安装于电路基板时产生以下的问题。现有的附带导线端子的面安装的电子部件在通常的面安装用的部件安装导线端子,在这些电子部件中为了安装于电路基板,通过浸入(dip)等的方法来在电子部件的安装面形成电极。因此,在安装面以外,在上表面、侧面等的电子部件的其他面也形成电极。若以该电子部件的外形为基准来安装导线端子,则根据电极的厚度差别,可能产生位置偏移。In the above-mentioned conventional electronic component, if a positional displacement occurs when the lead terminal is mounted, the following problems arise when it is mounted on a circuit board. The existing surface-mounted electronic components with lead terminals are mounted with lead terminals on the components used for surface mounting. In these electronic components, in order to be mounted on the circuit board, the mounting surface of the electronic components is dipped by dipping or the like. Form the electrodes. Therefore, electrodes are also formed on other surfaces of the electronic component, such as the upper surface and the side surface, in addition to the mounting surface. If the lead terminal is mounted based on the outer shape of the electronic component, a positional shift may occur due to a difference in thickness of the electrodes.
实施方式中的层叠电子部件1000如上述那样,能够高精度地容易地安装于安装物2001,能够提高安装性。As described above, the multilayer
在对导线端子17A、17B进行定位时,单独部件1003之中在安装面53C的相反侧使距安装面53C最远的部分与基准面54抵接。在图8所示的单独部件1003中,镀敷层16A、16B与基准面54抵接。在实施方式中,为了可靠地抑制烧结体11的差别所导致的导线端子17A、17B的位置的差别,优选相比于外部电极14A、14B,绝缘层15在安装面53C的相反侧远离于安装面53C。When positioning the
-符号说明--Symbol Description-
11 烧结体11 Sintered body
12A、12B 内部电极12A, 12B Internal electrodes
13A、13B 外部电极(第1外部电极)13A, 13B External electrodes (1st external electrodes)
14A、14B 外部电极(第2外部电极)14A, 14B External electrode (2nd external electrode)
15 绝缘层15 insulation
16A、16B 镀敷层16A, 16B plating layer
17A、17B 导线端子17A, 17B wire terminals
18A、18B 接合层18A, 18B bonding layer
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PCT/JP2018/034534 WO2019073762A1 (en) | 2017-10-11 | 2018-09-19 | Layered electronic component production method |
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CN110945605B true CN110945605B (en) | 2023-01-03 |
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US (2) | US11387023B2 (en) |
JP (2) | JP7361250B2 (en) |
CN (1) | CN110945605B (en) |
WO (1) | WO2019073762A1 (en) |
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KR20230103096A (en) | 2021-12-31 | 2023-07-07 | 삼성전기주식회사 | Mutilayer electronic component |
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JPH08330107A (en) * | 1995-03-24 | 1996-12-13 | Tdk Corp | Stacked-type varistor |
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JPS58111915U (en) * | 1982-01-25 | 1983-07-30 | 日本電気株式会社 | Multilayer ceramic capacitor |
JPS6284921U (en) * | 1985-11-15 | 1987-05-30 | ||
JPH06295803A (en) * | 1993-04-07 | 1994-10-21 | Mitsubishi Materials Corp | Chip type thermister and production thereof |
US6160472A (en) * | 1995-03-24 | 2000-12-12 | Tdk Corporation | Multilayer varistor |
JP2000164406A (en) * | 1998-11-25 | 2000-06-16 | Murata Mfg Co Ltd | Chip type electronic part and manufacture thereof |
JP2000223359A (en) | 1999-01-29 | 2000-08-11 | Murata Mfg Co Ltd | Ceramic electronic component |
JP2000235932A (en) * | 1999-02-16 | 2000-08-29 | Murata Mfg Co Ltd | Ceramic electronic component |
JP2000306764A (en) | 1999-04-23 | 2000-11-02 | Murata Mfg Co Ltd | Ceramic electronic component and production thereof |
JP3476800B2 (en) | 2001-08-22 | 2003-12-10 | Tdk株式会社 | Radial lead type multilayer ceramic electronic components |
US20080239621A1 (en) * | 2007-03-29 | 2008-10-02 | Azizuddin Tajuddin | Clip-on leadframe |
JP4978307B2 (en) | 2007-05-24 | 2012-07-18 | 株式会社村田製作所 | Electronic component with lead wire, and method for manufacturing electronic component with lead wire |
JP5353251B2 (en) | 2009-01-07 | 2013-11-27 | Tdk株式会社 | Multilayer capacitor and multilayer capacitor mounting structure |
JP5664574B2 (en) | 2011-03-18 | 2015-02-04 | 株式会社村田製作所 | Multilayer ceramic capacitor |
JP5375877B2 (en) * | 2011-05-25 | 2013-12-25 | Tdk株式会社 | Multilayer capacitor and multilayer capacitor manufacturing method |
CN203085375U (en) * | 2012-12-24 | 2013-07-24 | 日科能高电子(苏州)有限公司 | Pin cutter of aluminum electrolytic capacitor |
JP2015012052A (en) | 2013-06-27 | 2015-01-19 | 株式会社村田製作所 | Ceramic thermistor |
JP6620413B2 (en) | 2015-03-30 | 2019-12-18 | 日本ケミコン株式会社 | Capacitor and manufacturing method thereof |
CN205752078U (en) * | 2016-05-10 | 2016-11-30 | 南京萨特科技发展有限公司 | Pin configuration heavy-current micro fuse |
CN106024231B (en) * | 2016-05-27 | 2018-07-10 | 辰硕电子(九江)有限公司 | A kind of preparation method of zinc oxide varistor tile |
JP7034613B2 (en) | 2017-06-29 | 2022-03-14 | 太陽誘電株式会社 | Ceramic electronic components and their manufacturing methods, as well as electronic component mounting boards |
-
2018
- 2018-09-19 JP JP2019547963A patent/JP7361250B2/en active Active
- 2018-09-19 US US16/622,572 patent/US11387023B2/en active Active
- 2018-09-19 CN CN201880048740.9A patent/CN110945605B/en active Active
- 2018-09-19 WO PCT/JP2018/034534 patent/WO2019073762A1/en active Application Filing
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2022
- 2022-06-13 US US17/838,961 patent/US20220310291A1/en not_active Abandoned
- 2022-08-25 JP JP2022133821A patent/JP7394292B2/en active Active
Patent Citations (1)
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JPH08330107A (en) * | 1995-03-24 | 1996-12-13 | Tdk Corp | Stacked-type varistor |
Also Published As
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JP7361250B2 (en) | 2023-10-16 |
WO2019073762A1 (en) | 2019-04-18 |
CN110945605A (en) | 2020-03-31 |
US20220310291A1 (en) | 2022-09-29 |
US11387023B2 (en) | 2022-07-12 |
US20200194151A1 (en) | 2020-06-18 |
JP2022166301A (en) | 2022-11-01 |
JPWO2019073762A1 (en) | 2020-09-17 |
JP7394292B2 (en) | 2023-12-08 |
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