CN110942989A - Platinum doping method for silicon-based fast recovery diode chip - Google Patents
Platinum doping method for silicon-based fast recovery diode chip Download PDFInfo
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- CN110942989A CN110942989A CN201911283460.9A CN201911283460A CN110942989A CN 110942989 A CN110942989 A CN 110942989A CN 201911283460 A CN201911283460 A CN 201911283460A CN 110942989 A CN110942989 A CN 110942989A
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- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 title claims abstract description 115
- 229910052697 platinum Inorganic materials 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000011084 recovery Methods 0.000 title claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 12
- 239000010703 silicon Substances 0.000 title claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 20
- 238000000137 annealing Methods 0.000 claims abstract description 14
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052796 boron Inorganic materials 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 4
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 230000001965 increasing effect Effects 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66121—Multilayer diodes, e.g. PNPN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a platinum doping method for a silicon-based fast recovery diode chip, which comprises the following steps: s1: the roughness of the back of the chip is improved to form a back rough layer, and a P + layer is generated below the back rough layer, so that the boron concentration of the back of the chip is greater than that of the front of the chip; s2: depositing a platinum metal layer with the thickness of 50-1000 mu m below the back rough layer; s3: placing the chip into a diffusion furnace tube or a rapid annealing furnace tube, wherein the annealing temperature is set to be 1000-1100 ℃, and the annealing time is 5 seconds-30 minutes; s4: and removing the back rough layer and the P + layer on the back of the chip. According to the platinum doping method, the probability of inversion on the front side of the chip caused by high-temperature platinum diffusion is reduced by increasing the concentration of platinum on the back side of the chip and reducing the concentration of platinum on the front side of the chip, so that the reverse leakage current of a diode is effectively controlled, and the platinum diffusion temperature can be further increased to realize that Trr is less than 15 ns.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a platinum doping method for a silicon-based fast recovery diode chip.
Background
With the continuous development of power electronic technology, the working frequency and performance of various main switching circuits are continuously improved, and especially main loops of various frequency conversion circuits and chopper circuits adopt thyristors which are turned off by current conversion or novel power electronic devices (such as GTO, IGBT and the like) with self-turn-off capability, and a fast recovery diode with extremely short reverse recovery time (Trr) is required. At present, chip manufacturers at home and abroad very favor to introduce a composite center by doping platinum to control the minority carrier lifetime so as to achieve the purpose of reducing the Trr of the fast recovery diode.
The common method is to deposit platinum on the front surface of the chip and adopt a high-temperature furnace tube or a rapid annealing furnace tube to perform platinum diffusion to control minority carrier lifetime, and the process method has the advantages of simple process and low manufacturing cost when processing the diode chip with the conventional recovery speed, and can produce the fast recovery diode chip with good parameter performance. When the Trr of the fast recovery diode chip is further reduced, the platinum diffusion temperature needs to be greatly increased, the diode reverse leakage current is greatly increased due to the higher diffusion temperature (over 980 ℃), and the reverse leakage current exponentially increases with the increase of the platinum diffusion temperature, and even the problem of electrical failure of the diode occurs. For example, in an 8A/600V silicon-based fast recovery diode chip, the lowest Trr 18ns can be realized by diffusing platinum from the front surface of the chip, the diode has good reverse breakdown characteristic, and if the platinum diffusion temperature (1000-1100 ℃) is further improved, the Trr can be below 15ns, but the reverse leakage current of the diode is increased sharply, and even the reverse blocking characteristic is lost. For the reasons, the Trr of the silicon-based 8A/600V chip at home and abroad cannot be less than 15ns, so that a circuit designer can only select the SiC Schottky with high price to replace the SiC Schottky, and the circuit cost is increased. On the background that the performance and the frequency of the switching circuit are continuously upgraded, the conventional platinum diffusion method cannot produce a fast recovery diode chip meeting the market requirement.
Disclosure of Invention
The invention discloses a platinum doping method of a silicon-based fast recovery diode chip, which can manufacture a fast recovery diode chip with Trr (reverse recovery time) less than 15ns and can effectively avoid the problem of increase of diode reverse leakage current caused by high-temperature platinum diffusion.
The invention relates to a platinum doping method for a silicon-based fast recovery diode chip, which comprises the following steps:
s1: before platinum doping: removing a dielectric layer on the back of the chip, simultaneously improving the roughness of the back of the chip to form a back rough layer, and generating a P + layer below the back rough layer to simultaneously enable the boron concentration of the back of the chip to be greater than the boron concentration of the front of the chip;
s2: platinum deposition: depositing a platinum metal layer with the thickness of 50-1000 mu m below the back rough layer;
s3: doping platinum: placing the chip subjected to platinum deposition into a diffusion furnace tube or a rapid annealing furnace tube, wherein the annealing temperature is set to be 1000-1100 ℃, and the annealing time is 5 seconds-30 minutes;
s4: after platinum doping: and removing the back rough layer and the P + layer on the back of the chip.
The method has the beneficial effects that: the back rough layer is beneficial to increasing the defect density, inducing more platinum to gather on the back of the chip and reducing the concentration of the platinum on the front of the chip; a P + layer is arranged below the back rough layer, so that the boron concentration of the back of the chip is greater than that of the front of the chip, and platinum is adsorbed; the platinum source is arranged on the back of the chip, the roughness of the back of the chip is improved, the P + layer is arranged to improve the platinum concentration of the back of the chip and reduce the platinum concentration of the front of the chip, so that the probability of inversion on the front of the chip and the possibility of increase of reverse leakage current of the diode are reduced, and finally the purpose of greatly improving the diffusion temperature of the platinum and not increasing the reverse leakage current of the diode is achieved.
Further, in step S1, the dielectric layer on the back side of the chip is removed by grinding or etching. The roughness of the back surface of the chip can be improved by the two modes.
Further, in step S1, the P + layer is disposed by implantation or boron source diffusion, and the concentration of the P + layer is 1 × 1018-1×1020cm-3The depth is 1-10 μm. After the P + layer is arranged on the back of the chip, platinum is adsorbed on the back of the chip through a large number of boron impurity defects to be gathered, and the front of the chip is reducedThe platinum concentration.
Further, in step S2, the platinum metal layer is disposed by sputtering or evaporation. Both of the above two ways can dispose the platinum source on the back of the chip.
Further, in the step S4, the back surface rough layer and the P + layer on the back surface of the chip are removed by back surface thinning or back surface etching. The two modes can obtain the original PN structure of the diode chip again.
Compared with the prior art, the invention has the beneficial effects that: the probability of inversion on the front surface of the chip caused by high-temperature platinum diffusion is reduced by improving the concentration of platinum on the back surface of the chip and reducing the concentration of platinum on the front surface of the chip, so that the reverse leakage current of the diode is effectively controlled, and the temperature of platinum diffusion (reaching 1000-1100 ℃) can be further improved on the basis of ensuring the stability and reliability of the reverse breakdown characteristic of the diode so as to realize that Trr is less than 15 ns.
Drawings
FIG. 1 is a first process diagram of the method of the present invention;
FIG. 2 is a second schematic process diagram of the method of the present invention;
FIG. 3 is a third schematic process diagram of the method of the present invention;
FIG. 4 is a fourth schematic process diagram of the method of the present invention;
FIG. 5 is a graph comparing the concentration distribution of platinum on the front and back surfaces of a chip using the method of the present invention with that of a chip using a conventional method;
the structure comprises a 1.N + type silicon single crystal substrate, a 2. back surface rough layer and a 3.P + layer.
Detailed Description
The present invention is further illustrated by the following detailed description, which is to be construed as merely illustrative and not limitative of the remainder of the disclosure, and modifications and variations such as those ordinarily skilled in the art are intended to be included within the scope of the present invention as defined in the appended claims.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In describing the invention, it is not necessary for a schematic representation of the above terminology to be directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples of the invention and features of different embodiments or examples described herein may be combined and combined by those skilled in the art without contradiction.
A platinum doping method for a silicon-based fast recovery diode chip is suitable for a fast recovery diode chip adopting a P-type epitaxial structure or an N-type epitaxial structure, and comprises the following steps:
1) removing dielectric layers such as silicon oxide and silicon nitride on the back surface of the chip on the back surface of the N + type silicon single crystal substrate 1 in a grinding or etching mode, and meanwhile, improving the roughness of the back surface of the chip to form a back surface rough layer 2, as shown in figure 1;
2) forming a P + layer 3 by boron implantation or boron source diffusion under the backside rough layer 2, the P + layer 3 having a concentration of 1 × 10 as shown in FIG. 218-1×1020cm-3The depth is 1-10 μm, and the boron concentration of the back surface of the chip is greater than that of the front surface of the chip;
3) depositing a platinum metal layer with the thickness of 50-1000 mu m below the back rough layer 2 by adopting a sputtering or evaporation mode;
4) placing the chip subjected to platinum deposition into a diffusion furnace tube or a rapid annealing furnace tube, wherein the annealing temperature is set to be 1000-1100 ℃, and the annealing time is 5 seconds-30 minutes;
5) and removing the back rough layer 2 and the P + layer 3 of the chip subjected to the annealing process in a back thinning or back etching mode, as shown in fig. 3, and recovering the initial PN structure, as shown in fig. 4.
As shown in fig. 5, compared with the diode chip adopting the conventional platinum doping method, the front platinum concentration of the fast recovery diode chip adopting the method is much smaller than the back platinum concentration.
The working principle of the invention is as follows:
through triple measures of improving the roughness of the back of the chip, introducing a concentrated boron impurity into the back of the chip and depositing platinum metal on the back of the chip, the concentration of platinum on the front of the diode chip is greatly reduced compared with that of the conventional process, the platinum diffusion temperature is further improved due to the fact that the concentration of platinum on the front is greatly reduced, the minority carrier lifetime can be further controlled, and finally the Trr of the fast recovery diode is lower without influencing the reverse breakdown characteristic of the diode.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (5)
1. A platinum doping method for a silicon-based fast recovery diode chip is characterized by comprising the following steps: the method comprises the following steps:
s1: removing a dielectric layer on the back of the chip, simultaneously improving the roughness of the back of the chip to form a back rough layer, and generating a P + layer below the back rough layer to simultaneously enable the boron concentration of the back of the chip to be greater than the boron concentration of the front of the chip;
s2: depositing a platinum metal layer with the thickness of 50-1000 mu m below the back rough layer;
s3: placing the chip subjected to platinum deposition into a diffusion furnace tube or a rapid annealing furnace tube, wherein the annealing temperature is set to be 1000-1100 ℃, and the annealing time is 5 seconds-30 minutes;
s4: and removing the back rough layer and the P + layer on the back of the chip.
2. The platinum doping method according to claim 1, wherein: in step S1, the dielectric layer on the back of the chip is removed by grinding or etching.
3. The platinum doping method according to claim 1, wherein: in step S1, the P + layer is disposed by implantation or boron source diffusion, and the concentration of the P + layer is1×1018-1×1020cm-3The depth is 1-10 μm.
4. The platinum doping method according to claim 1, wherein: in the step S2, the platinum metal layer is disposed by sputtering or evaporation.
5. The platinum doping method according to claim 1, wherein: and in the step S4, the back rough layer and the P + layer on the back of the chip are removed by back thinning or back etching.
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| CN201911283460.9A CN110942989B (en) | 2019-12-13 | 2019-12-13 | Platinum doping method for silicon-based fast recovery diode chip |
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| CN201911283460.9A CN110942989B (en) | 2019-12-13 | 2019-12-13 | Platinum doping method for silicon-based fast recovery diode chip |
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| CN110942989B CN110942989B (en) | 2020-08-11 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111613531A (en) * | 2020-05-26 | 2020-09-01 | 西安微电子技术研究所 | Method for improving switching speed of diode |
| CN114093928A (en) * | 2021-11-11 | 2022-02-25 | 扬州国宇电子有限公司 | Platinum doping method of fast recovery diode |
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| CN103618006A (en) * | 2013-10-30 | 2014-03-05 | 国家电网公司 | A fast recovery diode and a manufacturing method thereof |
| CN105895677A (en) * | 2014-10-21 | 2016-08-24 | 南京励盛半导体科技有限公司 | Back structure of semiconductor device |
| CN107293598A (en) * | 2016-11-25 | 2017-10-24 | 扬州国宇电子有限公司 | A kind of low QRR plane fast recovery diode chip |
| CN108010842A (en) * | 2017-12-14 | 2018-05-08 | 深圳市晶特智造科技有限公司 | The production method of fast recovery diode |
| US10273597B2 (en) * | 2016-06-30 | 2019-04-30 | Infineon Technologies Ag | Method of manufacturing CZ silicon wafers, and method of manufacturing a semiconductor device |
-
2019
- 2019-12-13 CN CN201911283460.9A patent/CN110942989B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103618006A (en) * | 2013-10-30 | 2014-03-05 | 国家电网公司 | A fast recovery diode and a manufacturing method thereof |
| CN105895677A (en) * | 2014-10-21 | 2016-08-24 | 南京励盛半导体科技有限公司 | Back structure of semiconductor device |
| US10273597B2 (en) * | 2016-06-30 | 2019-04-30 | Infineon Technologies Ag | Method of manufacturing CZ silicon wafers, and method of manufacturing a semiconductor device |
| CN107293598A (en) * | 2016-11-25 | 2017-10-24 | 扬州国宇电子有限公司 | A kind of low QRR plane fast recovery diode chip |
| CN108010842A (en) * | 2017-12-14 | 2018-05-08 | 深圳市晶特智造科技有限公司 | The production method of fast recovery diode |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111613531A (en) * | 2020-05-26 | 2020-09-01 | 西安微电子技术研究所 | Method for improving switching speed of diode |
| CN114093928A (en) * | 2021-11-11 | 2022-02-25 | 扬州国宇电子有限公司 | Platinum doping method of fast recovery diode |
| CN114093928B (en) * | 2021-11-11 | 2023-01-13 | 扬州国宇电子有限公司 | Platinum doping method of fast recovery diode |
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