CN110933006B - Parallel digital synthesis method and circuit for FM modulation signal - Google Patents

Parallel digital synthesis method and circuit for FM modulation signal Download PDF

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CN110933006B
CN110933006B CN201911095318.1A CN201911095318A CN110933006B CN 110933006 B CN110933006 B CN 110933006B CN 201911095318 A CN201911095318 A CN 201911095318A CN 110933006 B CN110933006 B CN 110933006B
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phase
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CN110933006A (en
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舒勇
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Chengdu Wavetech Co ltd
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Chengdu Wavetech Co ltd
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/10Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/12Modulator circuits; Transmitter circuits
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/10Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/16Frequency regulation arrangements

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
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Abstract

The invention relates to a parallel digital synthesis method of FM modulation signals and a circuit thereof, which adopts a multipath parallel structure to realize the generation of the FM modulation signals on FPGA hardware, wherein the generation of the FM signals is mainly divided into a baseband signal generation module and an up-conversion module, the baseband signal generation module is used for generating FM baseband signals, the up-conversion module realizes up-conversion, the baseband signals are converted to a designated carrier frequency, the baseband signals are multiplied by the carrier signals, and the two paths of signals are subtracted to finish the frequency spectrum migration of the signals. The invention has the characteristics of variable bandwidth, variable center frequency, easy realization on FPGA and the like.

Description

Parallel digital synthesis method and circuit for FM modulation signal
Technical Field
The invention relates to the field of frequency modulation, in particular to a parallel digital synthesis method and a circuit thereof for FM modulation signals.
Background
FM (Frequency Modulation), frequency modulation. FM is conventionally used to refer to general FM broadcasting (76-108 MHz, 88-108MHz in china and 76-90MHz in japan), and is also a modulation scheme, and even between 27-30MHz in the short wave range, FM is used as a band for amateur radio, space, satellite communication applications. FMradio is known as a FM radio. The modulated signal is a low frequency signal transformed from the original information, i.e. the information to be used is loaded onto the transmitted waveform. For example, a computer uses a high frequency digital signal as a signal from a computer connected to a telephone line to load the digital signal onto an audio signal in the telephone line to perform modulation. But sometimes the modulated signal will be referred to as a modulated signal. FM modulation signal, the amplitude of carrier is invariable, modulation signal control carrier's frequency, make the frequency of modulated signal change according to modulation signal law, FM modulation signal's expression is:
S FM (t)=cos[(ω c t+K f ∫x(t)dt)]……(1)
x (t): modulating the signal;
cosω c t=cos2πf c t: a carrier signal;
ω c : carrier angular frequency;
f c : a carrier frequency;
K f : proportion ofThe constant, called the sensitivity of the modulator.
S FM (t): a modulated signal.
There are two main methods for FM signal generation, direct and indirect. The direct method uses a voltage-controlled oscillator, so that the instantaneous frequency of the voltage-controlled oscillator changes linearly with the change of the modulation signal x (t). The indirect method firstly uses the modulation signal to generate a narrow-band frequency modulation signal, then the narrow-band signal passes through a frequency multiplier to obtain a wide-band frequency modulation signal, and the realization block diagram of the indirect method is shown in figure 1.
The disadvantages of the prior art are: the same problems exist in the FM signal generation process, namely the bandwidth of the FM circuit is generally fixed or the central frequency is not variable in a certain interval, so that the flexibility of the FM circuit is lower and the FM circuit cannot be suitable for generating FM modulation signals with different bandwidths and central frequencies.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a parallel digital synthesis method and a circuit thereof for FM modulation signals.
The aim of the invention is realized by the following technical scheme:
a parallel digital synthesis method of FM modulated signals, the method comprising the steps of:
s1: inputting N phase values of the sine wave of the modulated signal into a frequency synthesizer respectively, wherein the input frequency is f b Forming N sampling branches, wherein the value of N is (1, 16);
s2: the output signal of each frequency synthesizer is respectively input into an adder, delayed by one clock period D and then input into a multiplier for parallel output of N baseband signal phase values FM_phaseN;
s3: the N-way phase value FM_phasen of the baseband signal is respectively input into an adder and then passes through a frequency synthesizer, and the input frequency of the frequency synthesizer is the carrier frequency f c The method comprises the steps of outputting N groups of sine values and cosine values;
s4: each group of sine value and cosine value is input into a subtracter to obtain an N-phase expression FM_SignalN of a modulation signal FM;
wherein omega c For the carrier angular frequency, K f T is the delay time of the clock period D, and n takes on the value of (0, 1,2,3 and … …) as the proportionality constant of the multiplier.
Further, in the step S2, the output signal of the last adder is delayed by one clock period D and then is input to the next adder, and the output signal of the last adder is delayed by one clock period D and then is input to the first adder to form a closed loop.
Further, the delay time T of the clock period D is an FPGA working clock, and the value of the delay time T is 1/150e 6
Further, the frequency synthesizer is a DDS IP core in the FPGA chip, two input parameters are required for the DDS IP core instantiation, one is the frequency of the sinusoidal signal, the other is the phase of the sinusoidal signal, the input of the frequency synthesizer in step S1 is the phase value of the sinusoidal signal, and the frequency input is f b The output is a cos value.
Further, the frequency synthesizer in the step S4 is divided into two input interfaces, which respectively input the phase and the frequency of the sinusoidal signal, and output two paths of signals, one path is a sin value and the other path is a cos value.
The parallel digital synthesis circuit of the FM modulation signal comprises a baseband signal module and an up-conversion module, wherein the baseband signal module is used for generating an FM baseband signal, the up-conversion module is used for realizing up-conversion, and the baseband signal module comprises N paths of phase value output circuits for parallelly outputting phase values FM_phaseN of the N paths of baseband signals;
each phase value output circuit consists of a first DDS, an adder A, a delay clock and a multiplier which are sequentially connected in series, wherein the first DDS is used for inputting the phase value of a sine wave of a modulation signal, and the frequency input is f b The delay clock output end of the last phase value output circuit is connected with the adder A of the first phase value output circuit;
the up-conversion module (S102) comprises N up-conversion branches, and is used for outputting an N-phase expression FM_SignalN of a modulation signal;
each up-conversion branch is composed of an adder B, a second DDS and a subtracter which are sequentially connected in series, wherein the adder B respectively corresponds to a phase value FM_phaseN and a phase angle of an input baseband signal, and the input frequency of the second DDS is f c The output of the system is two paths, one path is sin value, and the other path is cos value.
Further, the first DDS and the second DDS are self-contained DDS IP cores in the FPGA chip.
Further, the delay clock is an FPGA working clock, and the value of the delay clock is 1/150e 6
The beneficial effects of the invention are as follows: the scheme adopts an N-path parallel structure for generating the FM baseband signal, the FM baseband signal generated by the method can well control the bandwidth of the FM baseband signal, the FM baseband signal is easy to realize on FPGA hardware, and meanwhile, the frequency spectrum of the baseband signal is moved to a designated frequency point by adopting the N-path parallel structure in the up-conversion processing, so that a higher center frequency can be obtained.
Drawings
FIG. 1 is a schematic diagram of a prior art FM modulated signal indirect method production;
FIG. 2 is a top level architecture diagram of the present invention;
FIG. 3 is a schematic diagram of a baseband signal generating module according to the present invention;
fig. 4 is a schematic diagram of an up-conversion module according to the present invention.
Detailed Description
The technical scheme of the present invention is described in further detail below with reference to specific embodiments, but the scope of the present invention is not limited to the following description.
The FM signal generated by the invention is used as an interference source signal, the spectrum requirement of the interference source signal is controlled within a certain range, the spectrum analysis of the FM signal is complex, and in order to obtain accurate FM signal bandwidth, the modulation signal is a single-frequency signal, namely x (t) =cos omega b t=cos2πf b t,ω b : modulating the sine wave angular frequency, f b : modulating the sine wave frequency of the signal, wherein the frequency spectrum of the FM signal can be controlled at omega c +K f And (3) inner part. Because the digital signal has the advantages of high flexibility, high precision, small error and the like compared with the analog signal, the invention adopts a digital mode to generate the FM modulation signal, and in order to improve the bandwidth and the carrier frequency of the FM signal as much as possible, the invention adopts a parallel mode to realize the generation of the FM modulation signal, and the specific method is as follows.
A parallel digital synthesis method of FM modulated signals, the method comprising the steps of:
s1: inputting N phase values of the sine wave of the modulated signal into a frequency synthesizer respectively, wherein the input frequency is f b Forming N sampling branches, wherein the value of N is (1, 16);
s2: the output signal of each frequency synthesizer is respectively input into an adder, delayed by one clock period D and then input into a multiplier for parallel output of N baseband signal phase values FM_phaseN;
s3: the N-way phase value FM_phasen of the baseband signal is respectively input into an adder and then passes through a frequency synthesizer, and the input frequency of the frequency synthesizer is the carrier frequency f c The method comprises the steps of outputting N groups of sine values and cosine values;
s4: each group of sine value and cosine value is input into a subtracter to obtain an N-phase expression FM_SignalN of a modulation signal FM;
wherein omega c For the carrier angular frequency, K f The proportionality constant of the multiplier is that T is the delay time of the clock period D, and n takes the values of 0,1,2,3 and 4 … ….
As a preferred embodiment, the output signal of the last adder in the step S2 is delayed by one clock period D and then input to the next adder, and the output signal of the last adder is delayed by one clock period D and then input to the first adder to form a closed loop. The delay time T of the clock period D is an FPGA working clock, and the value of the delay time T is 1/150e 6 . The frequency synthesizer is a DDS IP core in the FPGA chip, two input parameters are needed when the DDS IP core is instantiated, one is the frequency of a sinusoidal signal, the other is the phase of the sinusoidal signal, the input of the frequency synthesizer in the step S1 is the phase value of the sinusoidal signal, and the frequency input is f b The output is a cos value. The frequency synthesizer in the step S4 is divided into two input interfaces, which respectively input the phase and the frequency of the sinusoidal signal, and outputs two paths of signals, one path is sin value and the other path is cos value.
In order to further embody this embodiment, N takes a value of 14 in this embodiment. In this embodiment, the generation of the FM modulation signal is realized on the FPGA hardware by adopting a 14-way parallel structure, and the FPGA working clock is assumed to be 150MHz. The top layer structure is shown in fig. 2. The FM signal generation is mainly divided into two modules S101 and S102, the S101 module is used for generating an FM baseband signal, the S102 module realizes up-conversion and converts the baseband signal to a designated carrier frequency f c On the baseband signal and the carrier signal cos (2pi.f c t) and sin (2pi.f) c t) multiplying and subtracting the two signals to complete the signal spectrum relocation, and the specific circuit thereof can be shown with reference to fig. 3 and 4.
A parallel digital synthesis circuit of FM modulation signals is composed of a baseband signal module S101 and an up-conversion module S102, wherein the baseband signal module S101 is used for generating FM baseband signals, the up-conversion module S102 is used for realizing up-conversion, and the baseband signal module S101 comprises 14 paths of phases for outputting phase values of baseband signals in parallelA value output circuit for outputting the phase value FM_phaseN of 14 paths of baseband signals in parallel; each phase value output circuit consists of a first DDS, an adder A, a delay clock and a multiplier which are sequentially connected in series, wherein the first DDS is used for inputting the phase value of a sine wave of a modulation signal, and the frequency input is f b . The phase angles of the 14 inputs in this embodiment are respectivelyWherein the delay clock output end of the last phase value output circuit is connected with the adder A of the next phase value output circuit, the delay clock output end of the last phase value output circuit is connected with the adder A of the first phase value output circuit, the specific circuit can be shown by referring to FIG. 3, wherein the input signal of the multiplier comprises a signal output by the delay clock and a proportionality constant K f Constant of fixation->I.e. < ->
As shown in fig. 4, the up-conversion module S102 includes 14 up-conversion branches for outputting a 14-phase expression fm_signaln of the modulated signal; each up-conversion branch is composed of an adder B, a second DDS and a subtracter which are sequentially connected in series, wherein the adder B respectively corresponds to a phase value FM_phaseN and a phase angle of an input baseband signal, and the input frequency of the second DDS is f c The output of the system is two paths, one path is sin value, and the other path is cos value. Wherein adders B are used for inputting 14-phase positions FM_SignalN and 14-phase positions FM_SignalN of the baseband signals, respectively
The resulting 14-way signal is a 14-phase expression of the FM signal. Digitizing equation (1), taking t=nt, T as sampling time interval, and summing up the integration, the 14 paths of signals output finally are respectively:
…………
the foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.

Claims (5)

1. A parallel digital synthesis method of FM modulated signals, characterized in that the method comprises the steps of:
s1: inputting N phase values of the sine wave of the modulated signal into a frequency synthesizer respectively, wherein the input frequency is fb, and fb is the frequency of the sine wave of the modulated signal to form N sampling branches, and the value of N is (1, 16);
s2: the output signal of each frequency synthesizer is respectively input into an adder, delayed by one clock period D and then input into a multiplier for parallel output of N baseband signal phase values FM_phaseN;
s3: the method comprises the steps of respectively inputting N paths of phase values FM_phaseN of a baseband signal into an adder, and then passing through a frequency synthesizer, wherein the input frequency of the frequency synthesizer is carrier frequency fc and is used for outputting N groups of sine values and cosine values;
s4: each group of sine value and cosine value is input into a subtracter to obtain an N-phase expression FM_SignalN of a modulation signal FM;
where n is a constant (0, 1,2,3, … …), ωc is the carrier angular frequency, kf is the proportionality constant of the multiplier, and T is the delay time of the clock period D.
2. The parallel digital synthesis method of FM modulated signals according to claim 1, wherein the output signal of the last adder is delayed by one clock period D and then input to the next adder, and the output signal of the last adder is delayed by one clock period D and then input to the first adder to form a closed loop.
3. The parallel digital synthesis method of an FM modulated signal according to claim 2, wherein the delay time T of the clock period D is an FPGA working clock, and the value thereof is 1/150e6.
4. The parallel digital synthesis method of FM modulated signals according to claim 1, wherein the frequency synthesizer is a DDSIP core of the FPGA chip, two input parameters are needed for the DDSIP core instantiation, one is the frequency of the sinusoidal signal, the other is the phase of the sinusoidal signal, the frequency synthesizer input in step S1 is the phase value of the sinusoidal signal, the frequency input is fb, and the output is one cos value.
5. The parallel digital synthesis method of FM modulated signals according to claim 4, wherein said frequency synthesizer in step S4 is divided into two input interfaces, respectively inputting the phase and frequency of the sinusoidal signal, outputting two signals, one being sin value and one being cos value.
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