JP2007525853A - Wideband direct digital synthesizer - Google Patents

Abstract

  The signal generator and DDS of the frequency synthesizer require a relatively high input clock speed and produce a spurious frequency response where unwanted components are present in the output frequency spectrum. Systems and methods are provided for reducing or avoiding spurious DDS responses by changing the clock signal input to the DDS.

Description

  The present invention relates to a signal generator, a frequency synthesizer, a signal generator and / or a device incorporating a frequency synthesizer.

  Many electronics applications and systems require the use of one or more signals having a specific frequency and / or phase. For example, wireless transmitters and receivers often use local oscillator signals for up-conversion and down-conversion. Accordingly, methods and apparatus (including problem solving based on a phase locked loop (PLL)) have been developed to generate such signals.

  Another device used to generate the signal is a direct digital synthesizer (DDS). In general, a DDS receives an input clock signal and a control word. Based on the control word, possibly subsequent timing (read, write, update control, etc.), the DDS outputs a waveform (eg, a sine wave) having a known frequency and / or phase relative to the input clock signal. To do. For example, a DDS typically includes a phase accumulator that indicates the phase state of the current output sample, and a look-up table that indicates the amplitude corresponding to that phase state. Control words are loaded into DDS registers (eg, phase accumulators). The DDS then determines the desired frequency and / or phase of the output signal based on lookup table information associated with the received input control word. DDS devices available from integrated circuit manufacturers include the AD98XX series available from Analog Devices, Norwood, Massachusetts. Other DDS manufacturers include Harris in Melbourne, Florida, Intersil in Melbourne, Florida, and Intel in Santa Clara, California.

  A standard DDS includes a phase accumulator, a phase / amplitude converter, and a digital-to-analog converter (D / A converter). The DDS core without a D / A converter is also called a numerically controlled oscillator (NCO). Each implementation varies from design to design, but phase accumulators, phase / amplitude converters, and D / A converters are standard components for DDS.

  One such change is a specific example of a phase / amplitude converter. This converter (which typically uses a look-up table stored in memory) receives the phase at a given sample and outputs the corresponding amplitude. However, in such an embodiment, only the most significant portion of the phase value is used due to memory size limitations of the current design. Thus, the table truncates the least significant bit X (X varies between designs and between devices) and uses only the most significant bit Y. In addition, the specific example of the table changes. For example, the amplitude is repeated in 90 ° increments, and only the amplitude sign changes with the quadrant. Thus, many look-up tables use only 90 ° in the look-up table, along with sign bits that specify what quadrant the phase is in.

  The DDS may be configured as a frequency divider. In such a case, the control word is the desired frequency and / or phase of the output signal (the frequency is processed through the DDS core and the phase offset is added), the desired output signal (the output frequency depends on the accumulator value and Specified as the ratio of the input clock signal (based on the clock rate).

  Since the DDS output is generated using digital processing, the DDS based problem solver provides significantly reduced phase noise compared to the analog based problem solver. For example, analog problem solvers use an error correction loop to determine the phase / frequency of the output. In such cases, the transfer function that determines the extent of correction (eg, bandwidth) is inversely proportional to the time required for correction, thereby sacrificing speed due to phase noise or vice versa. In addition, DDS-based problem-solving means can provide highly accurate tuning resolution of output frequency (eg, microhertz tuning resolution) and less than 1 ° phase tuning. In addition, DDS-based problem solving techniques such as occur with extremely fast speeds in tuning to output frequency or phase, phase continuous frequency switching without overshoot / undershoot, and analog-based (eg, loop) problem solving techniques. Offers advantages such as little or no settling time. Also, DDS-based problem solving means require manual system tuning and fine tuning due to component degradation and temperature drift (which is often a problem with analog-based problem solving means, for example). Reduce or eliminate.

  However, DDS-based problem solvers require relatively high input clock speeds and produce spurious frequency responses in which unwanted components are present in the output frequency spectrum.

One cause of spurious output components (or “intermodulation components”) is phase truncation errors. For example, the number of entries in the DDS output look-up table is less than the maximum number of possible amplitudes that can be specified by the digital control word, eg, based on the length of the DDS accumulator register that receives the control word for decoding Sometimes a phase truncation error occurs. For example, a DDS with a 32-bit phase accumulator can clearly specify 2 ³² distinct phases. Providing amplitude entries corresponding to each of these 2 ³² possibilities requires a phase lookup table containing 4,294,967,296 entries, and 4,294,967,296 entries. It is not feasible to provide a phase lookup table that includes Thus, the look-up table contains fewer entries than the maximum number of possible amplitudes, and the DDS determines the phase accumulator value resulting from the input control word for the phase closest to the exact value specified by the state of the phase accumulator, Or associate.

  Further, the amplitude of the truncation error intermodulation component varies periodically over a period of time based on the overflow characteristics of the phase accumulator (also known as the Grand Repetition Rate). The change in truncation error amplitude over time defines a periodic waveform with a sufficiently high range of frequency spectrum, and the higher order harmonics of the truncation error waveform generate aliasing in the Nyquist bandwidth. Additional information on DDS phase truncation errors, other errors, and spurious responses is available from industry sources, for example (published in 1999 by Analog Devices, http://www.analog.com/UploadedFiles/Tutorials / 3343533079104002517 Includes "A Technical Tutorial on Digital signal Synthesis" (available online at DDStutor.pdf).

  The spurious response appears at a frequency that is relatively close to the output frequency of the DDS. This aspect is particularly troublesome for system designers. In narrowband applications, for example, to avoid these “close range” responses, the DDS input clock can be set to a single frequency or a very narrow tuning band. However, limiting the input clock range also limits the output signal tuning range of the DDS.

  In general, errors during the digital / analog conversion (D / A converter) process are a significant source of spurious responses. Such errors include quantization error and D / A converter nonlinearity. In general, errors introduced in D / A converters (related to clock frequency and output frequency) are highly predictable.

  Embodiments of the present invention include systems and methods for utilizing DDS-based signal generator problem solvers for broadband applications. Such embodiments also provide systems and methods for reducing or avoiding spurious DDS responses by changing the clock signal input to the DDS.

  At least one embodiment of a signal generator according to the present invention includes a clock generator having a first direct digital synthesizer (DDS) configured to generate a composite signal based on a clock source signal. The signal generator further includes a clock divider having a second DDS configured to generate the divided signal based on (1) the combined signal and (2) a control signal indicating the division ratio. In addition, these embodiments include a selectable filter configured to generate a filtered signal based on the split signal. Selectable filter selections include control signals, selected output frequencies (eg, selected by the user or by hardware or software components of the application), split signals (based on the selected output frequency) And / or other values based on the selected output frequency (eg, frequency ratio). In at least one embodiment, the number of filters that can be selected is four.

  In at least one embodiment, the signal generator further includes a frequency converter configured to generate the converted signal based on the filtered signal. In some embodiments, the frequency converter is a mixer that receives a local oscillator (LO) signal, a frequency doubler, or a multiplier (eg, including a step recovery diode (SRD)). The use of a multiplier introduces spurious components but is also transformed.

  In at least one embodiment, the clock divider is configured to generate a split signal having a main frequency that is 2.5 times lower than the main frequency of the composite signal by subsequent filtering.

  Further, the clock divider is configured to generate the second divided signal based on (1) the synthesized clock signal and (2) a second control signal indicating the second frequency ratio. Includes 3 DDS. In such an embodiment, one selection of a plurality of selectable filters is provided based on the second control signal. In at least one embodiment, the number of filters that can be selected is four.

  In addition, in at least one embodiment, the second DDS (or third DDS) includes a table of output values, the split signal is (1) a synthesized clock signal, and (2) a frequency ratio, and It is determined based on a table of output values in response to the control signal instructing the phase / amplitude conversion. In these embodiments, the second DDS outputs the change to the split signal at a frequency substantially equal to the frequency of the synthesized clock signal without a complete phase / amplitude conversion. Since the output divided signal is a phase value of an integer or integer ± subset (for example, 0.5), the size of the lookup table can be reduced.

  Further, in at least one embodiment, a second DDS (or third DDS) is pre-introduced to output the split signal in response to receiving a clock signal synthesized at a predetermined frequency. The

  A method for generating a signal according to another embodiment of the present invention uses a first DDS for generating a clock signal, and generates a signal based on the clock signal to generate a half of the clock signal. Using a second DDS having substantially equal frequencies. Such a method also includes providing a phase offset value to the second DDS.

  A method for generating a signal according to another embodiment of the present invention includes providing a first signal to a clock input of a DDS and generating an output signal based on the first signal to generate a half of the clock signal. Using a DDS having a frequency substantially equal to. Such a method also includes providing a phase offset value to the DDS.

  A method for generating a signal according to another embodiment of the present invention includes generating an output signal to use a DDS having a desired frequency component and a spurious frequency component, monitoring the intensity of the spurious frequency component, and the monitoring. And changing the phase offset value of the DDS based on the result of.

  In addition, embodiments of the present invention include transmitters, receivers, transceivers, test equipment, satellite communication systems, and signal generators described herein (eg, utilized as local oscillators), and such devices. Including radar systems including methods to use.

  Furthermore, the present invention will be described in terms of exemplary embodiments. These exemplary embodiments are described in detail with reference to the figures. These examples are exemplary, not limiting, and like reference numerals represent like structures throughout the drawings.

  Unless otherwise specified, the terms “signal generator”, “synthesizer” and “frequency synthesizer” are used interchangeably herein. Embodiments described as “exemplary” merely refer to illustrative examples and need not be preferred over other embodiments.

  Embodiments of the present invention include, for example, a synthesizer architecture suitable for signal generation in wideband applications. In at least one embodiment, the DDS synthesizer includes a clock generator configured to provide an adjustable (or varying) clock input to one or more other DDSs. The operation of such a device includes selecting the output frequency of the clock generator (including DDS) to prevent or reduce spurious components of the output of the subsequent one or more DDSs. Such an embodiment is applied, for example, to generate signals over a wide frequency range.

  FIG. 24 shows a block diagram of the signal generator 10 according to an embodiment of the present invention. The clock generator 101 (including one or more DDSs) generates a synthesized clock signal based on a clock source signal (not shown). The divider 105 (including one or more DDSs) receives the synthesized clock signal (or a signal based thereon) and generates a divided signal based on the synthesized clock signal and ratio. A selectable bank of filters 167 receives the split signal (or signal based thereon) and a selected one of the filters is applied to filter the signal to produce an output. The selection of selectable filters is based on the ratio. In addition, embodiments of the signal generator 10 described herein may be selected from components such as filters, frequency converters, switches, and / or dividers 105 between the clock generator 101 and the divider 105. Analog adder (in the signal path between the filter 167 and / or downstream of one or more selectable filters 167)

  FIG. 1 shows a functional block diagram of a synthesizer 100 including two specific examples 20 a and 20 b of the signal generator 10. The synthesizer 100 is configured as a wideband local oscillator signal generator (eg, including a first agile clock generator 101 configured to provide a first clock signal). In this specific example, the clock generator 101 receives a first clock source signal (and possibly other signals) from the clock distribution unit 110. For example, the clock distribution unit 110 generates or receives a 300 MHz clock signal input, and outputs a 300 MHz clock signal to the clock generator 101 based on the signal. In other implementations, the clock generator 101 includes an oscillator configured to generate a first clock signal, or a precursor of such a signal. Such an oscillator is a crystal oscillator (eg, a temperature controlled crystal oscillator, or TCXO), or other suitable device.

  In at least one embodiment, clock generator 101 generates a DDS clock signal input to clock divider 102. The clock generator 101 includes a step recovery diode (SRD) and associated circuitry for clock generation (eg, by multiplying with a clock signal having a low frequency). The clock divider 102 is configured to output a divided signal based on the DDS clock signal input and the state of the control word.

  2 and 3 provide additional details regarding possible implementations of the clock generator 101 and the clock divider 102, respectively. As shown in FIG. 2, the clock generator 101 includes a DDS 151 coupled to a variable bandpass (and / or switch bandpass) filter 153, and the output of the variable bandpass (and / or switch bandpass) filter 153. Is provided to frequency converter 155. The variable bandpass filter 153 removes artifacts due to the clock signal and other artifacts (eg, aliases and spurious responses).

  The term “frequency converter” as used herein includes devices such as frequency multipliers (eg, circuits including SRDs and mixers). The frequency converter 155 is implemented as a mixer that receives the first local oscillator signal and generates an upconverted output DDS clock signal. In at least one embodiment, the first local oscillator signal is derived from the same base as the clock signal provided to the DDS 151 by the clock distribution unit 110, and may be the same signal. Further, the output DDS clock signal is implemented as a continuously adjustable sine wave over a range (eg, any frequency across the output band of DDS 151). The output DDS clock signal is filtered using one of a plurality of selectable bandpass filters (or a switch bandpass filter, or a single filter) 157 to generate a filtered output DDS clock signal. The

  As shown in FIG. 3, the clock divider 102 includes a DDS 161 that receives an output DDS clock signal from the clock generator 101. The DDS 161 generates a split signal that is provided to a variable bandpass (or switch bandpass or single) filter 163 that is coupled to the output of the DDS 161. The variable bandpass filter 163 removes artifacts due to clock signals and other artifacts (eg, aliases and spurious responses). The divided signal output by the DDS 161 is, for example, a sine wave that can be adjusted over a wide frequency range.

  Next, the filtered divided signal is a frequency converter 165 configured to generate a transformed divided signal (eg, by mixing the filtered divided signal with a second local oscillator signal). Provided to. The transformed (eg, upconverted) split signal is filtered using one of a plurality of selectable bandpass filters 167 that produce a filtered upconverted split signal. In at least one embodiment, DDS 161 selects a particular bandpass filter 167 based on the state of the control word.

  In some embodiments, the divided signal output by clock divider 102 has a frequency that is at least twice (but less than three times) the DDS clock signal received from clock generator 101. In at least one embodiment, the split signal has a frequency 2.5 times lower than the DDS clock signal. In such an embodiment, it is sufficient to provide output filtering to only suppress images that appear at 0.5 and 1.5 times the output frequency. Thus, only the partitioning limit around the integer value 2 is the limit imposed by the sampling characteristics of the digital architecture, which introduces errors in the bandwidth of interest to the image.

  In at least one embodiment, it has been found that a suitable number for the set of selectable bandpass filters 157, 167 is 4, and each of the bandpass filters 157, 167 filters each input signal. To be selected separately. In at least one embodiment, each filter in the set of filters 157, 167 is assembled using individual components, and the individual components are separate components for each filter. Alternatively, if a selectable input frequency to the agile clock generator is used, 4 has been found to be an appropriate number for the set of selectable bandpass filters 153,163. The use of a selectable input frequency to the agile clock generator 101 is further advantageous in increasing the bandwidth free of intermodulation components of the clock generator 101 output.

  Each filter that makes up the set of filters 157, 167 (and other sets of selectable bandpass filters) has a different bandpass frequency range and a smaller (or more) compared to the other filters in the set. A large) relative bandpass range (i.e., the size of the filter range calculated as the difference between the high and low frequency cutoffs for the filter). Depending on the specific application (or design) requirements and / or tolerances, adjacent passbands may overlap (or not overlap). One possible arrangement of the passbands of a set of filters is similar to a series of octaves.

  For example, filter set 157 has four filters and is implemented to pass the band 50-200 MHz. If individual filters are implemented to have equal width passbands, each passband is centered at 50, 100, 150, and 200 MHz, and each filter passes a band ± 25 MHz from the center frequency. Such a distribution is not suitable for removing the images at 0.5x and 1.5x from the 50 MHz output frequency, however, the 25 MHz and 75 MHz images are inside (or at least the edges) of the passband of the 50 MHz filter. )It is in. Thus, other distributions of the filter center frequency and / or passband are more desirable. For example, the same center frequency may be used with a filter having a passband that gradually increases as the center frequency increases. Alternatively, the filter may have non-uniformly distributed center frequencies. For example, an octave or half-octave distribution (eg, 50-70-100-140) is used instead with each filter having a passband slightly narrower than the center frequency.

  The DDSs 151 and 161 receive one or more control words that cause the DDS to generate an output signal having a specific frequency and phase. For example, the control word includes digital phase and frequency information. Control words are stored by DDS 151, 161, for example, in a phase accumulator (or other registers for decoding and processing).

  In at least one embodiment, the DDS phase accumulator used in the embodiment (eg, DDS 151 or DDS 161) can add the digital information contained in the received control word to the binary value already in the accumulator (eg, modulo-2 addition). In addition, a new frequency / phase index value is formed. The DDS then determines the frequency and phase of the signal from the phase lookup table using the newly formed frequency / phase index value and outputs from the DDS.

  More particularly, in at least one embodiment, one or both DDSs are phase continuous. That is, when a new accumulator value is written to the accumulator, the DDS accumulates the current value in the phase accumulator. When a new frequency value (phase accumulator value) is written, the new frequency value accumulates or adds to the final value in the accumulator unless the DDS is deliberately reset to the phase accumulator value 0.

  In an embodiment, the clock divider 102 is pre-introduced to output the divided signal at a predetermined frequency in response to receiving the DDS clock signal input.

  Table 1 below provides specific examples of frequency planning and controls specific examples of DDS 151 ("DDS1") and DDS 161 ("DDS2") for performing the signal synthesis operations described herein. Control information used for the purpose. In at least one embodiment, control logic is used to control the function of DDS 151, 161 according to Table 1 to generate a particular split signal. For example, one or more control words are loaded into the control register of the DDS. This logic may include, for example, a gate-based logic design embodied in a rewritable gate array (FPGA), an application specific integrated circuit (ASIC), a series of discrete components, and / or (read only memory (ROM), Using instructions executable by a processor stored in memory that is programmable ROM (PROM), erasable PROM (EPROM), non-volatile random access memory (NVRAM), flash memory, or variations thereof) To be implemented.

  In this embodiment, the output of DDS1 (151) is upconverted by 300 MHz before input to DDS2 (161). DDS2 (161) applies the selected split ratio and its output signal is doubled to obtain the desired output signal. Given a predetermined selected output frequency, a known range of acceptable split ratios, and a known set of available up-conversion choices, the control logic selects an appropriate output frequency for DDS1 (151). To be implemented.

  In at least one embodiment, the clock divider 102 includes an amplitude value lookup table that is used to directly specify the split signal output (eg, without converting the phase value). For example, in the response to the control word, the output value is determined based on the amplitude value table. In at least one embodiment, clock divider 102 outputs the new value of the divided signal at a frequency substantially equal to the frequency of the DDS clock signal without a complete phase-amplitude conversion. The DDS 151 look-up table for the clock generator 101 also includes predetermined entries to reduce or prevent the occurrence of spurious components in the frequency spectrum of the DDS clock signal generated by the clock generator 101. .

  In at least one embodiment, the spurious content is reduced by tuning the divider DDS to an integer (or integer ± 0.X) value (where X is a number). More specifically, X is equal to 5. However, other values for X are possible (eg, 1). Alternatively, X may be a real number. This selection has the effect of masking spurious responses (eg, images generated by D / A converter errors (eg, quantization and non-linearity)) below the fundamental frequency (output frequency). For exact integer division values, the total spurious content due to D / A converter error is categorized as a fundamental frequency term. Integer value ± 0. For X, some spurious content is classified into fundamental frequency terms and the remaining remaining spurious content is classified into frequency terms equal to the output frequency ± (0.X * output frequency). Thus, the number of filters and the need for rejection can be determined based on a range where there is no spurious output frequency.

  FIG. 3A shows another embodiment of clock divider 102 and frequency converter stage 120. As shown in this figure, the clock divider 102 includes a DDS 161 that receives the clock signal output by the clock generator 101. DDS 161 generates a filtered split signal using one of a plurality of selectable bandpass filters 167 to generate a filtered split signal. In at least one embodiment, DDS 161 selects a particular bandpass filter 167 based on the state of the control word. For example, the divided signal output by the DDS 161 is a sine wave that can be adjusted over a wide frequency range.

  The filtered split signal is provided through a drive circuit 169 to a frequency converter stage 120 where the filtered split signal is converted to produce a converted split signal. The frequency converter 121 is implemented using, for example, a comb generator including a snap-off diode (step recovery diode) as a multiplier. Alternatively, the frequency converter 121 includes a mixer configured as a frequency doubler (or “dedicated multiplier”), and the input signal is coupled to both the RF input and LO input of the mixer.

  The converted split signal is filtered using one of a plurality of selectable bandpass filters 123 to produce a filtered and split split signal. For example, the number of bandpass filters that can be selected is four. In at least one embodiment, DDS 161 selects a particular bandpass filter 123 based on the state of the control word. Thus, the filtered and transformed split signal is provided to one or more frequency converters through a drive circuit 125 (eg, a buffer, amplifier, or impedance matching network) to generate other frequencies of interest.

  FIG. 4 shows a detailed functional block diagram of an embodiment of frequency converter stage 130. As shown in this figure, the frequency converter stage 130 that outputs the first portion of the first local oscillator signal includes a frequency converter 131 (coupled to the frequency converter stage 120), and the frequency converter The output of 131 is coupled to one or more selectable bandpass filters 133, 134 through switches 132, 135. In at least one embodiment, frequency converter stage 130 selects bandpass filter 133 or bandpass filter 134 based on the frequency of the received (filtered and transformed) split signal. In the embodiment, the number of bandpass filters that can be selected at this stage is two, but more or less than two filters may be used as appropriate.

  The bandpass filters 133, 134 are selected based on the desired output frequency of the stage (or the intermediate frequency required to perform the conversion to the desired output frequency). For example, in the specific example shown in FIG. 4, either the 1100-1300 MHz bandpass filter 133 or the 1300-1500 MHz bandpass filter 134 is the desired output frequency for the first frequency converter stage 130. The output frequency range is 1100 MHz-1500 MHz. As shown in FIG. 4, the 100-300 MHz intermediate frequency (IF) input from the preceding stage 120 is mixed with either 1000 MHz or 1200 MHz to produce the output.

  In at least one embodiment, control logic is used to select filter 133 or filter 134 based on the desired output frequency. The control logic is implemented using (but not limited to), for example, an FPGA, ASIC, ROM device, or software as described above. The control logic first determines the provided output frequency and then determines the local oscillator frequency required to be upconverted to the final output. In an embodiment, if the desired output frequency is 1100-1300 MHz, a 1000 MHz local oscillator signal is selected as shown in FIG. 4 and 100- 100 using frequency converter 131 to produce 1100-1300 MHz. Mixed with 300 MHz. On the other hand, if the desired output frequency is 1300-1500 MHz, the 1200 MHz local oscillator signal is selected and the 1300-1500 MHz filter 134 is selected. In at least one embodiment, selecting the LO signal and the filter is performed using the same control signal. Additional details regarding control logic and control flow are described with respect to FIG.

  FIG. 5 shows a detailed functional block diagram of an embodiment of frequency converter stage 140. As shown in this figure, the frequency converter stage 140 has a plurality of selectable bandpasses in a first position to generate a filtered signal that the frequency converter stage 140 receives. It includes a set of switches 144, 145 configured to provide to a frequency converter 141 (eg, a mixer) coupled to one of the filters 142. In at least one embodiment, frequency converter stage 140 selects a particular bandpass filter 142 based on the final output frequency required at the output of frequency converter stage 140. In the second position, the switches 144 and 145 cause the frequency converter stage 140 to output the signal received by the frequency converter stage 140. In either case, the second stage signal through switch 145 is provided through driver circuit 146 as the first local oscillator final output signal. In the particular embodiment shown in FIGS. 1 and 5, the first local oscillator signal output by this stage has a frequency of 1100 MHz-2100 MHz.

  In at least one embodiment, filtering and up-conversion selection, or switch settings for bypass, are controlled by the control logic, stage output frequency, desired final output frequency of the first local oscillator LO1 (eg, 1100-2100 MHz), Or selected based on the intermediate frequency used for up-conversion to generate one of these. A filter is selected that has a passband in the output frequency range and attenuates unwanted terms (eg, local oscillator input in case of upconversion). If the frequency converter stage 140 is not configured for up-conversion (eg, the output frequency is 1100-1500 MHz), the frequency converter 141 is bypassed and the previous stage (eg, the frequency conversion of FIG. 4). The output frequency from the instrument stage 130) is used.

  As shown in FIG. 1, in at least one embodiment, synthesizer 100 is coupled to a second signal generator (ie, second divider 104) configured to generate a second local oscillator signal. A second clock generator 103). The clock signal received from the clock distribution unit 110 by the second clock generator 103 has the same frequency as the clock signal received by the first clock generator 101. Alternatively, the clock distribution unit 110 provides signals having different frequencies to the second clock generator 103. The structure and operation of the second clock generator 103 and the second divider 104 are substantially the same as those described for the first clock generator 101 and the first divider 102 of FIGS. 1-3A. Is the same. The second local oscillator signal has a frequency of 48 MHz-94 MHz, for example. To generate a higher local oscillator frequency, the output of the second divider 104 is coupled to the upconverter and / or one or more synthesizer stages.

  In at least one embodiment, synthesizer 100 provides a third local oscillator signal. The third local oscillator signal has one of the frequencies of, for example, 300 MHz, 500 MHz, or 1100 MHz. In an embodiment, clock distribution unit 110 includes one or more step recovery diodes (SRDs) configured to generate a third local oscillator signal.

  Alternatively, changing the adjustable clock source may be configured using other than a DDS method and apparatus that provides a clock for the second (or later) DDS. An example of such a variable (adjustable) clock source is a phase locked loop. Phase locked loops are slow to tune, but such devices provide low power consumption (down to milliwatts) and / or small size (eg, due to reduced filtering requirements) compared to DDS. In such an embodiment, the variable frequency clock signal is received by a clock divider, which was described with respect to FIGS. 1-3A.

  In another embodiment, synthesizer 200 includes a clock generator 201 that is coupled to two or more dividers (eg, dividers 202-204 as shown in FIG. 6). In at least one embodiment, one or more dividers 202-204 are implemented using DDS. For example, multiple clock dividers are used to reduce or eliminate the time taken to load a new division ratio or control word into the DDS divider. In one implementation, one or more clock dividers 202-204 may use a particular division ratio, control word, and / or output frequency / phase to achieve a uniformly fast switching time (ie, Pre-configured (before being selected for signal path). In typical applications, such an architecture is used to “ping-pong” (or “hop”) very quickly between (or in) different frequencies.

  For example, the one or more clock dividers 202-204 include a plurality of registers for pre-loading different predetermined divider values, and the dividers can use one of the pre-loaded divider values, Control logic can select in response to a signal provided earlier than the time it takes to load each divider separately outside the divider. The control signal is provided when (or before) the divider is selected for the signal path.

  Alternatively, each of the plurality of dividers 202-204 is preconfigured with each single divider value (or preloaded with each single divider value), and each divider has a very fast tuning speed. To achieve this, a separate selection is made earlier than the time it takes to load each divider separately (eg, by switch 205). In at least one embodiment, dividers 202-204 have parallel load control word registers (as opposed to serially loaded registers).

  Although FIG. 6 shows three dividers 202-204, it is noted that any number of dividers (or dividers DDS) can be used in various embodiments. The architecture can also be implemented to include a switch between the clock generator 201 and the dividers 202-204.

  In other embodiments, the divider chip has the property of selecting multiple (eg, 4 or 8) different pins so that fast frequency switching is achieved during operation as described for FIG. In addition, each characteristic includes a respective control word (or division ratio). In one embodiment, such a divider chip provides a phase continuity that switches between two different frequencies. Alternatively, the architecture of FIG. 6 replaces switch 205 so that multiple dividers (eg, outputs from 202-204) combine to provide a modulated output signal (or desired waveform). This is done using an analog adder (or in addition to switch 205).

  Further alternatively, at least one of the dividers 202-204 may be a frequency divider that is not based on DDS. For example, such a frequency divider includes a logic chip (eg, TTL, ECL) or is configured to use discrete components, or includes an integrated circuit that can output a divided frequency. Alternatively, such a divider generates a divided signal in response to the selection signal by one of a plurality of different division ratios. Such an embodiment is such that the clock generator 201 requires that in a particular application, at least one of the dividers 202-204 has a frequency range that is greater than the embodiment implemented using DDS. Reduce the set of available split ratios.

  As shown in FIG. 7A, a synthesizer 700 according to another embodiment includes a clock generator 701 coupled to a first divider stage 710, where the output of the first divider stage 710 is a second Coupled to splitter stage 703. In such embodiments, at least one (or all) of the clock generator 701, the first divider stage 710, and the second divider stage 703 are implemented using DDS, for example, the clock generator 701 includes a first DDS that is coupled to a second DDS that implements a first divider stage 710, and the first divider stage 710 includes a second divider stage 703. It is coupled to the third DDS that is running. For example, the third DDS (or second stage divider) substantially reproduces the second DDS (or divider) of the above embodiment.

  Advantages of using a third DDS coupled in series to the output of the second DDS include more accurate tuning resolution (eg, microhertz resolution) and / or further spurious component suppression. In addition, a first DDS (eg, an agile clock or clock generator DDS) with increased tuning resolution (but reduced spurious performance) is used. In such an embodiment, the spurious component generated by the first DDS (eg, Agile Clock Generator DDS) is, for example, 20 log [(second DDS split value) * (third DDS split value) ] Is reduced. Thus, the addition of a third DDS further reduces the spurious response created by the first DDS (eg, an agile clock generator) while providing more accurate tuning resolution. As in other embodiments, one or more DDSs are preloaded for quick frequency switching. Further, as shown in FIG. 7B, the first divider stage 722 is implemented to include two or more dividers (eg, dividers 710, 711). Such dividers have outputs that are selectable (eg, via switch 712) or combinable (eg, to obtain a modulated signal, or other waveform).

  With respect to clock divider 102, in at least one embodiment, DDS 161 includes a table of amplitude values that are output directly to the D / A converter at the rate of the input clock. Such an architecture bypasses the phase-to-amplitude conversion of current DDS architectures, thus eliminating the need for control word input. The amplitude value table is only for small (or integer ± 0.5) ratios, as the control word is replaced by a signal specifying the integer (± 0.5) ratio to which it is applied. Implemented). More specifically, such embodiments use, for example, integer values ± 0.5 and / or ratios of integer values ± 0.1, ± 0.2, ± 0.3, or ± 0.4. May be. Other acceptable problem solving measures include a non-integer ratio divider DDS that has been found to provide a wide band without spurious response (eg, as shown in FIG. 23). This approach is flexible to meet specific requirement specifications (eg, application bandwidth, dynamic range without spurs, requirement specification size, etc.).

  In an embodiment, the above synthesizer is implemented using an integrated circuit device as a programmable divider chip DDS for use in signal generation. The chip is programmed by sending it to a specific split ratio that indicates the corresponding sine wave (or cosine) value for use in each clock cycle. The output is a sine wave, but other waveforms are possible. Such a programmable divider chip is designed for a specific application (eg, an application using a dual DDS configuration) and thus utilizes a simplified (or streamlined) design. In the case of a dual DDS synthesizer, one DDS is used to synchronize a second DDS that is operable to function only at a specific split ratio for a specific spectral purity relationship.

  As discussed above, dual DDS synthesizers are implemented to have the advantage of reducing intermodulation components. Spurious response is one feature of previous DDS architectures that limited the widespread use of DDS, especially for wideband applications. Since the clock is related to the adjusted output frequency, at a predictable interval of the clock, the DDS has many adjacent spurious responses. In narrowband systems, the clock is set to a single frequency to avoid these adjacent responses, but this also limits the tuning range. Therefore, these spurious responses prohibit the use of existing DDS architectures in broadband systems.

  In at least one embodiment of the invention, the first DDS provides an adjustable clock to the second DDS, and the adjustable clock is necessary to mitigate the inherent spurious region of the second DDS. As it is, it allows the input clock to the second DDS to be adjusted. This configuration removes and / or significantly reduces adjacent spurious responses in order to take advantage of the desired benefits of DDS, where the desired benefits of DDS include excellent phase noise and fast tuning speed. Since the cleanest output spectrum is obtained in integer and half-integer ratios, the DDS chips dedicated to these split ratios are optimized for their function.

  Another embodiment of the invention includes a programmable divider chip. Such DDS synthesizer chips (particularly configured as divider DDS) are utilized in a variety of wideband applications where fast tuning and low phase noise characteristics are desired. These applications may include (but are not limited to) signal monitoring, electronic warfare, test equipment, transmitters, radar, and data communications. Specific advantages of divider DDS (eg, compared to analog design) include a simpler design, a faster design, a smaller tuning word, a lower spurious response, a higher fidelity, and a lower phase jitter. .

  As shown in FIG. 8A, a programmable divider chip according to an embodiment of the present invention includes three parts: a division ratio-address mapping unit 801, a lookup table 802 (eg, sine and / or cosine), and A digital-analog converter (D / A converter) unit 803 is included. The split ratio-address mapping unit 801 (which outputs an array of addresses for the lookup table 802 according to the indicated split ratio) may be implemented in a number of different ways and selected split ratios (eg, a series of 2 .., 5, 3, 3.5, 4, 4.5,. For example, when dividing by 4, the mapping unit 801 outputs every 90 ° (or 0 °, 90 °, 180 °, etc.) output to the D / A converter 803 at one address / angle rate per clock cycle. And the address of the look-up table 802 for sine (or cosine) values for 270 °. Thus, one complete cycle of output divided by 4 is generated in 4 clock cycles. When divided by 2.5, the mapping unit 801 indicates addresses for sine values for 0 °, 144 °, 288 °, 432 °, and 576 ° output to the D / A converter 803 at the same rate. . In this case, two complete cycles of output divided by 2.5 are generated in five clock cycles. Operations for other split ratios can be inferred from this logic. Such chips also include selectable characteristics described herein (eg, selectable pins).

  Such an embodiment provides a sine wave (or cosine wave) output, but other embodiments of this basic structure are possible. As shown in FIG. 8B, one embodiment includes a lookup to a split ratio ROM, such as one function 802. Another example is a look-up table based on non-sinusoidal waveforms (eg, triangular, sawtooth, or other waveforms).

  Table 2 below lists examples of incremental phase values used to generate a particular split ratio.

  Many values are reused, as recognized by considering the number of phase increases. For example, a division by 12 has 12 values every 30 ° and encompasses all 6 values of a division by 6 having a value every 60 °. Such number reuse (and a consequent reduction in the size of the lookup) allows for the simplification of the DDS realized in the example.

  The use of DDS at a split ratio of 2 (ie Nyquist frequency) is currently unknown. One possible reason is that the DDS shows a decrease in output signal strength up to 20 dB (or greater than 20 dB) at an integer ratio of 2 compared to output signal strength at a higher split ratio.

  Some DDS (eg, Analog Devices 98XX series DDS) include measures to add the phase offset value to the phase value output by the phase accumulator (eg, prior to digital to analog conversion). The inventor has discovered that by selecting a phase offset of 90 ° (or 270 °), the output signal strength is achieved at an integer ratio 2 comparable to the result at higher division ratios (eg, FIG. 25).

  As described herein, such techniques are used for certain advantages with DDS driven by a variable frequency clock (eg, PLL, or other DDS). In one such application, the divider DDS is configured with a division ratio of 2 and a phase offset of 90 °. Synchronizing the PLL (or DDS) is used to provide frequency variability (and / or wideband operation), while the divider DDS is phase continuous (and / or relatively spurious free). Is used at half the clock frequency. It is confirmed that different phase offset values provide similar advantages to other DDS modules.

  The adjustment of the phase offset value of the DDS is performed by dividing the division ratio X. 5 (where X is an integer greater than or equal to 2) (see, eg, FIG. 26). In a method according to another embodiment of the invention, a phase offset value is selected to provide a reduced spurious signal strength (and / or increased output signal strength).

  As noted above, D / A converter nonlinearity increases spurious content. In general, D / A converter nonlinearity is greater at higher frequencies. One reason for this effect is that the output at the lower split ratio is converted using fewer data points than the output at the higher split ratio. Perhaps because of this effect, the operation of DDS at a split ratio of 2.5 is currently unknown. Filters (and other techniques) that allow such operation are described herein.

  As described herein, the split ratio X. A DDS operating at 5 (where X is an integer greater than or equal to 2) is expected to have a spurious output at an output frequency of 0.5 times (and 1.5 times) (see, eg, FIG. 21) ). By changing (or selecting) the phase offset value of the DDS, the intensity of one (or both) of these intermodulation components is reduced.

  Such a method is further applied, for example, to simplify the filtering task. For example, the filter reduces the spurious strength due to one clock frequency, but does not have a sufficient effect (to meet certain design specifications) on the spurious strength due to other clock frequencies. In at least the second case, by reducing the spurious intensity as described above, it is possible to meet the specification by using the same filter in that case, which adds another filter to the system. Avoid the need. Also, the method described here is described in X. It is also used in DDS that operates at a split ratio other than 5.

  The phase offset value is the division ratio X. When changed (or selected) for a DDS operating at 5 (where X is an integer greater than or equal to 2), an appropriate phase offset value (ie, a desired (or acceptable) reduction in spurious intensity), And / or values that result in a desired (or acceptable) increase in desired signal strength) can be gradually changed. For example, such values change based on effects such as temperature, capacitance, frequency, device degradation, and the like. Therefore, it is desirable to monitor the intensity of one or more spurious components of the output signal of the DDS and to change (or select) the DDS phase offset value based on the monitoring result (see, for example, FIG. 27). ). Such a method is also described in X. It is also used in DDS that operates at a split ratio other than 5. In addition, such a method is used to reduce (or without) the spurious strength and increase the desired signal strength.

  Change (or select) the phase offset value to produce the desired output for different DDS of the same model number, different DDS from the same lot, etc. for at least the same frequency, same split ratio, and / or operation in the same application It is possible to obtain information from one or more DDSs used to do so. For example, information about the optimal (or desirable) phase offset value depends on one or more specific propagation paths (inside and / or outside the DDS) and the relationship between the value and the propagation path It can be applied to the use of other DDS. For example, information about measurements at two or more different clocks (and / or output frequencies) can be used to calculate a phase offset value that has advantages at other frequencies (eg, FIG. 28). Specific methods known in the art, such as state analysis, interpolation, etc., are applied in the method according to embodiments of the present invention.

  As described herein, embodiments of the present invention are used for applications where one or more extremely clean, fast tuning frequency sources are desired. Examples include (but are not limited to) local oscillators in frequency conversion, decoding modulation, and transmission and test and measurement applications. In general, the present invention is also used for previously implemented phase locked loop (PLL) applications. For FIGS. 9-16, specific applications are described below.

FIG. 9 is a block diagram of a fast tuning, high spectral purity tuner / receiver 900 according to an embodiment. More particularly, FIG. 9 shows an embodiment of a tuner / receiver designed for fast tuning speed and high spectral purity (dynamic range (SFDR) free of phase noise and spurious). Applications for such embodiments include collection and analysis of signal intelligence (SIGINT) and electronic intelligence (ELINT) signals. In at least one embodiment, the receiver / tuner 900 includes a radio frequency (RF) antenna 901 coupled to a receive band filter 903, and the output of the receive band filter 903 passes through a low noise amplifier 905 to the first frequency converter 907. Sent to generate a _first intermediate frequency (IF ₁ ). The output of the frequency converter 907 is coupled through a bandpass filter 909 to a second frequency converter 911 that generates a _second IF (IF ₂ ). The output of the second frequency converter 911 is sent through a bandpass filter 913 and an amplifier (or signal processor) 915 to a third frequency converter 917 that recovers the detected digital signal. The output of the frequency converter 917 passes through a first low-pass filter 919, an amplifier / signal processor 921, and a second low-pass filter 923 to reconstruct an analog signal corresponding to the detected digital signal. / A coupled to 925. In such an embodiment, the tuning speed and spectral purity of the receiver is determined by its synthesizer (each LO1, LO2, and LO3 input to the specific example frequency converters 907, 909 and 917 shown in FIG. 9). Determined by. The phase noise, SFDR, and tuning speed of embodiments of the present invention are well suited for such applications. More particularly, any one (or all) of LO1, LO2, and LO3 may be a signal generator (or including one or more embodiments of signal generator 10) described herein (or It is implemented using a synthesizer embodiment. Alternatively, one or both of LO2 and LO3 is implemented using other problem solving means (eg, a signal generator based on PLL or based on SRD).

  FIG. 10 is a block diagram of a DDS chip / chipset according to an embodiment (eg, “DDS on chip”). A new hybrid signal foundry process is used to provide this architecture to the chip (or chipset) problem solver with a limited number of external components. The bandwidth of the chip (or chipset) provides a simplification of a DDS chip with a greatly improved wideband SFDR (eg, 85-90 dBc). The bandwidth of the architecture according to embodiments of the present invention continues to increase the speed of digital and D / A converter architectures.

  In FIG. 10, a modified sine look-up table and phase accumulator ROM contains the phase accumulator and look-up values for the optimally tuned spot for DDS # 2 described herein. For a specific application, these optimal spots are an integer division ratio and an integer ± 0.5 division ratio. Using only those values corresponding to these “optimum spots” reduces the size of the phase accumulator ROM and sine look-up table (ROM). As shown in FIG. 10, in some embodiments, filter components and frequency converter components are provided external to the DDS integrated circuit.

  FIG. 11 is a functional information related diagram for the test and measurement signal generator / spectrum analyzer front end according to the embodiment. More specifically, embodiments of the present invention have the necessary properties for use in test and measurement equipment, including (but not limited to) excellent phase noise and SFDR due to modulation capabilities. The test and measurement signal generator front end includes, for example, a reference signal generator 1105 and a broadband signal generator 12 in communication with the reference signal generator 1105. The broadband signal generator 12 is implemented to include one or more embodiments of the signal generator 10 described herein. The architecture is also beneficial for the RF front end of the device (eg, a spectrum analyzer) and improves the overall performance of the device.

  FIG. 12 is a block diagram of a secure transceiver 1200 having a modulation scheme provided by an embodiment. The modulation function of embodiments of the present invention is useful for use in a transmitter / receiver (transceiver). For example, the low phase noise and spectral purity provided by embodiments of the present invention allow for higher order complex modulation types (and frequency hopping) implementations, and higher order complex modulation types and frequencies. Hopping is a prerequisite for some form of secure transmission. The transmitter is used for standard communication applications or for specific applications (eg radar).

  In at least one embodiment, the transmitter portion of transceiver 1200 includes an encoder / decoder (CODEC) for encoding secure data, and a signal generator 14a, of signal generator 10 described herein. One or more embodiments are included for modulating the encoded data for RF transmission. Such an embodiment requires a filter change to accommodate a broadband modulated signal. Further, in such an embodiment, the receiver portion of transceiver 1200 substantially includes the components described in FIG. 9 for a local oscillator source (one or more of the signal generators 10 described herein). Including the use of signal generators 14b-14d, each of which includes multiple embodiments. However, in these embodiments, the bandpass filter 913 (see FIG. 9) is implemented using a surface acoustic wave (SAW) element. Other filters (eg, filters 903, 909, 919, 923) are implemented using dielectric elements, ceramic elements, or a mixture thereof. Further, in some embodiments, oscillator 14c (and / or oscillator 14d) is implemented using other problem solving means (eg, a PLL (or SRD) based signal generator).

  FIG. 13 is a block diagram of a satellite communication system according to an embodiment. In general, satellite communications require at least three basic components (two terrestrial links and one satellite link) that are used as transponders. Each of these components includes a transmitter / receiver, or a frequency converter (eg, a mixer) used with an embodiment of the present invention (eg, utilized as a local oscillator signal generator).

  In addition, other applications that benefit from the phase noise characteristics of embodiments of the present invention are possible. FIG. 14 is a series of distribution diagrams illustrating the effect of the improved phase noise of one embodiment. Low quality phase noise results in increased BER (bit error rate) that results in data loss, incorrect demodulation of the data (or inability to modulate at the receiver). In this embodiment, for 16-QAM, it is noted that the constellation point is inside the decision region, whereas the 64-QAM embodiment has a decision error (of the region inside each grid). , Indicates that it is caused only by small noise deviations that cause errors in the data. The exceptional phase noise characteristics of embodiments of the present invention allow very high order signals to be demodulated with a significant reduction in bit errors.

  Commercially, embodiments of the present invention are applied, for example, to increase the data transmitted over a given bandwidth, thus making mobile phone / database stations more capable than adding new cell sites. Allows for expansion. In a transceiver, the embodiments are applied to be implemented by current PLL systems at a level where complex high order modulation / demodulation cannot be achieved. In addition, the increased tuning speed also allows the hopping frequency to be intercepted and tracked when used at the receiver. On the transmit side, a transceiver including an embodiment of the present invention is implemented so that it can tune faster than today's receivers (PLLs) can detect. For defense related applications, the embodiments are used in a transmit / receive (transceiver) system that enables secure transmission.

  FIG. 15 is a full functional block diagram of a single frequency radar system according to an embodiment. As shown in FIG. 15, such a radar system uses a power divider (eg, PD1-PD6), amplifier, delay line (eg, DL1 and DL1) to generate interferometric polarization components and circular polarization components. DL2) and an I / Q demodulator (IQD1-IQD2). For each radar application, the spectral purity and reproducible behavior of the signal generator described herein allows radar identification characteristics to be defined with higher resolution and accuracy. More specifically, embodiments including embodiments of the signal generator 10 described herein may be configured to implement OSC1 (and / or) shown in FIG. 15 to implement a single frequency (or multiple frequency) radar system. , OSC2) used to provide the device. In multi-frequency applications, the delay line elements DL1, DL2 are implemented such that they can be varied and selected based on the current frequency. Also, embodiments of the present invention enable smaller, lighter packaged products for most applications and / or show that reproducible behavior is not available from the PLL circuit. Embodiments become smaller as the speed of digital technology (and D / A converters) increases, reducing the need for peripheral hardware.

  In FIG. 16, an embodiment of the present invention is implemented in any number of ways, including a variable frequency source instead of DDS # 1, or the modified architecture described for the DDS chip / chipset embodiment It is carried out by carrying out. The characteristics of the embodiment shown in FIG. 16 will now be described.

In FIG. 16, DDS # 1 functions as a variable clock source for DDS # 2. According to the frequency requirement specification, in this embodiment, this clock source is generated by mixing DDS # 1 with 300 MHz and filtering to achieve 300 MHz ± DDS # 1. It is noted that the frequencies and components are used only for illustration and clarity herein, and that other variations are possible. Narrowband spurious (ie, unfilterable) performance is established by the spurious performance of DDS # 1 and the split ratio (tuning word) of DDS # 2. The reduction of the intermodulation component of the output produced by DDS # 1 is formulated as follows.
Output spurious = DDS # 1 spurious-20 logN (Formula 1)
Where N = DDS # 2 division ratio or 2 ^X / FTW (where X is the number of bits of the phase accumulator)

For example, DDS # 1 has a worst spurious of −75 dBc, and the frequency tuning word (FTW) of DDS # 2 is ¼ full resolution (or division ratio 4).
Output spurious = −75−20 log 4 = −75−12 = −87 dBc

Determining the spurious performance required for a given application is determining the SFDR for DDS # 1. In general, D / A converters contribute the most to spurious performance and are characterized as follows.
dBc = 20 log1 / 2 ^N (Formula 2)
Here, N = number of bits of D / A converter (or dBc≈−6 * N)

  Therefore, for a 12-bit D / A converter, ≈−6 * 12≈−72 dBc, and for a 14-bit D / A converter, ≈−6 * 14≈−84 dBc.

  Increasing the D / A converter resolution (bits) (and / or using spurious reduction techniques (eg, dithering)) improves the spurious performance of the D / A converter. Since dithering broadens noise / spurious in the frequency domain, dithering also reduces the overall SFDR (noise floor), but dithering is used to reduce the amplitude of individual spurious responses.

  The converted (mixed) DDS # 1 frequency output is then provided as the system clock for DDS # 2. DDS # 2 is adjusted to an optimum spot (without spurious). The output is then changed by changing DDS # 1 (SYSCLK for DDS # 2).

  There are two main types of spurious response at the DDS output (D / A converter error (eg, non-linearity and quantization error) and phase-censored intermodulation components) to determine the optimal spot for DDS # 2. Remember to do it. The worst phase truncation intermodulation component is as follows. For example, if the number of phase bits (after truncation) is 19, the phase truncation error is approximated by 19 bits * 6.02≈114 dBc. This worst-case condition (-114 dBc) appears only with a single bit pattern for truncation bits. This pattern is 1 for the MSB and all remaining bits are 0. As demonstrated by the worst case of 114 dBc, phase truncation is not a major factor for spurious performance and is not considered.

  The second source of spurious response is D / A converter error, which includes quantization error and D / A converter nonlinearity. These intermodulation components (created with harmonics of the fundamental frequency) introduce errors in the signal bandwidth and are predictable and reproducible.

  FIG. 17 illustrates a broadband signal generation method 1700 according to at least one embodiment. In an embodiment, method 1700 is implemented, for example, as rewritable gate array (FPGA) logic. However, other variations are possible. For example, instead, the method 1700 uses an array of programmed instructions (or software executed by a processor), a microprocessor, a microcontroller, or a personal computer, or using separate logic components. To be implemented.

  As shown in FIG. 17, the wideband signal generation method begins at block 1705. Control then proceeds to task 1710, where task 1710 receives a request for an output signal (eg, from a user or a hardware (or software) component of an application). The request indicates at least a specific signal frequency. Control then proceeds to task 1715, where task 1715 determines the division ratio for the divider based on the requested output signal frequency (and clock source frequency). Control then proceeds to tasks 1720, 1725, 1730, where tasks 1720, 1725, 1730 generate at least one control signal (eg, one or more control words) corresponding to the split ratio determined in task 1715. The band pass filter is selected from a set of filters based on the division ratio. In an embodiment, the control signal includes specifications for frequency, phase offset, and / or amplitude scaling.

  Control then proceeds to task 1725, where task 1725 provides a control signal corresponding to the divider. In the example, this task was performed by loading (eg, latching) the control word into the corresponding register of the divider. In at least one embodiment, the divider is a DDS with a synthesizer and signal generator as described herein. Task 1725 also selects the appropriate filter (eg, within filter 167) and / or the requested frequency (and / or the requested frequency (eg, frequency ratio, clock source, etc.). Selection based on the frequency, the associated value) selected by the frequency of the signal being filtered (or passed through).

  Control then proceeds to task 1735, which instructs at least one divider to begin operating according to the control signal. Control then proceeds to task 1740, which changes the frequency of the synthesizer according to the new control signal. Control then proceeds to task 1745 where the method ends. The method 1700 is repeated as often as necessary to support applications for the broadband synthesizer as needed.

  The graphs shown in FIGS. 18-23 show the main frequency of the simulated output of an embodiment of the signal generator 20 and mainly D (including quantization error and / or D / A converter nonlinearity). / A spurious component due to converter error is included. The graph also illustrates aliasing and shows the optimal frequency for adjusting the DDS. For example, the best tuning spot that invalidates the D / A converter spurious response corresponds to a DDS tuning word that produces an integer split value.

  FIG. 18 shows a theoretical graph of the output signal generated by at least one embodiment having a split ratio of 2.990, which generates a spurious term. FIG. 19 shows a theoretical graph of the output signal generated by at least one embodiment having a split ratio of 2.999, which also generates spurious terms but is closer to the fundamental frequency (ie, Spurious terms concentrate on the fundamental frequency). FIG. 20 shows a theoretical graph of the output signal generated according to at least one embodiment having a split ratio of 3.000. FIG. 21 shows a theoretical graph of the output signal produced by at least one embodiment having a split ratio of 2.5000. FIG. 22 shows a theoretical graph of the output signal generated by at least one embodiment having a split ratio of 3.1000. Finally, FIG. 23 shows a theoretical graph of the output signal produced by at least one embodiment having a split ratio of 6.1991.

  FIG. 20 shows a uniform integer division value (for example, division ratio = 3.000). Such ratio is the optimal spot for the second (ie, final) DDS since all image terms are hidden below the fundamental frequency. This condition allows tuning (and / or modulation) of the upstream DDS (eg, DDS # 1) without affecting the SFDR of the later DDS (eg, DDS # 2) in the current state, This state enables clean, spurious-free output. The spurious component concealed by the fundamental frequency is an arbitrary but deterministic phase for this (separate) synchronization system and does not result in a significant amplitude change inside the Nyquist band.

  Referring to FIG. 18, it can be seen that as the division ratio approaches the integer value, spurious components concentrate on the fundamental frequency. The graph of FIG. 20 shows the performance without spurious because the spurious term is placed directly under the carrier. The second best case is when the tuning word produces an integer ± 0.5, as shown in FIG. This case creates spurious terms at 0.5 times (and 1.5 times) the output frequency due to obvious D / A converter errors. For example, the third spurious term shown in the graph is an image of the second harmonic of the fundamental frequency. Since the spurious position in this case is predictable, such a ratio is used depending on the specification, bandwidth, and filtering implemented.

  The third selection item is an extension in the second case. This is done by programming a tuning word that produces an integer ± 0.1, ± 0.2, ± 0.3, or ± 0.4. Table 3 below helps to predict the spurious position in this case (as shown in the example of FIG. 22).

  Other cases implemented using these embodiments require additional filtering and frequency planning, as shown in FIG. This case characterizes the particular DDS used (and the D / A converter) and selects the band observed to be free of spurs based on the D / A converter state analysis shown in FIG. Is achieved. This case is highly dependent on performance criteria, D / A converter characteristics, and filtering. This case produced a narrower band compared to the above architecture, but also provides further improvements over the current single DDS architecture.

By using the graphs shown in FIGS. 18-23 and Table 3, the optimal spot for DDS # 2 can be summarized (in order) as follows.
DDS # 2 set to an integer value (CLK / Freq tuning word = integer)
DDS # 2 set to an integer value ± 0.5 (2.5, 3.5, 4.5, ... N.5)
DDS # 2 set to integer values ± 0.1, ± 0.2, ± 0.3, or ± 0.4
Random (observation) optimally adjusted spot based on DDS and D / A converter state analysis

  While the preferred embodiment of the invention has been illustrated and described, it will be apparent to those skilled in the art that various modifications and changes can be made without departing from the scope of the invention as defined by the claims. Let's go.

1 is a block diagram of a frequency synthesizer 100 according to at least one embodiment. FIG. 3 is a detailed block diagram describing at least one example clock generator. FIG. 3 is a detailed block diagram describing a clock divider of at least one embodiment. FIG. 6 is a detailed block diagram of another embodiment of a clock divider and frequency multiplier. FIG. 3 is a detailed block diagram of an embodiment of a first synthesizer stage. FIG. 6 is a detailed block diagram of an embodiment of a second synthesizer stage. FIG. 3 is an example of a synthesizer including a clock generator coupled to two or more dividers. FIG. It is a block diagram of the other Example of a synthesizer. It is a block diagram of the other Example of a synthesizer. FIG. 3 is a block diagram of an example of a programmable divider chip. FIG. 5 is another block diagram of an example of a programmable divider chip. 1 is a block diagram of a tuner / receiver that is fast tuned according to an embodiment and has high spectral purity. FIG. 3 is a block diagram of a DDS chip / chipset according to an embodiment. FIG. 6 is a functional information related diagram for a test and measurement signal generator / spectrum analyzer front end according to an embodiment. FIG. 3 is a block diagram of a secure transceiver having a modulation scheme provided by an embodiment. 1 is a block diagram of a satellite communication system according to an embodiment. FIG. 6 is a series of distribution diagrams illustrating the effect of improved phase noise in an embodiment. 1 is an overall block diagram of a radar system according to an embodiment. FIG. 6 is a block diagram of at least one embodiment of a divider having a variable frequency input source. 2 is a flow diagram of a method according to at least one embodiment. FIG. 10 is a theoretical graph of an output signal generated by at least one embodiment having a split ratio of 2.990. FIG. 6 is a theoretical graph of an output signal generated by at least one embodiment having a split ratio of 2.999. FIG. 6 is a theoretical graph of an output signal generated by at least one embodiment having a split ratio of 3.000. FIG. 6 is a theoretical graph of an output signal generated by at least one embodiment having a split ratio of 2.5000. Fig. 6 is a theoretical graph of an output signal generated by at least one embodiment having a split ratio of 3.1000. FIG. 10 is a theoretical graph of an output signal generated by at least one embodiment having a split ratio of 6.1991. FIG. 1 is a block diagram of a signal generator 10 according to an embodiment of the present invention. It is a block diagram of a DDS having a division ratio of 2. It is a block diagram of DDS having a division ratio of 2.5. 3 is a flowchart of a method according to an embodiment of the present invention. 3 is a flowchart of a method according to an embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Signal generator 12 Broadband signal generator 20 Signal generator 100,200,700,720 Synthesizer 101,103,201,701 Clock generator 102,104,105,202,203,204,703,710,711 Clock division 110 Clock distribution unit 120, 130, 140 Frequency converter stage 121 Frequency doubler 125, 146, 169 Drive circuit 123, 133, 134, 142, 913 Band pass filter 131, 141, 155, 165, 907, 911 917 Frequency converter 132, 135, 144, 145, 205, 712 Switch 142, 157, 167, 909 Band pass filter 151, 161 Direct digital synthesizer (DDS)
153, 163 Variable band pass filter 722 Divider stage 801 Division ratio-address mapping unit 802 Look-up table 803 D / A converter 900 Tuner / receiver 901 Antenna 903 Receive band filter 905, 915, 921 Amplifier 913 Band pass filter 919 , 923 Low-pass filter 925 D / A converter 1105 Reference signal generator 1200 Transceiver

Claims (28)

A clock generator including a first direct digital synthesizer (DDS) configured to generate a composite signal based on the clock source signal;
A clock divider in communication with the clock generator and including a second DDS and configured to generate a split signal based on (1) the combined signal and (2) a control signal indicating a frequency ratio; A plurality of selectable filters configured to communicate with the clock divider and to generate a filtered signal based on the divided signal;
The selection of the plurality of selectable filters is based on the frequency ratio.   The signal generator of claim 1, wherein the clock generator includes a frequency converter configured to communicate with the clock divider and generate a converted signal based on the combined signal. vessel.   The signal generator according to claim 2, wherein the frequency converter includes a mixer.   The frequency converter includes a mixer having the local oscillator input, the mixer configured to receive a signal at the local oscillator input based on the clock source signal. Signal generator.   The frequency converter further comprising a frequency converter configured to communicate with at least one of the plurality of selectable filters and to generate a converted signal based on the filtered signal. A signal generator according to claim 1.   The signal generator according to claim 1, wherein the division ratio is at least 2 and less than 3.   A third DDS configured to generate the second divided signal based on (1) the combined signal and (2) a second control signal indicating a second frequency ratio; The signal generator according to claim 1, comprising:   The signal generator of claim 1, wherein the selection of the plurality of selectable filters is based on a user selected frequency.   The signal generator of claim 1, wherein the plurality of selectable filters comprises a 1 / N · octave band filter bank, where N is an integer greater than zero.   The signal generator of claim 1, wherein at least two of the plurality of selectable filters have different bandwidths.   Communicating with the clock divider and including a third DDS to generate a divided signal based on (1) the filtered signal and (2) a second control signal indicative of a second frequency ratio The signal generator according to claim 1, further comprising a second clock divider configured as follows. An adjustable clock generator configured to generate a clock signal;
A clock that communicates with the adjustable clock generator, includes a direct digital synthesizer, and is configured to generate a split signal based on (1) the clock signal and (2) a control signal indicative of a frequency ratio. A divider, and a plurality of selectable filters configured to communicate with the clock divider and to generate a filtered signal based on the divided signal;
The signal generator, wherein the selection of the plurality of selectable filters is based on the frequency ratio. And further comprising at least one second clock divider each communicating with the adjustable clock generator and configured to generate a divided signal based on the clock signal;
At least one of the at least one second clock divider includes a direct digital synthesizer and is configured to generate the divided signal based on a second control signal indicative of a second frequency ratio. 13. A signal generator according to claim 12, characterized in that   The signal generator of claim 13, wherein the plurality of selectable filters are in communication with the at least one second clock divider.   The switch of claim 13, further comprising a switch configured to communicate with the clock divider and the at least one second clock divider and to select one of each of the divided signals. Signal generator.   14. The signal generator of claim 13, wherein at least one of the clock divider and the at least one second clock divider includes a frequency converter.   17. Signal generator according to claim 16, characterized in that at least one frequency converter is a mixer.   The signal generator of claim 13, wherein the adjustable clock generator comprises a direct digital synthesizer.   14. The at least one direct digital synthesizer is preconfigured to output each of the divided signals at a predetermined frequency in response to receiving the clock source signal. A signal generator according to claim 1. Receiving a request indicating the frequency;
Determining a split ratio based on the indicated frequency and the frequency of the clock source signal;
Generating a control signal corresponding to the division ratio;
Selecting a bandpass filter from a set of filters based on the split ratio;
Generating an output signal having a principal component at the indicated frequency based on the control signal; and filtering the output signal using the selected bandpass filter to pass the principal component. A method of signal generation comprising:   The signal of claim 20, wherein generating an output signal includes providing a control word and a signal to a direct digital synthesizer (DDS) based on the clock source signal. Method of occurrence.   21. A method of signal generation according to claim 20, wherein generating an output signal comprises dividing the signal by a ratio of at least 2 but less than 3 based on the clock source signal. .   21. The method of signal generation according to claim 20, wherein generating an output signal includes dividing the signal by 2.5 based on the clock source signal. Using a first direct digital synthesizer (DDS) to generate a clock signal, and generating a signal having a frequency substantially equal to one half of the clock signal based on the clock signal; Using a second DDS to generate a signal.   The method of signal generation according to claim 24, further comprising providing a phase offset value to the second DDS. Providing a first signal to a clock input of a direct digital synthesizer (DDS) and, based on the first signal, an output signal having a frequency substantially equal to one half of the clock signal A method of signal generation comprising using the DDS to generate.   27. The method of signal generation according to claim 26, further comprising providing a phase offset value to the DDS. Using a direct digital synthesizer (DDS) to generate an output signal having a desired frequency component and a spurious frequency component;
A method of signal generation, comprising: monitoring an intensity of the spurious frequency component; and changing a phase offset value of the DDS based on a result of the monitoring.

Images