CN112260979B - Multichannel parallel segmented modulation method - Google Patents
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Abstract
The invention discloses a multichannel parallel segmented modulation method, which is characterized in that under a zero intermediate frequency architecture, digital baseband complex signals meeting the frequency range requirement are synthesized through an FPGA, then digital complex frequency mixing is carried out on the digital baseband complex signals and N paths of digital complex local oscillator signals at the same time, then N paths of analog baseband complex signals are obtained through filtering processing of a low-pass filter and sampling of a DAC, finally, the N paths of analog baseband complex signals are respectively subjected to quadrature modulation with corresponding local oscillator signals through a quadrature modulation chip, and the signals are synthesized and output through a combiner, so that broadband modulation signals for improving modulation broadband are obtained, and the expansion of modulation bandwidth is realized.
Description
Technical Field
The invention belongs to the technical field of wireless communication, and particularly relates to a multichannel parallel segmented modulation method.
Background
With the continuous development of electronic information technology, the requirements of various electronic systems, such as digital oscilloscopes, radars, signal sources, frequency spectrometers and the like, on signal conditioning modules gradually develop towards the directions of broadband, generalization and miniaturization. The radio frequency transmitting channel is used as a core module in the system, and is used for converting an analog baseband signal generated by the digital-to-analog converter into a radio frequency signal through up-conversion, and finally transmitting the radio frequency signal to a space through an antenna after signal conditioning. At present, most of transmitting channels adopt a superheterodyne or zero intermediate frequency architecture, and the main difference lies in that different architectures have different requirements on indexes such as baseband signal instantaneous bandwidth and frequency.
A block diagram of a typical system structure of a superheterodyne architecture is shown in fig. 1, and the structure mainly includes a radio frequency band pass filter, a power amplifier, a local oscillation module, a mixer, and an amplitude conditioning circuit. As shown in fig. 1, firstly, after the analog signal generated by the digital-to-analog converter passes through the baseband amplitude conditioning circuit, the out-of-band interference is filtered by the band-pass filter, so that the output signal meets the power requirement of the input port of the post-stage frequency conversion module, and the input signal of the frequency conversion module does not carry stray signals. Then, the signal is mixed with the local oscillator signal to shift the frequency spectrum, and the output signal of the frequency mixer is a nonlinear device and has various harmonics besides the required useful signal, so that the later stage of the frequency mixer is a specific filter bank, on one hand, the spurious of various harmonics is suppressed, and on the other hand, the channel division is performed. And finally, outputting the filtered signal to a transmitting antenna through a power amplifier. The superheterodyne architecture is the most common scheme for building a transmitting system, although the dynamic range and the adjacent channel selectivity of the superheterodyne architecture are far superior to those of other architectures for receiving and transmitting systems, and the local oscillator leakage and the direct current bias have small influence on the system, the defects are obvious, firstly, the combined frequency interference caused by the nonlinear characteristic of a frequency mixer is more, particularly, the image interference is generated, and along with the development of the wireless communication technology, the system is not only specific to a certain frequency point but also is a broadband signal, so that various harmonic spurs are difficult to analyze and filter. Secondly, the volume and the whole power consumption of the superheterodyne transmitter are large, and the complexity is too high: the super heterodyne architecture transceiver can achieve high performance because it can perform multiple frequency conversion processes, i.e., a reasonable system of intermediate or baseband signal frequencies. The multiple frequency conversion processing means that the complexity of the whole system circuit is too high, a plurality of filters are needed, and partial filters with high performance and high Q values can only be realized outside the chip. In summary, the super heterodyne transmitter is difficult to have the characteristics of broadband, generalization and miniaturization.
A direct conversion transmitter, also called a zero intermediate frequency transmitter, has a block diagram as shown in fig. 2. The zero intermediate frequency scheme firstly generates two paths of digital signals with the same amplitude and 90-degree phase difference through an FPGA through a DDS synthesis technology, then generates IQ two paths of analog baseband signals through a two-channel digital-to-analog conversion circuit, then mixes the IQ two paths of analog baseband signals with 90-degree phase difference local oscillator signals through two independent signal paths respectively, and finally obtains the required radio frequency signals through summation by a summation amplifier.
Combining the working principle of a direct conversion transmitter, assuming that the I path signal is IIfThe phase difference between the Q path signal and the I path is 90 deg., and the Q path signal is QIf(t) is a sin (ω t), and the local oscillation signals required by the two IQ independent paths are respectively ILO(t)＝B cos(ωct) and QLO(t)＝B sin(ωct) when the output signal of the transmitter is directly converted.
S(t)＝IIf(t)ILO(t)-QIf(t)QLO(t)
＝Acos(ωt)Bcos(ωct)-Asin(ωt)Bsin(ωct)
＝AB cos((ω+ωc)t)
It can be seen from the above formula that the output signal frequency is the sum of the IQ signal frequency and the local oscillator signal frequency, and the image signal generated by the mixing can be completely eliminated theoretically due to the phase characteristics satisfied by the signals in the zero intermediate frequency architecture. In addition, two groups of IQ signals with different phase relationships are synthesized by DDS and other technologies, so that the bandwidth of a digital-to-analog converter of each path of signal can be reduced to half of the instantaneous bandwidth of the system.
At present, aiming at different frequency ranges and modulation bandwidth indexes, a plurality of orthogonal modulation chips exist in the market, however, in practical application, the modulation chips often cannot meet the requirements of the frequency ranges and the modulation bandwidths.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a multichannel parallel segmented modulation method, which is based on a zero intermediate frequency structure and utilizes a plurality of modulation chips to perform parallel segmented modulation in a multi-level frequency conversion expansion mode so as to realize modulation bandwidth expansion.
In order to achieve the above object, the present invention provides a multi-channel parallel segmented modulation method, which is characterized by comprising the following steps:
(1) synthesizing the frequency range of [ -2 pi BW/2f through FPGAs,2πBW/2fs]Wherein f is the digital baseband complex signal x (n), andsBW is more than or equal to BW, BW is modulation bandwidth;
(2) generating N paths of digital complex local oscillator signals by a digital oscillator, and simultaneously carrying out digital complex frequency mixing on x (N) and the N paths of digital complex local oscillator signals; wherein, the k-th path digital complex local oscillator signal is marked as Ldk＝exp(jωdkn) corresponding to frequency ωdkExpressed as:
wherein k is 0,1,.., N-1;
(3) filtering each path of signal after the digital complex mixing through a low-pass filter, and outputting N paths of baseband complex signals;
(4) respectively sampling each sub-band complex signal by using DAC (digital-to-analog converter), and outputting N paths of sampling signals with sampling rate fsThe frequency ranges are [ -BW/2N, BW/2N]Analog baseband complex signal x ofk(t)；
(5) And generating N local oscillator signals by using the PLL, wherein the frequency of each local oscillator signal is represented as:
fak＝fRF+(2k+1-N)BW/2N
wherein k is 0,1,.., N-1;
respectively carrying out quadrature modulation on the N paths of analog baseband complex signals and corresponding local oscillation signals through a quadrature modulation chip to finish the frequency spectrum shifting of the analog baseband complex signals;
(6) signal synthesis
Correcting N paths by using combinerAdding the signals after the cross modulation to finally generate the signal with the center frequency fRFA wideband modulated signal x (t) with an instantaneous bandwidth BW.
The invention aims to realize the following steps:
the invention discloses a multichannel parallel segmented modulation method, which is characterized in that under a zero intermediate frequency architecture, digital baseband complex signals meeting the frequency range requirement are synthesized through an FPGA, then digital complex frequency mixing is carried out on the digital baseband complex signals and N paths of digital complex local oscillator signals at the same time, then N paths of analog baseband complex signals are obtained through filtering processing of a low-pass filter and sampling of a DAC, finally, the N paths of analog baseband complex signals are respectively subjected to quadrature modulation on corresponding local oscillator signals through a quadrature modulation chip, and the signals are synthesized and output through a combiner, so that broadband modulation signals for improving modulation broadband are obtained, and the expansion of modulation bandwidth is realized.
Meanwhile, the multichannel parallel segmented modulation method also has the following beneficial effects:
(1) the N-segment parallel modulation architecture provided by the invention can reduce the instantaneous bandwidth index of the orthogonal modulation chip in the traditional architecture to BW/N, and can realize the orthogonal modulation function of high bandwidth by applying the orthogonal modulation chips with multi-path lower modulation bandwidth;
(2) aiming at the problem that the quadrature modulation chips on the market cannot meet the modulation bandwidth index, the bandwidth can be expanded in a mode that a plurality of modulation chips work in parallel, namely, firstly, a plurality of groups of quadrature signals with different frequency ranges are synthesized on a digital domain in a DDS mode and the like, the plurality of modulation chips modulate a plurality of groups of baseband quadrature signals in a segmented mode after passing through a digital-to-analog conversion circuit, and finally, radio frequency signals with high instantaneous bandwidth are obtained through a combiner, so that the problem that the modulation bandwidth cannot meet the requirement is solved.
Drawings
Fig. 1 is a schematic diagram of the structure of a superheterodyne transmitter;
fig. 2 is a schematic diagram of the architecture of a zero if transmitter;
FIG. 3 is a functional block diagram of a multi-channel parallel segment modulation of the present invention;
FIG. 4 is a block diagram of a simulation architecture for a dual channel parallel modulation circuit;
FIG. 5 is a graph of a digital complex signal spectrum;
FIG. 6 is a graph of channel 0 digital complex mixing result output;
FIG. 7 is a graph of channel 1 digital complex mixing result output;
FIG. 8 is a diagram of channel 0 modulation output spectrum;
FIG. 9 is a diagram of channel 1 modulation output spectrum;
fig. 10 is the system total modulation output.
Detailed Description
The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.
Examples
Fig. 3 is a schematic block diagram of a multi-channel parallel segment modulation of the present invention.
In the present embodiment, as shown in FIG. 3, in order to output a center frequency fRFThe radio frequency signal x (t) with instantaneous bandwidth BW, if based on the conventional zero if structure, the output can be decomposed into frequency fRFHas a carrier signal and a frequency range of [ -BW/2, BW/2]The baseband modulation signal, however, because the modulation chips on the market are limited by bandwidth indexes at present, a method of multi-channel parallel segmented modulation is proposed, that is, a modulation signal meeting the index requirement is output based on the existing low-bandwidth modulation chips on the market by dividing the bandwidth BW and reasonably selecting the frequencies of a plurality of groups of carrier signals. Therefore, the quadrature modulation circuit based on the zero-if architecture needs to satisfy two conditions: 1. the quadrature modulation chip needs to meet the requirement of instantaneous bandwidth index; the maximum sampling rate of the DAC is equal to or greater than twice the instantaneous bandwidth index of the output signal (two channel synthesis I, Q, each channel maximum sampling rate should be equal to or greater than the instantaneous bandwidth).
The following N-segment parallel modulation architecture is proposed to reduce the instantaneous bandwidth index of the quadrature modulation chip in the conventional architecture to BW/N, and the quadrature modulation function with high bandwidth can be realized by the multiple quadrature modulation chips with lower modulation bandwidth, which specifically includes the following steps:
s1, synthesizing BW/2f with frequency range of [ -2 pi ] through FPGAs,2πBW/2fs]Of the digital baseband complex signal x (n), wherein fsBW is more than or equal to BW, and BW is modulation bandwidth.
S2, generating N paths of digital complex local oscillation signals through a digital oscillator, and performing digital complex mixing on x (N) and the N paths of digital complex local oscillation signals at the same time; wherein, the k-th path digital complex local oscillator signal is marked as Ldk＝exp(jωdkn) corresponding to frequency ωdkExpressed as:
wherein k is 0,1,.., N-1;
at this time, the bandwidths of the N complex mixed frequency output signals are all 2 pi BW/fsI.e. each signal contains all the information of the digital baseband complex signal x (n).
S3, filtering each path of signal after digital complex mixing through a low-pass filter, and outputting N paths of baseband complex signals;
in this embodiment, the cut-off frequency of the low-pass filter is 2 π BW/2NfsAs shown in FIG. 4, the frequency ranges of the baseband complex signals outputted by the low-pass filtering are [ -2 π BW/2Nfs,2πBW/2Nfs]The bandwidth is 2 pi BW/Nfs(ii) a The kth path low-pass filters the output frequency spectrum information and the digital baseband complex signal x (N) frequency band [2 pi (2k-N) BW/2Nfs,2π(2k+2-N)BW/2Nfs]The medium frequency spectrum information is consistent, so that N equal division of the instantaneous bandwidth of the digital signal is realized while useful information is not lost, and the instantaneous bandwidth of each baseband signal is reduced by N times, so that the quadrature modulation chip can be realized only by meeting the requirement of lower modulation bandwidth.
S4, respectively sampling each baseband complex signal by using DAC, and outputting N paths of sampling signals with sampling rate fsThe frequency ranges are [ -BW/2N, BW/2N]Analog baseband complex signal ofxk(t) thereby reducing the sampling rate requirements of the DAC chip.
In this embodiment, when N is 4, the frequency of each digital replica signal is ωdk＝2π(2k-3)BW/8fsK is 0,1,2,3, the frequency range of the 4-path digital baseband signals after complex mixing and low-pass filtering is [ -2 pi BW/8fs,2πBW/8fs]The bandwidth is 2 pi BW/4fsCorresponding to the frequency ranges of x (n) being [ -2 π BW/2fs,-2πBW/4fs]，[-2πBW/4fs,0]，[0，2πBW/4fs]And [2 π BW/4fs,2πBW/2fs]The total frequency range is [ -2 π BW/2fs,2πBW/2fs]。
From the above analysis, it can be seen that after the digital complex mixing and the segmentation by the filter, the bandwidth of the signal has been reduced to one N times of the original bandwidth, so as to greatly reduce the requirements on the DAC sampling rate index and the orthogonal modulation chip modulation bandwidth index.
S5, obtaining the final center frequency fRFIn the wideband quadrature modulation output of the instantaneous bandwidth BW, the frequency of each rf local oscillator PLL needs to be reasonably set, and in combination with the final output signal and the relevant frequency index of the N analog baseband complex signals, the frequency of each rf local oscillator signal can be expressed as:
fak＝fRF+(2k+1-N)BW/2N
respectively carrying out quadrature modulation on the N paths of analog baseband complex signals and corresponding local oscillation signals through a quadrature modulation chip to finish the frequency spectrum shifting of the analog baseband complex signals;
in this embodiment, after each analog baseband complex signal is quadrature modulated, the frequency range of the output rf signal is fRF+(2k-4)BW/8,fRF+(2k+2-4)BW/4]. When k is 0, the frequency range is fRF-BW/2,fRF+-2BW/8](ii) a When k is 3, the frequency range is [ fRF+2BW/8,fRF+BW/2]。
S6, signal synthesis
Adding the N paths of orthogonally modulated signals by using a combiner to finally generate a signal with a center frequency fRFInstantaneous bandwidth BWWideband modulation signal x (t).
In this embodiment, the frequency range of the rf signal output from the 4-way quadrature modulation output via the 4-way combiner is fRF+ -BW/2, thereby achieving wideband quadrature modulation of the instantaneous bandwidth BW.
In summary, the proposed method of multi-channel parallel segmented modulation greatly reduces the requirements of modulation bandwidth of quadrature modulation chip and DAC conversion rate.
The method proposed herein is demonstrated below by the Simulink simulation tool in Matlab, using a dual channel as an example.
The dual-channel parallel modulation circuit mainly comprises a digital complex signal generation module, a digital signal complex mixing module, a dual-channel quadrature modulation module and a combiner, and a specific block diagram is shown in fig. 4.
If the circuit is required to output a broadband radio frequency signal with the center frequency of 5GHz and the instantaneous bandwidth of 2GHz, the setting and the working process of relevant parameter indexes are as follows: first, a frequency range of [ -1GHz, 1GHz is generated]The digital baseband complex signal (I, Q signal sampling rates are all fs2.5 GSPS). Then, the frequency of the digital replica oscillation signal of the two sub-channels is 2 pi (2k-1) × 2GHz/4fs(k is 0, 1). The modulation bandwidth of the final output signal is 2GHz, namely the cut-off frequencies of four sub-signals of two channels are all 500MHz, and the sampling rate f of the subsequent DACsThe dual channel 2.5GHz is set.
For the baseband signal in the channel 0, complex mixing with a digital local oscillator frequency of 2 pi-0.5/2.5 (corresponding to the frequency of the analog complex signal of-500 MHz) is realized, and after passing through a low-pass filter with a cut-off frequency of 500MHz, the part of [ -1GHz,0] in the frequency range of the original baseband complex signal [ -1GHz, 1GHz ] is moved to [ -500MHz, 500MHz ]. Similarly, for the channel 1 baseband signal, complex mixing with a digital local oscillator frequency of 2 pi · 0.5/2.5 (corresponding to the analog complex signal frequency of 500MHz) is realized, and after passing through a low-pass filter with a cutoff frequency of 500MHz, the [0,1GHz ] part in the frequency range of the original baseband complex signal [ -1GHz, 1GHz ] is shifted to [ -500MHz, 500MHz ]. Two [ -500MHz, 500MHz ] frequency range digital baseband complex signals output by channel 0 and channel 1 mixing frequency are respectively subjected to digital-to-analog conversion by two-channel DACs.
Since the center frequency of the final output signal is 5GHz, the modulation local oscillation frequencies of the two sub-channels are 5000+ (2k-1)500MHz (k is 0,1), that is, the modulation local oscillation frequency of the channel 0 is 4.5GHz, and the modulation local oscillation of the channel 1 is 5.5 GHz. The frequency ranges of the two channel modulation input baseband complex signals (i.e., DAC outputs) are both [ -500MHz, 500MHz ], so the frequency range of the channel 0 quadrature modulation output is [4GHz, 5GHz ], and the frequency range of the channel 1 quadrature modulation output is [5GHz, 6GHz ]. And finally, the two-channel modulation output generates an orthogonal modulation signal with the center frequency of 5GHz and the bandwidth of 2GHz through a combiner.
An analog complex signal is set to-900 MHz, random noise signals are superposed through an adder, and then a digital baseband complex signal with the frequency of-900 MHz is generated through an ADC (double channel, sampling rate of 2.5GHz), and a frequency spectrum diagram of the digital baseband complex signal is shown in FIG. 5.
As can be seen from FIG. 5, the complex digital signal x [ n ] synthesized by FPGA has a frequency of-0.9 GHz, a power of-30.002 dBm, and a noise power of-20 dBm.
Fig. 6 shows the result of channel 0 being output by a low-pass filter after being mixed with a digital local oscillator frequency 2 pi x-0.5/2.5, the frequency of the digital complex signal is shifted from-900 MHz to-400 MHz, and the effective frequency range is [ -500MHz, 500MHz ].
As can be seen from FIG. 6, after complex mixing, the frequency spectrum of the digital complex signal x [ n ] is shifted from-0.9 GHz to-0.4 GHz, and after filtering by the low-pass filter, the frequency and power values of the main signal are not affected, and the effective frequency range of the channel at this time becomes [ -500MHz, 500MHz ], corresponding to [ -1GHz,0] of the original digital complex signal x [ n ].
Fig. 7 shows the result of channel 1 being output by a low-pass filter after being complex-mixed with a digital local oscillator frequency 2 pi 0.5/2.5, and the effective frequency range is [ -500MHz, 500MHz ].
It can be seen from fig. 7 that the effective frequency range of channel 1 is also [ -500MHz, 500MHz ], which corresponds to [0,1GHz ] of the original digital complex signal x [ n ], and the frequency spectrum of the filter output signal is a noise spectrum because only random noise exists in the frequency range of [0,1GHz ] for the original x [ n ] signal.
Fig. 8 is a diagram of the modulation output result of channel 0, because the frequency range of the channel 0 processing signal corresponds to [ -1GHz,0] of the original digital baseband signal, the digital baseband complex signal of-900 MHz is in the modulation range of channel 0 after digital complex mixing, and the local oscillator signal frequency of the quadrature modulation circuit in channel 0 is 4.5GHz, so the modulation output signal frequency is 4.1 GHz.
It can be seen from fig. 8 that after quadrature modulation, the effective frequency range of the channel is shifted from [ -500MHz, 500MHz ] to [4GHz, 5GHz ], the main signal is up-converted from-0.4 GHz to 4.1GHz, the power value is about 32dBm, and the noise power in the channel is still about-20 dBm.
FIG. 9 is a diagram of the modulation output result of channel 1, and since the frequency range of the processed signal of channel 1 corresponds to [0,1GHz ] of the original digital baseband complex signal, no signal is output in channel 1.
As can be seen from fig. 9, after quadrature modulation, the effective frequency range of channel 1 is shifted to [5GHz, 6GHz ], and since the original digital complex signal does not contain useful information in [0,1GHz ], only a random noise signal is output in channel 1.
Fig. 10 is a frequency spectrum of a signal obtained by the two-channel modulation output combining, and it can be seen from the diagram that the center frequency is 5GHz, the instantaneous bandwidth is 2GHz, and the original-900 MHz digital baseband complex signal is output after two-channel orthogonal modulation to obtain a radio frequency output of 4.1GHz, thereby achieving the intended target.
As can be seen from fig. 10, after the combiner, a wideband modulation signal with a bandwidth of 2GHz is generated, and the main signal has a power of 32dBm at 4.1GHz and an in-band noise power value of-20 dBm, thereby proving feasibility of the invention, that is, the wideband modulation signal with a bandwidth of BW is generated by N quadrature modulation chips with a modulation bandwidth of BW/N, and the noise power value in the pass band is not increased.
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.
Claims (1)
1. A method for improving modulation bandwidth through multi-channel parallel segmented modulation, comprising the steps of:
(1) synthesizing the frequency range of [ -2 pi BW/2f through FPGAs,2πBW/2fs]Of the digital baseband complex signal x (n), wherein fsBW is more than or equal to BW, BW is modulation bandwidth;
(2) generating N paths of digital complex local oscillation signals through a digital oscillator, and simultaneously carrying out digital complex frequency mixing on x (N) and the N paths of digital complex local oscillation signals; wherein, the k-th path digital complex local oscillator signal is marked as Ldk＝exp(jωdkn) corresponding to frequency ωdkExpressed as:
wherein k is 0,1,.., N-1;
(3) filtering each path of signal after the digital complex mixing through a low-pass filter, and outputting N paths of baseband complex signals;
(4) respectively sampling each sub-band complex signal by using DAC (digital-to-analog converter), and outputting N paths of sampling signals with sampling rate fsThe frequency ranges are [ -BW/2N, BW/2N]Analog baseband complex signal x ofk(t)；
(5) And generating N local oscillator signals by using the PLL, wherein the frequency of each local oscillator signal is represented as:
fak＝fRF+(2k+1-N)BW/2N
respectively carrying out quadrature modulation on the path analog baseband complex signal and the corresponding local oscillation signal through a quadrature modulation chip to complete the frequency spectrum shift of the analog baseband complex signal;
(6) signal synthesis
Adding the N paths of orthogonally modulated signals by using a combiner to finally generate a signal with a center frequency fRFInstantaneous bandwidthWideband modulation signal x (t) for BW;
wherein the cut-off frequency of the low-pass filter is 2 pi BW/2Nfs。
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