CN110932712B - Interface circuit of connector and electronic device - Google Patents
Interface circuit of connector and electronic device Download PDFInfo
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- CN110932712B CN110932712B CN201811093035.9A CN201811093035A CN110932712B CN 110932712 B CN110932712 B CN 110932712B CN 201811093035 A CN201811093035 A CN 201811093035A CN 110932712 B CN110932712 B CN 110932712B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses an interface circuit of a connector, and belongs to the technical field of connectors. The interface circuit includes: the level shifting circuit comprises a biasing circuit, a field effect transistor, a triode and a first resistor. In the embodiment of the invention, the field effect transistor is controlled to work in an amplifying state through the voltage output by the voltage output end of the bias circuit, when external equipment is not connected to the connected interface contact, the triode works in a conducting state under the control of the window comparison circuit, and then the voltage division processing is carried out on the level signal detected by the logic detection pin of the connector through the field effect transistor and the first resistor, so that the voltage of the interface contact of the connector is ensured to be lower than the voltage of the electrolytic reaction generated by water vapor. When the external equipment is connected to the interface contact of the connector, the window comparison circuit controls the triode to work in a cut-off state based on the level signal detected by the interface contact of the connector, so that the detection of the external equipment is realized.
Description
Technical Field
The present invention relates to the field of connectors, and in particular, to an interface circuit and an electronic device of a connector.
Background
Along with the continuous development of the connector, the USB (Universal Serial Bus ) Type-C connector is a connector widely used by users based on the characteristics of strong charging capability, fast data transmission rate, universal applicability and the like. However, in order to ensure normal use of the USB Type-C connector, the interface circuit of the connector interface needs to be maintained in a high-level state (e.g., 5 volts) in order to be able to correctly detect and identify the device Type of the inserted external device when the external device is inserted into the connector interface. However, the exposed connector interface is very easy to contact with water vapor, and when the level is higher than 1.5V, the water vapor can generate electrolytic reaction, so that the metal contact of the interface circuit is damaged, and the problems of poor contact and the like are caused in the subsequent use. Therefore, there is a need for an interface circuit that can avoid the problem of electrolytic reaction of water vapor while enabling normal identification of the device type of the external device.
Disclosure of Invention
The invention provides an interface circuit of a connector, which can solve the problem that the interface circuit is easy to generate electrolytic reaction due to water vapor and realize normal identification of the equipment type of external equipment. The technical scheme is as follows:
in a first aspect, there is provided an interface circuit of a connector, the interface circuit comprising: a level shift circuit and a window comparison circuit;
the level transfer circuit comprises a bias circuit, a field effect transistor, a triode and a first resistor, wherein the grid electrode of the field effect transistor is electrically connected with the voltage output end of the bias circuit, the drain electrode of the field effect transistor is electrically connected with the logic detection pin of the connector, the source electrode of the field effect transistor is respectively and electrically connected with the interface contact of the connector, the collector electrode of the triode and the input end of the window comparison circuit, the base electrode of the triode is electrically connected with the control end of the window comparison circuit, the first resistor is connected between the emitter electrode of the triode and the ground in series, and the grounding end of the level transfer circuit and the grounding end of the window comparison circuit are grounded;
the field effect transistor works in an amplifying state based on the voltage output by the bias circuit, when external equipment is not connected to an interface contact of the connector, the triode works in a conducting state based on the window comparison circuit, and the voltage of a logic detection pin of the connector is divided by the field effect transistor and the first resistor; when the external device is connected to the interface contact of the connector, the triode works in a cut-off state based on the window comparison circuit, and the interface contact of the connector detects the external device.
Optionally, the bias circuit includes a first power supply, and a second resistor and a third resistor connected in series between the first power supply and ground, and a voltage output terminal of the bias circuit is a common terminal of the second resistor and the third resistor.
Optionally, the level shift circuit further comprises a first diode;
the cathode of the first diode is electrically connected with the drain electrode of the field effect tube, and the anode of the first diode is electrically connected with the source electrode of the field effect tube.
Optionally, the window comparison circuit comprises a second power supply, a voltage division circuit, a first voltage comparator, a second diode, a third diode and a pull-up circuit;
the first voltage output end of the voltage dividing circuit is electrically connected with the non-inverting input end of the first voltage comparator, and the second voltage output end of the voltage dividing circuit is electrically connected with the inverting input end of the second voltage comparator;
the inverting input end of the first voltage comparator and the non-inverting input end of the second voltage comparator are respectively and electrically connected with the output end of the level shifting circuit, the positive power end of the first voltage comparator and the positive power end of the second voltage comparator are respectively and electrically connected with the second power supply, the negative power end of the first voltage comparator and the negative power end of the second voltage comparator are respectively grounded, the output end of the first voltage comparator is electrically connected with the negative electrode of the second diode, and the output end of the second voltage comparator is electrically connected with the negative electrode of the third diode;
and the output end of the pull-up circuit is electrically connected with the positive electrode of the second diode, the positive electrode of the third diode and the control end of the level shifting circuit respectively.
Optionally, the voltage dividing circuit includes a third power supply, and a fourth resistor, a fifth resistor and a sixth resistor connected in series between the third power supply and ground, wherein a first voltage output end of the voltage dividing circuit is a common end of the fourth resistor and the fifth resistor, and a second voltage output end of the voltage dividing circuit is a common end of the fifth resistor and the sixth resistor.
Optionally, the pull-up circuit includes the fourth power supply, and a seventh resistor connected in series between the fourth power supply and the anode of the second diode.
Optionally, when the external device is not connected to the interface contact of the connector, the voltage of the source electrode of the field effect transistor is smaller than the voltage of the first voltage output end of the voltage dividing circuit and larger than the voltage of the second voltage output end of the voltage dividing circuit, and the output end of the pull-up circuit outputs a high-level signal;
when external equipment is connected to the interface contact of the connector, the voltage of the source electrode of the field effect transistor is larger than the voltage of the first voltage output end of the voltage dividing circuit or smaller than the voltage of the second voltage output end of the voltage dividing circuit, and the output end of the pull-up circuit outputs a low-level signal.
Optionally, the field effect transistor is an NMOS (N-Metal-Oxide-Semiconductor) type field effect transistor, and the triode is an NPN type triode.
Optionally, the second resistor and the third resistor are variable resistors.
In a second aspect, an electronic device is provided, wherein the electronic device is provided with a connector, and the connector is provided with the interface circuit according to the first aspect.
The technical scheme provided by the invention has the beneficial effects that at least the following steps are included:
according to the invention, the field effect transistor is controlled to work in an amplifying state through the voltage output by the voltage output end of the bias circuit, when external equipment is not connected to the connected interface contact, the triode is conducted under the control of the window comparison circuit, at the moment, the logic detection pin, the field effect transistor, the triode and the first resistor of the connector are conducted, and then the voltage division processing is carried out on the level signal detected by the logic detection pin of the connector through the field effect transistor and the first resistor, so that the voltage of the interface contact of the connector is ensured to be lower than the voltage of electrolytic reaction generated by water vapor, and the interface contact of the connector is prevented from being damaged. When the external equipment is connected to the interface contact of the connector, the window comparison circuit controls the triode to work in a cut-off state based on the level signal detected by the interface contact of the connector, and the logic detection pin of the connector, the field effect transistor and the interface contact of the connector are conducted, so that the identification of the equipment type of the external equipment is realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an interface circuit of a connector according to an embodiment of the present invention;
fig. 2 is a diagram of square wave signals detected by a logic detection pin of a connector according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an interface circuit of another connector according to an embodiment of the present invention.
Reference numerals:
cc_cpu: logic detection pins of the connector; cc_conn: interface contacts of the connector;
1: a level shift circuit; 1a: an output terminal of the level shift circuit; 1b: a control terminal of the level shift circuit;
11: a bias circuit; 11a: a voltage output terminal of the bias circuit; v1: a first power supply; r2: a second resistor; r3: a third resistor;
12: a field effect transistor; g: a gate of the field effect transistor; d: a drain electrode of the field effect transistor; s: a source of a field effect transistor;
13: a triode; c: a collector of the triode; b: a base of the triode; e: an emitter of the triode;
r1: a first resistor; d1: a first diode;
2: a window comparison circuit; 2a: an input of the window comparator circuit; 2b: a control end of the window comparison circuit; v2: a second power supply;
21: a voltage dividing circuit; 21a: a first voltage output terminal of the voltage dividing circuit; 21b: a second voltage output terminal of the voltage dividing circuit; v3: a third power supply; r4: a fourth resistor; r5: a fifth resistor; r6: a sixth resistor;
22: a first voltage comparator; 23: a second voltage comparator; d2: a second diode; d3: a third diode;
24: a pull-up circuit; 24a: an output terminal of the pull-up circuit; v4: a fourth power supply; r7: and a seventh resistor.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of an interface circuit of a connector according to an embodiment of the present invention. As shown in fig. 1, the interface circuit includes: a level shift circuit 1 and a window comparison circuit 2; the level transfer circuit 1 comprises a bias circuit 11, a field effect tube 12, a triode 13 and a first resistor R1, wherein a grid G of the field effect tube 12 is electrically connected with a voltage output end 11a of the bias circuit 11, a drain D of the field effect tube 12 is electrically connected with a logic detection pin CC_CPU of a connector, a source S of the field effect tube 12 is respectively electrically connected with an interface contact CC_Conn of the connector, a collector c of the triode 13 and an input end 2a of the window comparison circuit 2, a base b of the triode 13 is electrically connected with a control end 2b of the window comparison circuit 2, the first resistor R1 is connected in series between an emitter e of the triode 13 and the ground, and a grounding end of the level transfer circuit 1 and a grounding end of the window comparison circuit 2 are grounded.
The field effect transistor 12 works in an amplifying state based on the voltage output by the bias circuit 11, when external equipment is not connected to an interface contact CC_Conn of the connector, the triode 13 works in a conducting state based on the window comparison circuit 2, and the voltage of a logic detection pin CC_CPU of the connector is divided by the field effect transistor 12 and the first resistor R1; when an external device is connected to the interface contact cc_conn of the connector, the transistor 13 operates in the off state based on the window comparison circuit 2, and the interface contact cc_conn of the connector detects the external device.
In the embodiment of the invention, the voltage output by the voltage output end 11a of the bias circuit 11 controls the field effect transistor 12 to work in an amplifying state, when external equipment is not connected to the connected interface contact cc_conn, the triode 13 is conducted under the control of the window comparison circuit 2, at the moment, the logic detection pin cc_cpu of the connector, the field effect transistor 12, the triode 13 and the first resistor R1 are conducted, and then the voltage division processing is carried out on the level signal detected by the logic detection pin cc_cpu of the connector through the field effect transistor 12 and the first resistor R1, so that the voltage of the interface contact cc_conn of the connector is ensured to be lower than the voltage of the electrolytic reaction generated by water vapor, and the interface contact cc_conn of the connector is prevented from being damaged. When the external device is connected to the interface contact cc_conn of the connector, the window comparison circuit 2 controls the triode 13 to work in a cut-off state based on a level signal detected by the interface contact cc_conn of the connector, and the logic detection pin cc_cpu of the connector, the field effect tube 12 and the interface contact cc_conn of the connector are conducted, so that detection of the external device is achieved.
The connector may be an USB Type-C connector, but of course, may also be another connector, which is not limited in the embodiment of the present invention. The logic detection pin cc_cpu of the connector is used for detecting a level signal provided by the connector, and the interface contact cc_conn of the connector is used for detecting a level signal of an external device when the external device is accessed. Alternatively, field effect transistor 12 may be an NMOS field effect transistor and transistor 13 may be an NPN transistor.
As shown in fig. 1, the bias circuit 11 includes a first power source V1, and a second resistor R2 and a third resistor R3 connected in series between the first power source V1 and ground, and a voltage output terminal 11a of the bias circuit 11 is a common terminal of the second resistor R2 and the third resistor R3. Since the voltage output terminal 11a of the bias circuit 11 is electrically connected to the gate G of the fet 12, after the voltage is divided by the second resistor R2 and the third resistor R3, the voltage output terminal 11a of the bias circuit 11 can output a voltage having a certain voltage value, so that the fet 12 can be controlled to operate in an amplified state, and at the same time, the fet 12 can be controlled to have a certain on-resistance. In this way, after the logic detection pin cc_cpu, the field effect transistor 12, the triode 13 and the first resistor R1 of the connector are turned on, the level signal detected by the logic detection pin cc_cpu of the connector can be divided by the field effect transistor 12 and the first resistor R1, so that the voltage of the interface contact cc_conn of the connector is ensured to be lower than the voltage of the electrolytic reaction generated by water vapor.
The smaller the voltage output from the voltage output terminal 11a of the bias circuit 11, the larger the on-resistance when the control fet 12 is operated in the amplified state, and the smaller the voltage of the interface contact cc_conn of the connector after the level signal detected by the logic detection pin cc_cpu of the connector is divided by the fet 12 and the first resistor R1. Therefore, after the field effect transistor 12 is controlled to be in the on state by the bias circuit 11, the voltage of the interface contact cc_conn of the connector can be ensured to be lower than the voltage of the water vapor generating electrolysis reaction by increasing the resistance value of the second resistor R2 or decreasing the resistance value of the third resistor R3.
In one possible implementation, the second resistor R2 and the third resistor R3 are variable resistors. In this way, the voltage output from the voltage output terminal 11a of the bias circuit 11 can be adjusted by adjusting the resistance value of the second resistor R2 and the resistance value of the third resistor R3 in the initial stage of design.
In the embodiment of the invention, when the connector is an USB Type-C connector, the connector can be used as a master device or a slave device. When the interface contact CC_Conn of the connector is connected with external equipment, if the logic detection pin CC_CPU of the connector detects a high-level signal and the interface contact CC_Conn of the connector detects a low-level signal, the equipment type of the connector is master equipment, and the equipment type of the external equipment is slave equipment; if the logic detection pin cc_cpu of the connector detects a low level signal and the interface contact cc_conn of the connector detects a high level signal, the device type of the connector is a slave device and the device type of the external device is a master device.
When the connector is used as a master device and the external device is used as a slave device, the connector can realize normal communication between the connector and the external device through the circuit. However, when the connector is used as a slave and the external device is used as a master, the fet 12 is operated in the off state due to the voltage of the source S of the fet 12 being higher than the voltage of the drain. Therefore, in order to ensure normal communication between the connector and the external device when the connector is used as the slave device and the external device is used as the master device, as shown in fig. 1, the level shifter circuit 1 further includes a first diode D1; the cathode of the first diode D1 is electrically connected to the drain D of the field effect transistor 12, and the anode of the first diode D1 is electrically connected to the source S of the field effect transistor 12.
Based on the above-described arrangement, the first diode D1 is turned on when the voltage of the source S of the field-effect transistor 12 is higher than the voltage of the drain, and at this time, the interface contact cc_conn of the connector, the first diode D1, and the logic detection pin cc_cpu of the connector are turned on, thereby realizing normal communication with the connector as a slave device and the external device as a master device.
It should be noted that, when the connector is an USB Type-C connector, the logic detection pin cc_cpu of the connector detects that the level signal is a square wave signal with high and low pulses, and the period may be 50-100 ms. As shown in fig. 2, the high level signal of the square wave signal is 5v, the low level signal is 0 v, and the period is 100 ms.
In the embodiment of the present invention, the voltage value of the first power supply V1 may be 3V, the resistance value of the second resistor R2 may be 200 kiloohms, the resistance value of the third resistor R3 may be 100 kiloohms, and the resistance value of the first resistor R1 may be 10 kiloohms. At the moment of system power-on, the window comparison circuit 2 controls the triode 13 to work in a conducting state, and meanwhile, the voltage output end 11a of the bias circuit 11 can output 1 volt to control the field effect tube 12 to work in an amplifying state and control the field effect tube 12 to have a certain conducting resistance.
When the external device is not connected to the interface contact cc_conn of the connector, if the level signal detected by the logic detection pin cc_cpu of the connector is 5v, the logic detection pin cc_cpu of the connector, the field effect transistor 12 and the first resistor R1 are turned on, and then the voltage division processing is performed on the 5v level signal detected by the logic detection pin cc_cpu of the connector through the field effect transistor 12 and the first resistor R1, so that the voltage of the source S of the field effect transistor 12, that is, the voltage of the interface contact cc_conn of the connector is 1.2 v. Further, the window comparison circuit 2 controls the triode 13 to be kept in a conducting state based on the voltage of 1.2V of the source electrode S of the field effect tube 12, so that the voltage of the source electrode S of the field effect tube 12 is kept to be 1.2V and is lower than the voltage of 1.5V of the electrolysis reaction generated by water vapor, and the electrolysis reaction generated by the water vapor of the interface contact CC_Conn of the connector is avoided.
After the voltage division processing is performed on the 5v level signal detected by the logic detection pin cc_cpu of the connector through the field effect transistor 12 and the first resistor R1, the current of the source S of the field effect transistor 12 may be calculated according to the following formula (1) and formula (2), and then the resistance value of the current first resistor R1 may be multiplied to obtain the voltage of the interface contact cc_conn of the connector.
In the above formula (1) and formula (2), V1 refers to the voltage value of the first power supply V1; r2 is the resistance value of the second resistor R2; r3 is the resistance value of the third resistor R3; v gs Refers to the voltage difference between the gate G and the source of the fet 12; i.e d Refers to the current value of the drain D of the field effect transistor 12; r1 is the resistance value of the first resistor R1; i.e DSS The saturation leakage current value of the field effect transistor 12 is based on the constant of the field effect transistor; v T Refers to the on-voltage value of the fet 12, which is based on the fet constant. In the embodiment of the invention, v1 has a value of 3V; r2 has a value of 200 kiloohms; r3 has a value of 100 kiloohms; r1 has a value of 10 kiloohms; i.e DSS Has a value of 0.0768, v T The value of (2) is 0.8.
When the external device accesses the interface contact cc_conn of the connector, if the level signal detected by the logic detection pin cc_cpu of the connector is a high level signal, the level signal detected by the interface contact cc_conn of the connector is a low level signal, that is, the level signal detected by the logic detection pin cc_cpu of the connector is 5 volts, and the level signal detected by the interface contact cc_conn of the connector is 0 volts. At this time, the window comparison circuit 2 controls the transistor 13 to be in an off state based on the 0 volt voltage of the interface contact cc_conn of the connector, in addition, the logic detection pin cc_cpu of the connector, the field effect transistor 12 and the interface contact cc_conn of the connector are conducted, the connector judges itself as a master device, and the external device is a slave device, so that normal communication between the connector and the external device is realized.
If the level signal detected by the logic detection pin cc_cpu of the connector and the level signal detected by the interface contact cc_conn of the connector are both high level signals, that is, the level signal detected by the logic detection pin cc_cpu of the connector and the level signal detected by the interface contact cc_conn of the connector are both 5 volts. At this time, the window comparator circuit 2 controls the transistor 13 to be in an off state based on the 5v voltage of the interface contact cc_conn of the connector, and the connector determines that the connector is in an invalid recognition state because both the level signal detected by the logic detection pin cc_cpu of the connector and the level signal detected by the interface contact cc_conn of the connector are high level signals.
If the level signal detected by the logic detection pin cc_cpu of the connector and the level signal detected by the interface contact cc_conn of the connector are both low level signals, that is, the level signal detected by the logic detection pin cc_cpu of the connector and the level signal detected by the interface contact cc_conn of the connector are both 0 volt. At this time, the window comparator circuit 2 controls the transistor 13 to be in an off state based on the 0 volt voltage of the interface contact cc_conn of the connector, and the connector determines that the recognition state is not valid because the level signal detected by the logic detection pin cc_cpu of the connector and the level signal detected by the interface contact cc_conn of the connector are both low level signals.
If the level signal detected by the logic detection pin cc_cpu of the connector is a low level signal, the level signal detected by the interface contact cc_conn of the connector is a high level signal, that is, the level signal detected by the logic detection pin cc_cpu of the connector is 0 volt, and the level signal detected by the interface contact cc_conn of the connector is 5 volt. At this time, the window comparison circuit 2 controls the transistor 13 to be in a cut-off state based on the 5v voltage of the interface contact cc_conn of the connector, and in addition, the interface contact cc_conn of the connector, the first diode D1 and the logic detection pin cc_cpu of the connector are turned on, the connector judges itself to be a slave device, and the external device is a master device, so that normal communication between the connector and the external device is realized.
When the internal circuit of the external device is integrated with a pull-up resistor of 56 kiloohms, 22 kiloohms, or 10 kiloohms, the level signal detected by the interface contact cc_conn of the connector is a high level signal; when the internal circuit of the external device is integrated with a pull-down resistor of 5.1 kiloohms or 1 kiloohm, the level signal detected by the interface contact cc_conn of the connector is a low level signal.
In the embodiment of the present invention, when the transistor 13 is controlled to operate in the on or off state by the window comparison circuit 2, as shown in fig. 3, the window comparison circuit 2 includes a second power supply V2, a voltage division circuit 21, a first voltage comparator 22, a second voltage comparator 23, a second diode D2, a third diode D3, and a pull-up circuit 24; the first voltage output end 21a of the voltage dividing circuit 21 is electrically connected with the non-inverting input end of the first voltage comparator 22, and the second voltage output end 21b of the voltage dividing circuit 21 is electrically connected with the inverting input end of the second voltage comparator 23; the inverting input end of the first voltage comparator 22 and the non-inverting input end of the second voltage comparator 23 are respectively and electrically connected with the output end 1a of the level shifting circuit 1, the positive power end of the first voltage comparator 22 and the positive power end of the second voltage comparator 23 are respectively and electrically connected with the second power supply V2, the negative power end of the first voltage comparator 22 and the negative power end of the second voltage comparator 23 are respectively grounded, the output end of the first voltage comparator 22 is electrically connected with the negative electrode of the second diode D2, and the output end of the second voltage comparator 23 is electrically connected with the negative electrode of the third diode D3; the output terminal 24a of the pull-up circuit 24 is electrically connected to the positive electrode of the second diode D2, the positive electrode of the third diode D3, and the control terminal 1b of the level shift circuit 1, respectively.
When the external device is not connected to the interface contact cc_conn of the connector, the voltage of the source S of the field effect transistor 12 is smaller than the voltage of the first voltage output terminal 21a of the voltage dividing circuit 21 and greater than the voltage of the second voltage output terminal 21b of the voltage dividing circuit 21, and at this time, the first voltage comparator 22 and the second voltage comparator 23 both output high-level signals, and the second diode D2 and the third diode D3 are both in the off state. In this way, the output end 24a of the pull-up circuit 24 can output a high level signal, and the output end 24a of the pull-up circuit 24 is electrically connected with the base b of the triode 13, so that the triode 13 can be controlled to be in a conducting state.
When an external device is connected to the interface contact cc_conn of the connector, if the voltage of the source S of the fet 12 is greater than the voltage of the first voltage output terminal 21a of the voltage dividing circuit 21, the voltage of the source S of the fet 12 is necessarily greater than the voltage of the second voltage output terminal 21b of the voltage dividing circuit 21, at this time, the first voltage comparator 22 outputs a low level signal, and the second voltage comparator 23 outputs a high level signal. When the first voltage comparator 22 outputs a low level signal and the second voltage comparator 23 outputs a high level signal, the second transistor 13 is in an on state and the third diode D3 is in an off state. In this way, the output terminals of the pull-up circuit 24, the second diode D2 and the first voltage comparator 22 are turned on, so that the output terminal 24a of the pull-up circuit 24 outputs a low level signal, thereby controlling the transistor 13 to be in an off state.
If the voltage of the source S of the field-effect transistor 12 is smaller than the voltage of the second voltage output terminal 21b of the voltage dividing circuit 21, the voltage of the source S of the field-effect transistor 12 is necessarily smaller than the voltage of the first voltage output terminal 21a of the voltage dividing circuit 21, and at this time, the first voltage comparator 22 outputs a high level signal and the second voltage comparator 23 outputs a low level signal. When the first voltage comparator 22 outputs a high level signal and the second voltage comparator 23 outputs a low level signal, the second transistor 13 is turned off and the third diode D3 is turned on. In this way, the outputs of the pull-up circuit 24, the third diode D3 and the second voltage comparator 23 are turned on, so that the output 24a of the pull-up circuit 24 outputs a low level signal, thereby controlling the transistor 13 to be in an off state.
As shown in fig. 3, the voltage dividing circuit 21 may include a third power supply V3, and a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6 connected in series between the third power supply V3 and ground, where the first voltage output terminal 21a of the voltage dividing circuit 21 is a common terminal of the fourth resistor R4 and the fifth resistor R5, and the second voltage output terminal 21b of the voltage dividing circuit 21 is a common terminal of the fifth resistor R5 and the sixth resistor R6. The pull-up circuit 24 may include a fourth power supply V4, and a seventh resistor R7 connected in series between the fourth power supply V4 and the anode of the second diode D2.
In the embodiment of the invention, the voltage values of the second power supply V2 and the fourth power supply V4 are equal, and may be 5V, the voltage value of the third power supply V3 may be 3V, the resistance value of the fourth resistor R4 may be 100 kiloohms, the resistance value of the fifth resistor R5 may be 120 kiloohms, the resistance value of the sixth resistor R6 may be 80 kiloohms, and the resistance value of the seventh resistor R7 may be 100 kiloohms. The voltage divider circuit 21 may output a voltage of 2 volts at the first voltage output terminal 21a and a voltage of 0.8 volts at the second voltage output terminal 21 b.
When the interface contact cc_conn of the connector is not connected to an external device, 1.2 volts of the source S of the field effect transistor 12 is output to the reverse input terminal of the first voltage comparator 22 and the forward input terminal of the second voltage comparator 23, respectively, and 2 volts of the first voltage output terminal 21a of the voltage dividing circuit 21 and 0.8 volts of the second output terminal are output to the forward input terminal of the first voltage comparator 22 and the reverse input terminal of the second voltage comparator 23, respectively, since the voltage 2 volts of the non-inverting input terminal of the first voltage comparator 22 is higher than the voltage 1.2 volts of the reverse input terminal, and the voltage 1.2 volts of the non-inverting input terminal of the second voltage comparator 23 is higher than the voltage 0.8 volts of the reverse input terminal, both the first voltage comparator 22 and the second voltage comparator 23 output high level signals. At this time, the second diode D2 and the third diode D3 are both in the off state, so that the output terminal of the pull-up resistor can output a high level signal, thereby controlling the transistor 13 to operate in the on state.
When the interface contact cc_conn of the connector is not connected to an external device, the voltage of the source S of the fet 12 may be 0 v or 5 v. If the voltage of the source S of the field effect transistor 12 is 0 v, when the voltage of the source S of the field effect transistor 12 is output to the reverse input terminal of the first voltage comparator 22 and the forward input terminal of the second voltage comparator 23, respectively, and the voltage of 2 v of the first voltage output terminal 21a of the voltage dividing circuit 21 and the voltage of 0.8 v of the second output terminal are output to the forward input terminal of the first voltage comparator 22 and the reverse input terminal of the second voltage comparator 23, respectively, the first voltage comparator 22 outputs a high level signal and the second voltage comparator 23 outputs a low level signal because the voltage of 2 v of the non-inverting input terminal of the first voltage comparator 22 is higher than the voltage of 0 v of the reverse input terminal, and the voltage of 0 v of the non-inverting input terminal of the second voltage comparator 23 is lower than the voltage of 0.8 v of the reverse input terminal. At this time, the second diode D2 is operated in an off state, and the third diode D3 is operated in an on state, so that the output terminal of the pull-up resistor can output a low level signal, thereby controlling the transistor 13 to be operated in an off state.
If the voltage of the source S of the field effect transistor 12 is 5 volts, the 5 volts of the source S of the field effect transistor 12 is output to the reverse input terminal of the first voltage comparator 22 and the forward input terminal of the second voltage comparator 23, respectively, and the 2 volts of the first voltage output terminal 21a of the voltage dividing circuit 21 and the 0.8 volts of the second output terminal are output to the forward input terminal of the first voltage comparator 22 and the reverse input terminal of the second voltage comparator 23, respectively, the first voltage comparator 22 outputs a low level signal and the second voltage comparator 23 outputs a high level signal since the 2 volts of the non-inverting input terminal of the first voltage comparator 22 is lower than the 5 volts of the reverse input terminal and the 5 volts of the non-inverting input terminal of the second voltage comparator 23 is higher than the 0.8 volts of the reverse input terminal. At this time, the second diode D2 is operated in an on state, and the third diode D3 is operated in an off state, so that the output terminal of the pull-up resistor can output a low level signal, thereby controlling the transistor 13 to be operated in an off state.
In the embodiment of the invention, at the moment of system power-on, the window comparison circuit controls the triode to work in a conducting state, and meanwhile, the voltage output by the voltage output end of the bias circuit controls the field effect tube to work in an amplifying state and controls the field effect tube to have a certain conducting resistance. When the external equipment is not connected with the connected interface contact, the high-level signal output by the window comparison circuit controls the triode to work in a conducting state, and at the moment, the voltage division processing is carried out on the level signal detected by the logic detection pin of the connector through the field effect tube and the first resistor, so that the voltage of the interface contact of the connector is ensured to be lower than the voltage of electrolytic reaction generated by water vapor, and the interface contact of the connector is prevented from being damaged. When the external equipment is connected to the interface contact of the connector, the window comparison circuit outputs a low-level signal based on the level signal detected by the interface contact of the connector so as to control the triode to work in a cut-off state, and at the moment, the logic detection pin of the connector, the field effect tube and the interface contact of the connector are conducted, so that the identification of the equipment type of the external equipment is realized.
The embodiment of the invention also provides an electronic device, which is provided with the connector and the interface circuit of the embodiment, so that the problem of poor subsequent contact caused by hydrolysis reaction of the interface circuit of the connector of the electronic device when the electronic device is not connected to external equipment is avoided, and meanwhile, when the external equipment is connected to the electronic device, the equipment type of the external equipment is normally identified.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (9)
1. An interface circuit of a connector, the interface circuit comprising: a level shift circuit (1) and a window comparison circuit (2);
the level shifting circuit (1) comprises a biasing circuit (11), a field effect tube (12), a triode (13) and a first resistor (R1), wherein a grid electrode (G) of the field effect tube (12) is electrically connected with a voltage output end (11 a) of the biasing circuit (11), a drain electrode (D) of the field effect tube (12) is electrically connected with a logic detection pin (CC_CPU) of the connector, a source electrode (S) of the field effect tube (12) is respectively electrically connected with an interface contact (CC_Conn) of the connector, a collector electrode (c) of the triode (13) and an input end (2 a) of the window comparison circuit (2), a base electrode (b) of the triode (13) is electrically connected with a control end (2 b) of the window comparison circuit (2), and the first resistor (R1) is connected between an emitter electrode (e) of the triode (13) and the ground in series, and the ground end of the level shifting circuit (1) and the ground end of the window comparison circuit (2) are grounded;
the window comparison circuit (2) comprises a second power supply (V2), a voltage division circuit (21), a first voltage comparator (22), a second voltage comparator (23), a second diode (D2), a third diode (D3) and a pull-up circuit (24);
a first voltage output end (21 a) of the voltage dividing circuit (21) is electrically connected with a non-inverting input end of the first voltage comparator (22), and a second voltage output end (21 b) of the voltage dividing circuit (21) is electrically connected with an inverting input end of the second voltage comparator (23);
the inverting input end of the first voltage comparator (22) and the non-inverting input end of the second voltage comparator (23) are respectively and electrically connected with the output end (1 a) of the level shifting circuit (1), the positive power end of the first voltage comparator (22) and the positive power end of the second voltage comparator (23) are respectively and electrically connected with the second power supply (V2), the negative power end of the first voltage comparator (22) and the negative power end of the second voltage comparator (23) are respectively grounded, the output end of the first voltage comparator (22) is electrically connected with the negative electrode of the second diode (D2), and the output end of the second voltage comparator (23) is electrically connected with the negative electrode of the third diode (D3);
the output end (24 a) of the pull-up circuit (24) is electrically connected with the positive electrode of the second diode (D2), the positive electrode of the third diode (D3) and the control end (1 b) of the level shifting circuit (1) respectively.
2. Interface circuit according to claim 1, characterized in that the bias circuit (11) comprises a first power supply (V1), and a second resistor (R2) and a third resistor (R3) connected in series between the first power supply (V1) and ground, the voltage output (11 a) of the bias circuit (11) being the common terminal of the second resistor (R2) and the third resistor (R3).
3. Interface circuit according to claim 1, characterized in that the level shift circuit (1) further comprises a first diode (D1);
the cathode of the first diode (D1) is electrically connected with the drain electrode (D) of the field effect tube (12), and the anode of the first diode (D1) is electrically connected with the source electrode (S) of the field effect tube (12).
4. Interface circuit according to claim 1, characterized in that the voltage dividing circuit (21) comprises a third power supply (V3), and a fourth resistor (R4), a fifth resistor (R5) and a sixth resistor (R6) connected in series between the third power supply (V3) and ground, the first voltage output (21 a) of the voltage dividing circuit (21) being the common terminal of the fourth resistor (R4) and the fifth resistor (R5), the second voltage output (21 b) of the voltage dividing circuit (21) being the common terminal of the fifth resistor (R5) and the sixth resistor (R6).
5. Interface circuit according to claim 1, characterized in that the pull-up circuit (24) comprises a fourth power supply (V4) and a seventh resistor (R7) connected in series between the fourth power supply (V4) and the anode of the second diode (D2).
6. Interface circuit according to claim 1, characterized in that when an external device is not connected to the interface contact (cc_conn) of the connector, the voltage at the source (S) of the field effect transistor (12) is smaller than the voltage at the first voltage output (21 a) of the voltage dividing circuit (21) and greater than the voltage at the second voltage output (21 b) of the voltage dividing circuit (21), the output (24 a) of the pull-up circuit (24) outputting a high signal;
when an external device is connected to an interface contact (CC_Conn) of the connector, the voltage of a source electrode (S) of the field effect transistor (12) is larger than the voltage of a first voltage output end (21 a) of the voltage dividing circuit (21) or smaller than the voltage of a second voltage output end (21 b) of the voltage dividing circuit (21), and an output end (24 a) of the pull-up circuit (24) outputs a low-level signal.
7. Interface circuit according to claim 1, characterized in that the field effect transistor (12) is an N-type metal-oxide-semiconductor NMOS type field effect transistor and the transistor (13) is an NPN transistor.
8. Interface circuit according to claim 2, characterized in that the second resistor (R2) and the third resistor (R3) are variable resistors.
9. An electronic device, characterized in that the electronic device is provided with a connector provided with an interface circuit as claimed in any one of claims 1-8.
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| CN111882852B (en) * | 2020-07-14 | 2021-10-22 | 深圳市信锐网科技术有限公司 | Access detection circuit, method, master device and storage medium |
| CN111966033B (en) * | 2020-07-17 | 2021-09-28 | 苏州浪潮智能科技有限公司 | Detection system for connection state of high-density connector |
| CN112904122A (en) * | 2021-01-22 | 2021-06-04 | 维沃移动通信有限公司 | Insertion detection circuit and electronic device |
| CN113295956A (en) * | 2021-06-04 | 2021-08-24 | 广州朗国电子科技有限公司 | DP signal source detection circuit, DP signal source detection method and display device |
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Address after: 266071 Shandong city of Qingdao province Jiangxi City Road No. 11 Patentee after: Qingdao Hisense Mobile Communication Technology Co.,Ltd. Address before: 266071 Shandong city of Qingdao province Jiangxi City Road No. 11 Patentee before: HISENSE MOBILE COMMUNICATIONS TECHNOLOGY Co.,Ltd. |
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