CN110932712A - Interface circuit of connector and electronic device - Google Patents
Interface circuit of connector and electronic device Download PDFInfo
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- CN110932712A CN110932712A CN201811093035.9A CN201811093035A CN110932712A CN 110932712 A CN110932712 A CN 110932712A CN 201811093035 A CN201811093035 A CN 201811093035A CN 110932712 A CN110932712 A CN 110932712A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses an interface circuit of a connector, and belongs to the technical field of connectors. The interface circuit includes: the level shifter comprises a bias circuit, a field effect transistor, a triode and a first resistor. In the embodiment of the invention, the field effect transistor is controlled to work in an amplifying state by the voltage output end of the bias circuit, when the external equipment is not connected with the connected interface contact, the triode works in a conducting state under the control of the window comparison circuit, and the level signal detected by the logic detection pin of the connector is subjected to voltage division processing by the field effect transistor and the first resistor, so that the voltage of the interface contact of the connector is lower than the voltage of the water vapor generating electrolytic reaction. When the external equipment is connected to the interface contact of the connector, the window comparison circuit controls the triode to work in a cut-off state based on the level signal detected by the interface contact of the connector, so that the detection of the external equipment is realized.
Description
Technical Field
The present invention relates to the field of connector technologies, and in particular, to an interface circuit of a connector and an electronic device.
Background
With the continuous development of connectors, USB (Universal Serial Bus) Type-C connectors have become a connector widely used by users based on the characteristics of strong charging capability, fast data transmission rate, Universal applicability, and the like. However, in order to ensure the normal use of the USB Type-C connector, the interface circuit of the connector interface needs to be maintained in a high state (e.g., 5 volts) so that the device Type of the inserted external device can be correctly detected and identified when the external device is inserted into the connector interface. However, the exposed connector interface is very easy to contact with water vapor, and the water vapor can generate electrolytic reaction when the level is higher than 1.5V, so that metal contacts of an interface circuit are damaged, and the problems of poor contact and the like are caused in the subsequent use. Therefore, there is a need for an interface circuit that can avoid the problem of the electrolytic reaction of moisture, while being able to recognize the device type of the external device normally.
Disclosure of Invention
The invention provides an interface circuit of a connector, which can solve the problem that the interface circuit is easy to generate electrolytic reaction due to water vapor and realize normal identification of the equipment type of external equipment. The technical scheme is as follows:
in a first aspect, an interface circuit of a connector is provided, the interface circuit including: a level shift circuit and a window comparison circuit;
the level shift circuit comprises a bias circuit, a field effect transistor, a triode and a first resistor, wherein the grid electrode of the field effect transistor is electrically connected with the voltage output end of the bias circuit, the drain electrode of the field effect transistor is electrically connected with a logic detection pin of the connector, the source electrode of the field effect transistor is respectively electrically connected with an interface contact of the connector, the collector electrode of the triode and the input end of the window comparison circuit, the base electrode of the triode is electrically connected with the control end of the window comparison circuit, the first resistor is connected between the emitter electrode of the triode and the ground in series, and the ground end of the level shift circuit and the ground end of the window comparison circuit are grounded;
the field effect transistor works in an amplifying state based on the voltage output by the bias circuit, when external equipment is not connected to an interface contact of the connector, the triode works in a conducting state based on the window comparison circuit, and the voltage of a logic detection pin of the connector is divided by the field effect transistor and the first resistor; when the external equipment is connected to the interface contact of the connector, the triode works in a cut-off state based on the window comparison circuit, and the interface contact of the connector detects the external equipment.
Optionally, the bias circuit includes a first power supply, and a second resistor and a third resistor connected in series between the first power supply and ground, and a voltage output terminal of the bias circuit is a common terminal of the second resistor and the third resistor.
Optionally, the level shift circuit further comprises a first diode;
the cathode of the first diode is electrically connected with the drain electrode of the field effect tube, and the anode of the first diode is electrically connected with the source electrode of the field effect tube.
Optionally, the window comparison circuit includes a second power supply, a voltage divider circuit, a first voltage comparator, a second diode, a third diode, and a pull-up circuit;
a first voltage output end of the voltage division circuit is electrically connected with a non-inverting input end of the first voltage comparator, and a second voltage output end of the voltage division circuit is electrically connected with an inverting input end of the second voltage comparator;
the negative power supply circuit comprises a level shift circuit, a first voltage comparator, a second voltage comparator, a first diode, a second diode, a first power supply, a second power supply, a first diode, a second diode and a third diode, wherein the negative-phase input end of the first voltage comparator and the non-phase input end of the second voltage comparator are respectively electrically connected with the output end of the level shift circuit;
and the output end of the pull-up circuit is respectively and electrically connected with the anode of the second diode, the anode of the third diode and the control end of the level shift circuit.
Optionally, the voltage divider circuit includes a third power supply, and a fourth resistor, a fifth resistor, and a sixth resistor connected in series between the third power supply and ground, where a first voltage output end of the voltage divider circuit is a common end of the fourth resistor and the fifth resistor, and a second voltage output end of the voltage divider circuit is a common end of the fifth resistor and the sixth resistor.
Optionally, the pull-up circuit includes the fourth power supply, and a seventh resistor connected in series between the fourth power supply and the anode of the second diode.
Optionally, when an external device is not connected to the interface contact of the connector, the voltage of the source of the field effect transistor is smaller than the voltage of the first voltage output end of the voltage division circuit and larger than the voltage of the second voltage output end of the voltage division circuit, and the output end of the pull-up circuit outputs a high-level signal;
when the external equipment is connected to the interface contact of the connector, the voltage of the source electrode of the field effect transistor is larger than the voltage of the first voltage output end of the voltage division circuit or smaller than the voltage of the second voltage output end of the voltage division circuit, and the output end of the pull-up circuit outputs a low level signal.
Optionally, the fet is an NMOS (N-Metal-Oxide-Semiconductor) fet, and the transistor is an NPN transistor.
Optionally, the second resistor and the third resistor are variable resistors.
In a second aspect, an electronic device is provided, wherein the electronic device is provided with a connector, and the connector is provided with the interface circuit of the first aspect.
The technical scheme provided by the invention has the beneficial effects that at least:
the field effect transistor works in an amplifying state under the control of the window comparison circuit when external equipment is not connected with the connected interface contact, the triode is conducted under the control of the window comparison circuit, at the moment, the logic detection pin of the connector, the field effect transistor, the triode and the first resistor are conducted, and then the voltage division processing is carried out on the level signal detected by the logic detection pin of the connector through the field effect transistor and the first resistor, so that the voltage of the interface contact of the connector is lower than the voltage of electrolytic reaction generated by water vapor, and the interface contact of the connector is prevented from being damaged. When the external equipment is connected to the interface contact of the connector, the window comparison circuit controls the triode to work in a cut-off state based on the level signal detected by the interface contact of the connector, and the logic detection pin of the connector, the field effect transistor and the interface contact of the connector are conducted, so that the identification of the equipment type of the external equipment is realized.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of an interface circuit of a connector according to an embodiment of the present invention;
FIG. 2 is a diagram of a square wave signal detected by a logic detection pin of a connector according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an interface circuit of another connector according to an embodiment of the present invention.
Reference numerals:
CC _ CPU: a logic detection pin of the connector; CC _ Conn: interface contacts of the connector;
1: a level shift circuit; 1 a: an output terminal of the level shift circuit; 1 b: a control terminal of the level shift circuit;
11: a bias circuit; 11 a: a voltage output terminal of the bias circuit; v1: a first power supply; r2: a second resistor; r3: a third resistor;
12: a field effect transistor; g: a gate of the field effect transistor; d: a drain electrode of the field effect transistor; s: a source electrode of the field effect transistor;
13: a triode; c: a collector of the triode; b: a base of the triode; e: an emitter of the triode;
r1: a first resistor; d1: a first diode;
2: a window comparison circuit; 2 a: an input terminal of the window comparison circuit; 2 b: a control terminal of the window comparison circuit; v2: a second power supply;
21: a voltage dividing circuit; 21 a: a first voltage output terminal of the voltage divider circuit; 21 b: a second voltage output end of the voltage division circuit; v3: a third power supply; r4: a fourth resistor; r5: a fifth resistor; r6: a sixth resistor;
22: a first voltage comparator; 23: a second voltage comparator; d2: a second diode; d3: a third diode;
24: a pull-up circuit; 24 a: an output terminal of the pull-up circuit; v4: a fourth power supply; r7: and a seventh resistor.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of an interface circuit of a connector according to an embodiment of the present invention. As shown in fig. 1, the interface circuit includes: a level shift circuit 1 and a window comparison circuit 2; the level shift circuit 1 comprises a bias circuit 11, a field effect transistor 12, a triode 13 and a first resistor R1, wherein a gate G of the field effect transistor 12 is electrically connected with a voltage output end 11a of the bias circuit 11, a drain D of the field effect transistor 12 is electrically connected with a logic detection pin CC _ CPU of a connector, a source S of the field effect transistor 12 is electrically connected with an interface contact CC _ Conn of the connector, a collector c of the triode 13 and an input end 2a of the window comparison circuit 2, a base b of the triode 13 is electrically connected with a control end 2b of the window comparison circuit 2, the first resistor R1 is connected between an emitter e of the triode 13 and the ground in series, and a ground end of the level shift circuit 1 and a ground end of the window comparison circuit 2 are grounded.
The field effect transistor 12 works in an amplifying state based on the voltage output by the bias circuit 11, when the external equipment is not connected to an interface contact point CC _ Conn of the connector, the triode 13 works in a conducting state based on the window comparison circuit 2, and the voltage of a logic detection pin CC _ CPU of the connector is divided by the field effect transistor 12 and the first resistor R1; when the external device is connected to the interface contact CC _ Conn of the connector, the triode 13 operates in a cut-off state based on the window comparison circuit 2, and the interface contact CC _ Conn of the connector detects the external device.
In the embodiment of the present invention, the voltage output from the voltage output terminal 11a of the bias circuit 11 controls the fet 12 to operate in an amplification state, when the external device is not connected to the connected interface contact CC _ Conn, the transistor 13 is turned on under the control of the window comparison circuit 2, at this time, the logic detection pin CC _ CPU of the connector, the fet 12, the transistor 13, and the first resistor R1 are turned on, and then the voltage division processing is performed on the level signal detected by the logic detection pin CC _ CPU of the connector through the fet 12 and the first resistor R1, so as to ensure that the voltage of the interface contact CC _ Conn of the connector is lower than the voltage of the electrolytic reaction generated by the water vapor, so as to avoid damaging the interface contact CC _ Conn of the connector. When the external device is connected to the interface contact CC _ Conn of the connector, the window comparison circuit 2 controls the triode 13 to operate in a cut-off state based on the level signal detected by the interface contact CC _ Conn of the connector, and the logic detection pin CC _ CPU of the connector, the field effect transistor 12 and the interface contact CC _ Conn of the connector are turned on, thereby realizing the detection of the external device.
The connector may be a USB Type-C connector, and certainly, may also be other connectors, which is not limited in this embodiment of the present invention. The logic detection pin CC _ CPU of the connector is used for detecting a level signal provided by the connector, and the interface contact CC _ Conn of the connector is used for detecting the level signal of the external equipment when the external equipment is connected. Alternatively, fet 12 may be an NMOS fet and transistor 13 may be an NPN transistor.
As shown in fig. 1, the bias circuit 11 includes a first power source V1, and a second resistor R2 and a third resistor R3 connected in series between the first power source V1 and ground, and the voltage output terminal 11a of the bias circuit 11 is a common terminal of the second resistor R2 and the third resistor R3. Since the voltage output terminal 11a of the bias circuit 11 is electrically connected to the gate G of the fet 12, after voltage division is performed by the second resistor R2 and the third resistor R3, the voltage output terminal 11a of the bias circuit 11 can output a voltage having a certain voltage value, so that the fet 12 can be controlled to operate in an amplification state, and the fet 12 can be controlled to have a certain on-resistance. Thus, after the logic detection pin CC _ CPU, the field effect transistor 12, the triode 13 and the first resistor R1 of the connector are turned on, the level signal detected by the logic detection pin CC _ CPU of the connector can be divided by the field effect transistor 12 and the first resistor R1, and the voltage of the interface contact CC _ Conn of the connector is further ensured to be lower than the voltage of the water vapor generation electrolytic reaction.
It should be noted that, the smaller the voltage output from the voltage output terminal 11a of the bias circuit 11, the larger the on-resistance when the fet 12 is controlled to operate in the amplification state, and the smaller the voltage at the interface contact CC _ Conn of the connector after the level signal detected by the logic detection pin CC _ CPU of the connector is divided by the fet 12 and the first resistor R1. Therefore, after the field effect transistor 12 is controlled to be in the conducting state by the bias circuit 11, the voltage of the interface contact CC _ Conn of the connector can be ensured to be lower than the voltage of the water vapor generation electrolytic reaction by increasing the resistance value of the second resistor R2 or decreasing the resistance value of the third resistor R3.
In one possible implementation, the second resistor R2 and the third resistor R3 are variable resistors. In this way, the resistance value of the second resistor R2 and the resistance value of the third resistor R3 can be adjusted at the initial stage of design, thereby adjusting the voltage output from the voltage output terminal 11a of the bias circuit 11.
In the embodiment of the invention, when the connector is the USB Type-C connector, the connector can be used as a master device and a slave device. When an interface contact CC _ Conn of the connector is connected with external equipment, if a logic detection pin CC _ CPU of the connector detects a high-level signal and the interface contact CC _ Conn of the connector detects a low-level signal, the equipment type of the connector is master equipment, and the equipment type of the external equipment is slave equipment; if the logic detection pin CC _ CPU of the connector detects a low level signal and the interface contact CC _ Conn of the connector detects a high level signal, the device type of the connector is a slave device, and the device type of the external device is a master device.
When the connector is used as a master device and the external device is used as a slave device, the connector can realize normal communication between the connector and the external device through the circuit. However, when the connector is a slave and the external device is a master, the fet 12 operates in the off state due to the high voltage at the source S and the high voltage at the drain of the fet 12. Therefore, in order to ensure normal communication between the connector and the external device when the connector is used as a slave device and the external device is used as a master device, as shown in fig. 1, the level shift circuit 1 further includes a first diode D1; the cathode of the first diode D1 is electrically connected to the drain D of the fet 12, and the anode of the first diode D1 is electrically connected to the source S of the fet 12.
Based on the above arrangement, when the voltage of the source S of the fet 12 is higher than that of the drain, the first diode D1 is turned on, and at this time, the interface contact CC _ Conn of the connector, the first diode D1, and the logic detection pin CC _ CPU of the connector are turned on, thereby achieving normal communication with the connector as a slave and the external device as a master.
It should be noted that, when the connector is a USB Type-C connector, the logic detection pin CC _ CPU of the connector detects that the level signal is a square wave signal with high and low pulses, and the period may be 50 to 100 milliseconds. As shown in fig. 2, the high level signal of the square wave signal is 5 volts, the low level signal is 0 volts, and the period is 100 milliseconds.
In an embodiment of the invention, the voltage value of the first power source V1 may be 3 volts, the resistance value of the second resistor R2 may be 200 kohms, the resistance value of the third resistor R3 may be 100 kohms, and the resistance value of the first resistor R1 may be 10 kohms. At the moment of system power-on, the window comparator circuit 2 controls the triode 13 to work in a conducting state, and meanwhile, the voltage output end 11a of the bias circuit 11 can output 1V voltage so as to control the field-effect tube 12 to work in an amplifying state and control the field-effect tube 12 to have certain conducting resistance.
When the external device does not access the interface contact CC _ Conn of the connector, if the level signal detected by the logic detection pin CC _ CPU of the connector is 5v, the logic detection pin CC _ CPU, the fet 12 and the first resistor R1 of the connector are turned on, and then the 5v level signal detected by the logic detection pin CC _ CPU of the connector is divided by the fet 12 and the first resistor R1, so that the voltage of the source S of the fet 12, that is, the voltage of the interface contact CC _ Conn of the connector is 1.2 v. Further, the window comparison circuit 2 controls the triode 13 to be kept in a conducting state based on the 1.2 volt voltage of the source electrode S of the field effect tube 12, so that the voltage of the source electrode S of the field effect tube 12 is kept to be 1.2 volts and is lower than the voltage 1.5 volts of the water vapor generating electrolytic reaction, and the water vapor generating electrolytic reaction of the interface contact CC _ Conn of the connector is avoided.
After the 5v level signal detected by the logic detection pin CC _ CPU of the connector is divided by the fet 12 and the first resistor R1, the current of the source S of the fet 12 is calculated by the following equations (1) and (2), and the voltage of the interface contact CC _ Conn of the connector is obtained by multiplying the resistance value of the current first resistor R1.
Wherein, in the above formula (1) and formula (2), V1 refers to the voltage value of the first power source V1; r2 is the resistance of the second resistor R2; r3 is the resistance of the third resistor R3; v. ofgsRefers to the voltage difference between the gate G and the source of the fet 12; i.e. idThe current value of the drain electrode D of the field effect tube 12; r1 is the resistance of the first resistor R1; i.e. iDSSIs the saturated leakage current value of the field effect transistor 12 and is based on the constant of the field effect transistor; v. ofTRefers to the turn-on voltage value of the fet 12, which is based on the fet's constant. In the embodiment of the invention, the value of v1 is 3V; r2 takes the value 200 kohms; r3 takes the value 100 kohms; r1 takes the value of 10 kilo ohms; i.e. iDSSIs 0.0768, vTIs 0.8.
When the external device is connected to the interface contact CC _ Conn of the connector, if the level signal detected by the logic detection pin CC _ CPU of the connector is a high level signal, the level signal detected by the interface contact CC _ Conn of the connector is a low level signal, that is, the level signal detected by the logic detection pin CC _ CPU of the connector is 5 volts, and the level signal detected by the interface contact CC _ Conn of the connector is 0 volt. At this time, the window comparison circuit 2 controls the triode 13 to be in a cut-off state based on the 0V voltage of the interface contact CC _ Conn of the connector, in addition, the logic detection pin CC _ CPU of the connector, the field effect transistor 12 and the interface contact CC _ Conn of the connector are conducted, the connector judges that the connector is a main device, the external device is a slave device, and normal communication between the connector and the external device is realized.
If the level signal detected by the logic detection pin CC _ CPU of the connector and the level signal detected by the interface contact CC _ Conn of the connector are both high level signals, that is, the level signal detected by the logic detection pin CC _ CPU of the connector and the level signal detected by the interface contact CC _ Conn of the connector are both 5 volts. At this time, the window comparison circuit 2 controls the triode 13 to be in a cut-off state based on the 5v voltage of the interface contact point CC _ Conn of the connector, and in addition, since the level signal detected by the logic detection pin CC _ CPU of the connector and the level signal detected by the interface contact point CC _ Conn of the connector are both high level signals, the connector judges as an invalid identification state.
If the level signal detected by the logic detection pin CC _ CPU of the connector and the level signal detected by the interface contact CC _ Conn of the connector are both low level signals, that is, the level signal detected by the logic detection pin CC _ CPU of the connector and the level signal detected by the interface contact CC _ Conn of the connector are both 0 v. At this time, the window comparison circuit 2 controls the triode 13 to be in a cut-off state based on the 0 v voltage of the interface contact point CC _ Conn of the connector, and in addition, since the level signal detected by the logic detection pin CC _ CPU of the connector and the level signal detected by the interface contact point CC _ Conn of the connector are both low level signals, the connector judges as an invalid identification state.
If the level signal detected by the logic detection pin CC _ CPU of the connector is a low level signal, the level signal detected by the interface contact CC _ Conn of the connector is a high level signal, that is, the level signal detected by the logic detection pin CC _ CPU of the connector is 0 v, and the level signal detected by the interface contact CC _ Conn of the connector is 5 v. At this time, the window comparison circuit 2 controls the triode 13 to be in a cut-off state based on the 5v voltage of the interface contact CC _ Conn of the connector, in addition, the interface contact CC _ Conn of the connector, the first diode D1 and the logic detection pin CC _ CPU of the connector are conducted, the connector judges that the connector is a slave device, the external device is a master device, and normal communication between the connector and the external device is realized.
It should be noted that, when a pull-up resistor of 56 kohm, 22 kohm or 10 kohm is integrated in an internal circuit of the external device, the level signal detected by the interface contact CC _ Conn of the connector is a high level signal; when the internal circuit of the external device is integrated with a pull-down resistor of 5.1 kilo ohms or 1 kilo ohms, the level signal detected by the interface contact CC _ Conn of the connector is a low level signal.
In the embodiment of the present invention, when the transistor 13 is controlled by the window comparator circuit 2 to operate in the on or off state, as shown in fig. 3, the window comparator circuit 2 includes a second power source V2, a voltage divider circuit 21, a first voltage comparator 22, a second voltage comparator 23, a second diode D2, a third diode D3, and a pull-up circuit 24; a first voltage output end 21a of the voltage division circuit 21 is electrically connected with a non-inverting input end of the first voltage comparator 22, and a second voltage output end 21b of the voltage division circuit 21 is electrically connected with an inverting input end of the second voltage comparator 23; an inverting input end of the first voltage comparator 22 and a non-inverting input end of the second voltage comparator 23 are electrically connected with the output end 1a of the level shift circuit 1, a positive power source end of the first voltage comparator 22 and a positive power source end of the second voltage comparator 23 are electrically connected with the second power source V2, a negative power source end of the first voltage comparator 22 and a negative power source end of the second voltage comparator 23 are grounded, an output end of the first voltage comparator 22 is electrically connected with a negative electrode of the second diode D2, and an output end of the second voltage comparator 23 is electrically connected with a negative electrode of the third diode D3; the output terminal 24a of the pull-up circuit 24 is electrically connected to the anode of the second diode D2, the anode of the third diode D3, and the control terminal 1b of the level shifter circuit 1, respectively.
When the external device is not connected to the interface contact CC _ Conn of the connector, the voltage of the source S of the fet 12 is smaller than the voltage of the first voltage output terminal 21a of the voltage divider 21 and larger than the voltage of the second voltage output terminal 21b of the voltage divider 21, at this time, the first voltage comparator 22 and the second voltage comparator 23 both output high level signals, and the second diode D2 and the third diode D3 both are in an off state. In this way, the output terminal 24a of the pull-up circuit 24 can output a high level signal, and since the output terminal 24a of the pull-up circuit 24 is electrically connected to the base b of the transistor 13, the transistor 13 can be controlled to be in a conducting state.
When the external device is connected to the interface contact CC _ Conn of the connector, if the voltage of the source S of the fet 12 is greater than the voltage of the first voltage output terminal 21a of the voltage divider 21, the voltage of the source S of the fet 12 is certainly greater than the voltage of the second voltage output terminal 21b of the voltage divider 21, and at this time, the first voltage comparator 22 outputs a low level signal, and the second voltage comparator 23 outputs a high level signal. When the first voltage comparator 22 outputs a low level signal and the second voltage comparator 23 outputs a high level signal, the second transistor 13 is in a conducting state and the third diode D3 is in a blocking state. Thus, the output terminals of pull-up circuit 24, second diode D2 and first voltage comparator 22 are turned on, so that output terminal 24a of pull-up circuit 24 outputs a low level signal, thereby controlling transistor 13 to be in an off state.
If the voltage of the source S of the fet 12 is lower than the voltage of the second voltage output terminal 21b of the voltage divider 21, the voltage of the source S of the fet 12 must be lower than the voltage of the first voltage output terminal 21a of the voltage divider 21, and at this time, the first voltage comparator 22 outputs a high level signal and the second voltage comparator 23 outputs a low level signal. When the first voltage comparator 22 outputs a high level signal and the second voltage comparator 23 outputs a low level signal, the second transistor 13 is in a cut-off state, and the third diode D3 is in a conducting state. Thus, the output terminals of pull-up circuit 24, third diode D3 and second voltage comparator 23 are turned on, so that output terminal 24a of pull-up circuit 24 outputs a low level signal, and transistor 13 is controlled to be in the off state.
As shown in fig. 3, the voltage divider circuit 21 may include a third power source V3, and a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6 connected in series between the third power source V3 and the ground, wherein the first voltage output terminal 21a of the voltage divider circuit 21 is a common terminal of the fourth resistor R4 and the fifth resistor R5, and the second voltage output terminal 21b of the voltage divider circuit 21 is a common terminal of the fifth resistor R5 and the sixth resistor R6. The pull-up circuit 24 may include a fourth power source V4, and a seventh resistor R7 connected in series between the fourth power source V4 and the anode of the second diode D2.
In the embodiment of the present invention, the voltage values of the second power source V2 and the fourth power source V4 are equal and may both be 5 volts, the voltage value of the third power source V3 may be 3 volts, the resistance value of the fourth resistor R4 may be 100 kohms, the resistance value of the fifth resistor R5 may be 120 kohms, the resistance value of the sixth resistor R6 may be 80 kohms, and the resistance value of the seventh resistor R7 may be 100 kohms. The first voltage output terminal 21a of the voltage divider circuit 21 may output a voltage of 2 v, and the second voltage output terminal 21b may output a voltage of 0.8 v.
When the interface contact CC _ Conn of the connector is not connected to an external device, when the 1.2 v voltage of the source S of the fet 12 is output to the inverting input terminal of the first voltage comparator 22 and the inverting input terminal of the second voltage comparator 23, respectively, and the 2 v voltage of the first voltage output terminal 21a and the 0.8 v voltage of the second output terminal of the voltage divider circuit 21 are output to the inverting input terminal of the first voltage comparator 22 and the inverting input terminal of the second voltage comparator 23, respectively, since the 2 v voltage of the non-inverting input terminal of the first voltage comparator 22 is higher than the 1.2 v voltage of the inverting input terminal, and the 1.2 v voltage of the non-inverting input terminal of the second voltage comparator 23 is higher than the 0.8 v voltage of the inverting input terminal, both the first voltage comparator 22 and the second voltage comparator 23 output high level signals. At this time, the second diode D2 and the third diode D3 are both in the off state, so that the output terminal of the pull-up resistor can output a high level signal, thereby controlling the transistor 13 to operate in the on state.
When the interface contact CC _ Conn of the connector is not connected to an external device, the voltage of the source S of the fet 12 may be 0 v or 5 v. If the voltage of the source S of the fet 12 is 0 v, the voltage of 0 v of the source S of the fet 12 is output to the inverting input terminal of the first voltage comparator 22 and the inverting input terminal of the second voltage comparator 23, respectively, and the voltage of 2 v of the first voltage output terminal 21a and the voltage of 0.8 v of the second output terminal of the voltage divider circuit 21 are output to the inverting input terminal of the first voltage comparator 22 and the inverting input terminal of the second voltage comparator 23, respectively, since the voltage of 2 v of the non-inverting input terminal of the first voltage comparator 22 is higher than the voltage of 0 v of the inverting input terminal, and the voltage of 0 v of the non-inverting input terminal of the second voltage comparator 23 is lower than the voltage of 0.8 v of the inverting input terminal, the first voltage comparator 22 outputs a high level signal, and the second voltage comparator 23 outputs a low level signal. At this time, the second diode D2 is operated in an off state, and the third diode D3 is operated in an on state, so that the output terminal of the pull-up resistor can output a low level signal, thereby controlling the transistor 13 to be operated in the off state.
If the voltage of the source S of the fet 12 is 5v, the voltage of 5v of the source S of the fet 12 is output to the inverting input terminal of the first voltage comparator 22 and the inverting input terminal of the second voltage comparator 23, respectively, and the voltage of 2 v of the first voltage output terminal 21a and the voltage of 0.8 v of the second output terminal of the voltage divider circuit 21 are output to the inverting input terminal of the first voltage comparator 22 and the inverting input terminal of the second voltage comparator 23, respectively, since the voltage of 2 v of the non-inverting input terminal of the first voltage comparator 22 is lower than the voltage of 5v of the inverting input terminal, and the voltage of 5v of the non-inverting input terminal of the second voltage comparator 23 is higher than the voltage of 0.8 v of the inverting input terminal, the first voltage comparator 22 outputs a low level signal, and the second voltage comparator 23 outputs a high level signal. At this time, the second diode D2 is operated in a turn-on state, and the third diode D3 is operated in a turn-off state, so that the output terminal of the pull-up resistor can output a low level signal, thereby controlling the transistor 13 to be operated in a turn-off state.
In the embodiment of the invention, at the moment of powering on the system, the window comparison circuit controls the triode to work in a conducting state, and simultaneously, the voltage output by the voltage output end of the biasing circuit controls the field effect transistor to work in an amplifying state and controls the field effect transistor to have certain conducting resistance. When the external equipment is not connected with the connected interface contact, the triode is controlled to work in a conducting state by the high level signal output by the window comparison circuit, and at the moment, the level signal detected by the logic detection pin of the connector is subjected to voltage division processing through the field effect transistor and the first resistor, so that the voltage of the interface contact of the connector is lower than the voltage of the electrolytic reaction generated by water vapor, and the interface contact of the connector is prevented from being damaged. When the external equipment is connected to the interface contact of the connector, the window comparison circuit outputs a low level signal based on the level signal detected by the interface contact of the connector so as to control the triode to work in a cut-off state, and at the moment, the logic detection pin of the connector, the field effect transistor and the interface contact of the connector are conducted, so that the identification of the equipment type of the external equipment is realized.
The embodiment of the invention also provides an electronic device, which is provided with a connector, wherein the connector is provided with the interface circuit in the embodiment, so that the problem of subsequent poor contact caused by hydrolysis reaction of the interface circuit of the connector of the electronic device when the electronic device is not accessed into the external equipment is avoided, and meanwhile, the equipment type of the external equipment is normally identified when the external equipment is accessed into the electronic device.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. An interface circuit for a connector, the interface circuit comprising: a level shift circuit (1) and a window comparison circuit (2);
the level shift circuit (1) comprises a bias circuit (11), a field effect transistor (12), a triode (13) and a first resistor (R1), wherein a grid (G) of the field effect transistor (12) is electrically connected with a voltage output end (11a) of the bias circuit (11), a drain (D) of the field effect transistor (12) is electrically connected with a logic detection pin (CC _ CPU) of the connector, a source (S) of the field effect transistor (12) is respectively electrically connected with an interface contact (CC _ Conn) of the connector, a collector (c) of the triode (13) and an input end (2a) of the window comparison circuit (2), a base (b) of the triode (13) is electrically connected with a control end (2b) of the window comparison circuit (2), and the first resistor (R1) is connected between an emitter (e) of the triode (13) and the ground in series, and the grounding end of the level shift circuit (1) and the grounding end of the window comparison circuit (2) are grounded.
2. Interface circuit according to claim 1, characterized in that the bias circuit (11) comprises a first power supply (V1), and a second resistor (R2) and a third resistor (R3) connected in series between the first power supply (V1) and ground, the voltage output (11a) of the bias circuit (11) being a common terminal of the second resistor (R2) and the third resistor (R3).
3. Interface circuit as claimed in claim 1, characterized in that the level shifter circuit (1) further comprises a first diode (D1);
the cathode of the first diode (D1) is electrically connected with the drain electrode (D) of the field effect tube (12), and the anode of the first diode (D1) is electrically connected with the source electrode (S) of the field effect tube (12).
4. The interface circuit according to claim 1, wherein the window comparison circuit (2) comprises a second power supply (V2), a voltage divider circuit (21), a first voltage comparator (22), a second voltage comparator (23), a second diode (D2), a third diode (D3), and a pull-up circuit (24);
a first voltage output end (21a) of the voltage division circuit (21) is electrically connected with a non-inverting input end of the first voltage comparator (22), and a second voltage output end (21b) of the voltage division circuit (21) is electrically connected with an inverting input end of the second voltage comparator (23);
the inverting input end of the first voltage comparator (22) and the non-inverting input end of the second voltage comparator (23) are respectively and electrically connected with the output end (1a) of the level shift circuit (1), the positive power end of the first voltage comparator (22) and the positive power end of the second voltage comparator (23) are respectively and electrically connected with the second power supply (V2), the negative power end of the first voltage comparator (22) and the negative power end of the second voltage comparator (23) are respectively and electrically connected with the ground, the output end of the first voltage comparator (22) is electrically connected with the negative electrode of the second diode (D2), and the output end of the second voltage comparator (23) is electrically connected with the negative electrode of the third diode (D3);
an output end (24a) of the pull-up circuit (24) is electrically connected with the anode of the second diode (D2), the anode of the third diode (D3) and the control end (1b) of the level shift circuit (1) respectively.
5. The interface circuit according to claim 4, wherein the voltage divider circuit (21) comprises a third power supply (V3), and a fourth resistor (R4), a fifth resistor (R5) and a sixth resistor (R6) connected in series between the third power supply (V3) and ground, wherein the first voltage output terminal (21a) of the voltage divider circuit (21) is a common terminal of the fourth resistor (R4) and the fifth resistor (R5), and wherein the second voltage output terminal (21b) of the voltage divider circuit (21) is a common terminal of the fifth resistor (R5) and the sixth resistor (R6).
6. The interface circuit of claim 4, wherein the pull-up circuit (24) includes a fourth power supply (V4), and a seventh resistor (R7) connected in series between the fourth power supply (V4) and the anode of the second diode (D2).
7. Interface circuit according to claim 4, characterized in that when no external device is connected to the interface contact (CC _ Conn) of the connector, the voltage of the source (S) of the FET (12) is lower than the voltage of the first voltage output (21a) of the voltage divider circuit (21) and higher than the voltage of the second voltage output (21b) of the voltage divider circuit (21), the output (24a) of the pull-up circuit (24) outputting a high signal;
when an external device is connected to the interface contact (CC _ Conn) of the connector, the voltage of the source (S) of the field effect transistor (12) is larger than the voltage of the first voltage output end (21a) of the voltage division circuit (21) or smaller than the voltage of the second voltage output end (21b) of the voltage division circuit (21), and the output end (24a) of the pull-up circuit (24) outputs a low-level signal.
8. Interface circuit according to claim 1, characterized in that said field effect transistor (12) is an N-type metal-oxide-semiconductor NMOS type field effect transistor and said transistor (13) is an NPN type transistor.
9. The interface circuit of claim 2, wherein the second resistor (R2) and the third resistor (R3) are variable resistors.
10. An electronic device, characterized in that the electronic device is provided with a connector provided with an interface circuit according to any of claims 1-9.
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| CN201811093035.9A CN110932712B (en) | 2018-09-19 | 2018-09-19 | Interface circuit of connector and electronic device |
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| CN110932712B (en) | 2023-05-05 |
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