CN110931360A - Preparation method of power device with terminal protection structure - Google Patents
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- CN110931360A CN110931360A CN201911024199.0A CN201911024199A CN110931360A CN 110931360 A CN110931360 A CN 110931360A CN 201911024199 A CN201911024199 A CN 201911024199A CN 110931360 A CN110931360 A CN 110931360A
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- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000002513 implantation Methods 0.000 claims description 11
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 7
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- 238000001459 lithography Methods 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000010992 reflux Methods 0.000 claims description 3
- 238000003491 array Methods 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 2
- 230000035945 sensitivity Effects 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
The invention provides a method for preparing a power device with a terminal protection structure, wherein a central active region of the device consists of single cell arrays connected in parallel, a terminal protection region is arranged at the periphery of the central active region, a terminal protection ring is arranged in the terminal protection region, and a P well strip is inserted between adjacent terminal protection rings. The power device adopts the field limiting ring combined with the protection ring structure of the P well strip, can improve the terminal protection efficiency, and reduces the occupied area of the terminal structure of the device, thereby reducing the manufacturing cost of the device, improving the yield and improving the sensitivity of the device to parasitic charges.
Description
Technical Field
The invention relates to a power device, in particular to a power device with a terminal protection structure.
Background
The power devices are developed in the direction of increasing power and increasing the operating voltage and current of the devices, and therefore, higher and higher requirements are put on the voltage resistance of the devices.
The terminal structure is one of the most core technologies in the power device, and the quality of the terminal structure directly affects the highest working voltage, the magnitude of leakage current, the reliability and the stability of the power device. In the semiconductor device planar process, the maximum electric field of the surface is always larger than that of the bulk due to the curvature of the PN junction on the surface, the withstand voltage of the device is often determined by surface breakdown, and when impact ionization occurs on the surface, hot carriers generated in the ionization process easily enter silicon dioxide to form fixed charges, so that the electric field distribution is changed, the performance of the device is unstable, and the reliability is reduced. Therefore, for the device which needs to bear high voltage, some special measures, namely a junction termination technology, need to be taken to improve the surface structure, so as to reduce the surface electric field, prevent the surface breakdown and improve the breakdown voltage of the power device.
The terminal protection structure of the existing power device (taking an N-type power MOS device as an example, other power devices such as IGBTs and the like) usually adopts a field limiting ring protection structure, and the power MOS device manufactured according to the requirement has the advantages that the design of the protection ring becomes more complicated when the power device manufacturing method with the terminal protection structure is manufactured, the terminal efficiency is reduced, the occupied area is greatly increased, and how to design the terminal structure of the power device manufacturing method with the terminal protection structure to improve the efficiency and the reliability is the content of the important research of the invention.
Disclosure of Invention
The invention aims to provide a method for preparing a power device with a terminal protection structure aiming at the problem of optimization of the terminal structure of the power device.
The technical scheme of the invention is as follows:
the invention provides a preparation method of a power device with a terminal protection structure, which comprises the following steps:
s1, growing a wet oxygen oxide layer;
s2, injecting and propelling a terminal protection ring to generate a field oxide layer;
s3, carrying out photoetching on the active region, and then carrying out etching on the active region by using wet etching;
s4, further adopting wet oxygen oxidation to grow a gate oxide layer, and then depositing a polysilicon layer;
s5, etching the polysilicon layer, and injecting and propelling the P well region;
s6, etching between adjacent terminal protection rings to form a P well strip injection window, and injecting and propelling the P well strip;
s7, injecting and propelling the N + source region of the power MOSFET;
s8, depositing TEOS and BPSG by LPCVD; carrying out reflux and finishing photoetching and etching of the hole; injecting and propelling a P + concentrated boron region of the power MOSFET;
s9, sputtering a metal aluminum layer; photoetching and etching metal, and PECVD depositing Si3N4Layer, lithography and etching of Si3N4And thinning and back metallization to finish the manufacture.
Further, in step S1, the temperature of wet oxygen oxidation is 800-.
Further, in step S2, the implantation energy of the terminal guard ring is 80KeV, and the dose is 5E14cm-2The advancing temperature is 800-.
Further, in step S4, the thickness of the gate oxide layer is 700-800A, and the thickness of the polysilicon layer is 6000A-10000A.
Further, in step S5, the P-well region is implanted with an energy of 80KeV and a dose of 6E13cm-2(ii) a The propulsion temperature is 1000 ℃ and the time is 150-.
Further, in step S6, the implantation dose of the P-well stripe 2E11 is advanced at a temperature of 800-1000 ℃ for 70-90 minutes.
Further, in step S7, the implantation energy of the N + source region is 80KeV, and the dosage is 1.2E16cm-2(ii) a The propelling was carried out at a propelling temperature of 900 ℃ for 150 minutes.
Further, in step S8, the thickness of the deposited TEOS layer is 1500-; the thickness of the BPSG layer is 7500-8000A; the implantation energy of the P + concentrated boron region is 100- & lt 110 & gtKeV, and the dosage is 2E15cm-2The advancing temperature is 800-900 ℃, the time is 100 minutes, and the thickness of the sputtered metal aluminum layer is 4-5 microns.
Furthermore, the number of the terminal protection rings is two, and the terminal protection rings are sequentially arranged from the central active area to the periphery; the terminal protection ring adopts an annular groove polysilicon array.
Furthermore, the number of the P well strips is multiple, and the P well strips are arranged in the direction perpendicular to the terminal protection ring.
Further, the distance between adjacent P well strips is 0.5um-3 um; the width of the P-well stripes ranges from 0.5um to 3 um.
The invention has the beneficial effects that:
compared with the prior art, the invention has the following innovation and advantages:
the invention adopts the protection structure of inserting the P well strip between the adjacent field limiting rings, so that the terminal protection efficiency of the device is improved, the area of the terminal structure is reduced, and the manufacturing cost of the device is reduced.
The invention improves the terminal protection efficiency by inserting the structure of the P well strip between the protection rings, reduces the occupied area of the terminal structure of the device, thereby reducing the manufacturing cost of the device, improving the yield and improving the sensitivity of the device to parasitic charges.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail exemplary embodiments thereof with reference to the attached drawings, in which like reference numerals generally represent like parts throughout.
FIG. 1 is a schematic diagram of a power MOS device with field limiting ring termination having P-well stripes according to the present invention;
FIG. 2 is a schematic structural view of section A-A' of FIG. 1;
FIG. 3 is a schematic structural view of the section B-B' in FIG. 1;
in the figure: 1. an N + substrate; 2. an N-type epitaxial layer; 3. a terminal protection ring; 4. a field oxide layer; 5. polycrystalline silicon; 6. a gate oxide layer; 7. a P well region; 8. an N + source region; 9. a P + concentrated boron region; 10. a dielectric layer; 11. a front metal layer; 12. a back metal layer; 13. and P well strips.
Detailed Description
Preferred embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein.
A preparation method of a power device with a terminal protection structure comprises the following steps:
s1, growing a wet oxygen oxidation layer, wherein the wet oxygen oxidation temperature is 800-900 ℃, and the growth thickness of the oxidation layer is 500A;
s2, implanting the terminal guard ring 3 with an implantation energy of 80KeV and a dose of 5E14cm-2(ii) a Advancing to generate a field oxide layer, wherein the advancing temperature is 800-;
s3, carrying out photoetching on the active region, and then carrying out etching on the active region by using wet etching;
s4, further adopting wet oxygen oxidation to grow a gate oxide layer 6, and then depositing a polycrystalline silicon layer 5; the thickness of the gate oxide layer 6 is 700-800A, and the thickness of the polysilicon layer 5 is 6000-10000A;
s5, etching the polysilicon layer 5, and injecting and propelling the P well region 7; implantation energy of 80KeV and dose of 6E13cm for P-well region 7-2(ii) a The propulsion temperature is 1000 ℃, and the time is 150 ℃ and 180 minutes;
s6, etching between adjacent terminal guard rings 3 to form an injection window of the P well stripe 13, and injecting and propelling the P well stripe 13, wherein the injection dosage of the P well stripe 13 is 2E11, the propelling temperature is 800-;
s7, injecting and propelling the N + source region 8 of the power MOSFET; implantation energy of 80KeV for N + source region 8, and dose of 1.2E16cm-2(ii) a The propelling was carried out at a propelling temperature of 900 ℃ for 150 minutes.
S8, depositing TEOS and BPSG by LPCVD, wherein the thickness of the deposited TEOS layer is 1500-1800A; the thickness of the BPSG layer is 7500-8000A; carrying out reflux and finishing photoetching and etching of the hole; injecting and propelling a P + concentrated boron region 9 of the power MOSFET;the implantation energy of the P + concentrated boron region 9 is 100- & lt 110 & gtKeV, and the dosage is 2E15cm-2The propelling temperature is 800-;
s9, sputtering a metal aluminum layer with the thickness of 4-5 microns; photoetching and etching metal, and PECVD depositing Si3N4Layer, lithography and etching of Si3N4And thinning and back metallization to finish the manufacture.
Furthermore, the number of the terminal protection rings 3 is two, and the terminal protection rings are sequentially arranged from the central active area to the periphery; the terminal guard ring 3 adopts an annular groove polysilicon array.
Furthermore, a plurality of P-well stripes 13 are arranged in a direction perpendicular to the terminal guard ring 3; the distance between the adjacent P well strips 13 is 0.5um-3 um; the width of the P-well stripes 13 ranges from 0.5um to 3 um.
As shown in fig. 1, it can be seen that the MOS central active region is composed of parallel unit cell arrays, and the periphery of the unit cell arrays is provided with a terminal protection structure. The unit cell array is formed into a whole by connecting polycrystalline silicon 5 in parallel, a terminal protection area is arranged on the periphery of the central active area, a terminal protection ring 3 is arranged in the terminal protection area, and a P well strip 13 is inserted between adjacent terminal protection rings 3; the number of the terminal protection rings is at least 2, the number of the terminal protection rings can be more, P well strips 13 in the vertical direction are inserted between every two adjacent protection rings, and the terminal protection rings are sequentially arranged from the central active region to the periphery; the terminal protection ring adopts a ring structure.
Example one
FIGS. 2 and 3 are sectional views A-A 'and B-B', respectively. The invention discloses an embodiment of manufacturing the N-type power MOS, which comprises the following steps:
preparation: the power MOSFET process is prepared as usual, for example: oxidizing and growing about 500A of pre-oxidation by using wet oxygen at 850 ℃, and then photoetching and etching the terminal ring; with energy 80KeV, dose 5E14cm-2Injecting a terminal protection ring, propelling the terminal protection ring at 900 ℃, and generating an oxide layer with the thickness of 12000A while propelling the terminal protection ring; photoetching an active region, and etching the active region by wet etching; growing gate oxide of about 800A by wet oxidation, and depositing a polysilicon layer by LPCVD to a thickness of 7000A; in the process of polysilicon etchingThereafter, by implantation and advancement of the P-well layer, e.g. with an energy of 80KeV, dose 6E13cm-2Injecting a P well layer, and then propelling at 1000 ℃ for 160 minutes; etching to form a P well strip injection window, and injecting and propelling the P well strip, wherein the injection dosage is 2E11, the propelling temperature is 1000 ℃, and the propelling time is 90 minutes; power MOSFET source N + implant and drive-in are then performed, for example, with an energy of 80KeV, dose 1.2E16cm-2Carrying out power MOSFET source electrode N +, and then carrying out propelling at 900 ℃ for 150 minutes; LPCVD deposition of TEOS and BPSG, respectively 1800A and 7500A in thickness, reflow at 900 ℃ and complete photolithography and etching of the holes, with an energy of 120KeV, dose 2E15cm-2Injecting P + of power MOSFET, advancing at 900 deg.C for 100 min, sputtering metallic aluminum to 4-5 μm thickness, photoetching and etching, and PECVD depositing Si3N4Lithography and etching of Si3N4And thinning and back metallization to finish the manufacture.
According to the invention, through the reasonable design of the junction terminal structure, the area of the terminal is reduced and the manufacturing cost is reduced while the voltage resistance and the terminal reliability of the power device are improved.
Having described embodiments of the present invention, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.
Claims (11)
1. A preparation method of a power device with a terminal protection structure is characterized by comprising the following steps: it comprises the following steps:
s1, growing a wet oxygen oxide layer;
s2, injecting and advancing the terminal protection ring (3) to generate a field oxide layer (4);
s3, carrying out photoetching on the active region, and then carrying out etching on the active region by using wet etching;
s4, further adopting wet oxygen oxidation to grow a gate oxide layer (6), and then depositing a polycrystalline silicon layer (5);
s5, etching the polysilicon layer (5), and injecting and propelling the P well region (7);
s6, etching between adjacent terminal guard rings (3) to form a P well bar (13) injection window, and injecting and propelling the P well bar (13);
s7, injecting and advancing an N + source region (8) of the power MOSFET;
s8, depositing TEOS and BPSG by LPCVD; carrying out reflux and finishing photoetching and etching of the hole; injecting and propelling a P + concentrated boron region (9) of the power MOSFET;
s9, sputtering a metal aluminum layer; photoetching and etching metal, and PECVD depositing Si3N4Layer, lithography and etching of Si3N4And thinning and back metallization to finish the manufacture.
2. The method for manufacturing a power device with a terminal protection structure according to claim 1, wherein: in step S1, the temperature of wet oxygen oxidation is 800-900 deg.C, and the thickness of the oxide layer is 500A.
3. The method for manufacturing a power device with a terminal protection structure according to claim 1, wherein: in step S2, the terminal guard ring (3) is implanted with an energy of 80KeV and a dose of 5E14cm-2The advancing temperature is 800-.
4. The method for manufacturing a power device with a terminal protection structure according to claim 1, wherein: in step S4, the thickness of the gate oxide layer (6) is 700-800A, and the thickness of the polysilicon layer (5) is 6000-10000A.
5. The method for manufacturing a power device with a terminal protection structure according to claim 1, wherein: in step S5, the P well region (7) is implanted with an energy of 80KeV and a dose of 6E13cm-2(ii) a The propulsion temperature is 1000 ℃ and the time is 150-.
6. The method for manufacturing a power device with a terminal protection structure according to claim 1, wherein: in step S6, the P-well stripe (13) is implanted with the dose 2E11 at a drive-in temperature of 800-1000 ℃ for 70-90 minutes.
7. The method for manufacturing a power device with a terminal protection structure according to claim 1, wherein: in step S7, the implantation energy of the N + source region (8) is 80KeV, and the dose is 1.2E16cm-2(ii) a The propelling was carried out at a propelling temperature of 900 ℃ for 150 minutes.
8. The method for manufacturing a power device with a terminal protection structure according to claim 1, wherein: in step S8, the thickness of the deposited TEOS layer is 1500-1800A; the thickness of the BPSG layer is 7500-8000A; the implantation energy of the P + concentrated boron region (9) is 100-110KeV, and the dosage is 2E15cm-2The advancing temperature is 800-900 ℃, the time is 100 minutes, and the thickness of the sputtered metal aluminum layer is 4-5 microns.
9. The method for manufacturing a power device with a terminal protection structure according to claim 1, wherein: the number of the terminal protection rings (3) is two, and the terminal protection rings are arranged from the central active area to the periphery in sequence; the terminal protection ring (3) adopts an annular groove polysilicon array.
10. The method for manufacturing a power device with a terminal protection structure according to claim 1, wherein: the number of the P well strips (13) is multiple, and the P well strips are arranged in the direction perpendicular to the terminal protection ring (3).
11. The method for manufacturing a power device with a terminal protection structure according to claim 1, wherein: the distance between the adjacent P well strips (13) is 0.5um-3 um; the width of the P-well stripe (13) ranges from 0.5um to 3 um.
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| CN104377245A (en) * | 2014-11-26 | 2015-02-25 | 张家港凯思半导体有限公司 | Groove type MOS device and manufacturing method and terminal protecting structure thereof |
| CN105679810A (en) * | 2016-03-31 | 2016-06-15 | 无锡新洁能股份有限公司 | Semiconductor structure suitable for charge coupled device and manufacturing method of semiconductor structure |
| CN106252390A (en) * | 2016-09-19 | 2016-12-21 | 西安理工大学 | A kind of groove field limiting ring composite terminal structure and preparation method thereof |
| CN208706654U (en) * | 2018-09-11 | 2019-04-05 | 无锡新洁能股份有限公司 | A kind of SiC power device terminal |
| CN211125658U (en) * | 2019-10-10 | 2020-07-28 | 江苏东晨电子科技有限公司 | High-voltage power device |
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Patent Citations (5)
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|---|---|---|---|---|
| CN104377245A (en) * | 2014-11-26 | 2015-02-25 | 张家港凯思半导体有限公司 | Groove type MOS device and manufacturing method and terminal protecting structure thereof |
| CN105679810A (en) * | 2016-03-31 | 2016-06-15 | 无锡新洁能股份有限公司 | Semiconductor structure suitable for charge coupled device and manufacturing method of semiconductor structure |
| CN106252390A (en) * | 2016-09-19 | 2016-12-21 | 西安理工大学 | A kind of groove field limiting ring composite terminal structure and preparation method thereof |
| CN208706654U (en) * | 2018-09-11 | 2019-04-05 | 无锡新洁能股份有限公司 | A kind of SiC power device terminal |
| CN211125658U (en) * | 2019-10-10 | 2020-07-28 | 江苏东晨电子科技有限公司 | High-voltage power device |
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