CN110912432A - MMC capacitor voltage-sharing strategy with lower switching frequency and complexity - Google Patents
MMC capacitor voltage-sharing strategy with lower switching frequency and complexity Download PDFInfo
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- CN110912432A CN110912432A CN201811083276.5A CN201811083276A CN110912432A CN 110912432 A CN110912432 A CN 110912432A CN 201811083276 A CN201811083276 A CN 201811083276A CN 110912432 A CN110912432 A CN 110912432A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/36—Arrangements for transfer of electric power between ac networks via a high-tension dc link
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/4835—Converters with outputs that each can have more than two voltages levels comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/60—Arrangements for transfer of electric power between AC networks or generators via a high voltage DC link [HVCD]
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- Engineering & Computer Science (AREA)
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- Inverter Devices (AREA)
Abstract
The invention provides an MMC capacitor voltage-sharing strategy with lower switching frequency and complexity, which comprises the following steps of S1: rapidly monitoring the voltage value of each sub-module capacitor; step S2: determining the number of the added and cut-off submodules, and judging the charging and discharging conditions of the added submodules in the bridge arm; step S3: delaying the sequencing result of the previous period, and grouping the sub-modules in the switching-in state and the switching-off state to perform insertion sequencing correction of limited step number, wherein the step number is determined by the maximum voltage difference, and the larger the difference is, the more the step number is; step S4: introducing a retention factor to the capacitor voltage of the corresponding sub-module according to the charging and discharging conditions; step S5: merging the two subsequences in the input and cut states by adopting 2 paths, updating and recording the sequencing result; step S6: a trigger pulse is generated. The invention realizes double optimization of the operation speed of the sorting algorithm and the switching frequency of the device, and solves the problems of large operation amount of the sorting algorithm and higher switching frequency of the device in the traditional submodule capacitor voltage-sharing strategy.
Description
Technical Field
The invention relates to an MMC capacitor voltage-sharing strategy with lower switching frequency and complexity, and belongs to the technical field of electric power.
Background
The Modular Multilevel Converter (MMC) is a core device of a flexible direct-current transmission technology, and the sub-module capacitor voltage-sharing problem of the MMC is one of the key problems of stable operation of a transmission system. In the traditional submodule capacitor voltage-sharing strategy, the operation amount of the sequencing algorithm is exponentially multiplied along with the number of the submodules. When the number of the sub-modules is large, the hardware design difficulty is large and the cost is high. Meanwhile, when the Modular Multilevel Converter (MMC) is applied to a flexible high-voltage direct-current transmission system, the converter valve has the characteristics of large quantity of power modules, large bridge arm current and the like, so that the converter valve is high in switching loss and difficult in heat dissipation of a switching device. The traditional sequencing voltage-sharing algorithm has the defects that the switching of a power module is a random process, the switching frequency is very high, and the actual engineering requirements are difficult to meet. Therefore, how to simultaneously increase the sorting speed and reduce the switching frequency of the device in the voltage-sharing process of the MMC capacitor is an urgent problem to be faced and solved.
Disclosure of Invention
In order to solve the problems of large operation amount of a sorting algorithm and high switching frequency of a device in the MMC capacitor voltage-sharing process, the invention provides a MMC submodule capacitor voltage optimization balance control strategy, which can reduce the sorting operation amount, maintain high efficiency, reduce the switching frequency of the device and reduce the switching loss.
The invention provides an MMC capacitor voltage-sharing strategy with lower switching frequency and complexity, which comprises the following steps:
step S1: rapidly monitoring the capacitance voltage value of each submodule in a bridge arm;
step S2: determining the number of the added and cut-off sub-modules, monitoring the current direction of each bridge arm, and judging the charging and discharging conditions of the bridge arm to the added sub-modules;
step S3: according to the sequencing result of the previous period, performing insertion sequencing correction of the limited step number on the sub-module groups in the input and cut-off states;
step S4: and if the bridge arm current enables the input sub-modules to be charged, multiplying the capacitance voltage of the sub-modules which are in the cutting-off state and the capacitance voltage of which is higher than the lower voltage limit by a holding factor which is slightly larger than 1 to obtain a new cutting-off sub-sequence. If the bridge arm current enables the input sub-modules to discharge, multiplying the capacitance voltage of the sub-modules which are in the input state and the capacitance voltage of which is higher than the lower voltage limit by a holding factor which is slightly larger than 1 to obtain a new input sub-sequence;
step S5: merging the two subsequences in the input and cut states by adopting 2 paths, updating and recording the sequencing result;
step S6: a trigger pulse is generated.
In the traditional capacitance voltage balance method, the voltage value of each sub-module capacitor is monitored firstly, and the sorting is carried out by adopting a bubbling method. When the bridge arm current is larger than zero, the bridge arm current charges the sub-module capacitors, and the sub-modules are put into the capacitor in the order from small to large according to the number of the sub-modules required to be put into the capacitor; and when the bridge arm current is less than zero, the sub-module capacitors are discharged, and the sub-modules are put into the sub-modules according to the number of the sub-modules required to be put into the bridge arm in the sequence from the large to the small of the sub-module capacitor voltage. When the traditional bubble sorting method is adopted, the sorting times required by each sorting of the bridge arms containing n submodules are as follows:
T0＝1+2+…+(n－1)＝n(n－1)/2
in the formula: t is0The number of sorting times at maximum temporal complexity.
In the invention, considering that the relative sequence of the capacitor voltages of the sub-modules in the input group and the cut-off group is basically unchanged in one period, the sequencing result of the previous period is used, the limited step number of the two sub-sequences is firstly corrected, and the corrected step number is the maximum capacitor voltage difference delta UCmaxAnd determining that the larger the difference value is, the more the steps are, finally performing 2-way merging and sorting on the two groups of corrected subsequences to obtain a new sequence, and compared with the traditional bubble sorting, the sorting frequency of the sorting method is obviously reduced.
The step of introducing the retention factor is to consider the requirement of reducing the switching frequency of the device, which is not considered by the traditional balance control method, and the switching of the sub-modules is only based on the capacitor voltage sequencing result and does not consider the initial switching state of the sub-modules. The conventional method aims at strictly controlling the difference between the capacitor voltages of the sub-modules. In practice, the aim of the balancing control is not to pursue a complete agreement of the capacitor voltages of the submodules, but rather to suppress the amplitude of the fluctuations of the capacitor voltages of the submodules with respect to their nominal values. Accordingly, a set of upper and lower voltage limits can be set near the rated value of the capacitor voltage, and the emphasis of the balance control is placed on the sub-modules with the out-of-limit capacitor voltage. And for the sub-modules with the capacitance and voltage not exceeding the limit, the capacitance and voltage of the sub-modules are processed by combining the charging and discharging conditions of the bridge arm current, and then the sub-modules are sequenced. The purpose of the processing is to increase the probability that the submodule without the out-of-limit capacitor voltage keeps the original switching state when the submodule is triggered to act next time so as to reduce the switching frequency of the device.
Advantageous effects
The invention provides an MMC capacitor voltage-sharing strategy with lower switching frequency and complexity, which can cope with application occasions with a large number of sub-modules, greatly reduces the calculation amount of capacitor voltage sequencing, and has high algorithm execution efficiency and high algorithm execution speed. Meanwhile, the invention puts the key point of balance control on the sub-modules with more deviation of the capacitor voltage from the rated value, and leads the other sub-modules to have certain capability of keeping the original switching state by introducing the retention factors so as to reduce the switching frequency of the power electronic device. In the MMC submodule capacitor voltage-sharing process, synchronous optimization of the operation speed of the sequencing algorithm and the switching frequency of a device is achieved, and the problems that the operation quantity of the sequencing algorithm is large and the switching frequency of the device is high in the traditional submodule capacitor voltage-sharing strategy are solved.
Drawings
FIG. 1 is a flow chart of an MMC capacitor voltage-sharing strategy (charging input) provided by the present invention;
FIG. 2 is a flowchart of an insertion sequencing of a limit number of steps;
fig. 3 is a 2-way merge flow diagram.
Detailed Description
In order to facilitate a better understanding of the contents of the inventive solution, it is further elucidated below with reference to specific examples. Fig. 1 is a flow chart of an MMC capacitor voltage-sharing strategy (charging), which is provided by the present invention, and the specific implementation steps are as follows:
step S1: quickly monitoring the capacitor voltage value of each submodule in the bridge arm, comparing the capacitor voltage value with the initially set upper limit and lower limit of the submodule, and calculating the maximum difference value delta U between the capacitor voltages of the submodulesCmaxFor determining the number of steps S in step S3;
step S2: determining the number of the added and cut-off sub-modules, monitoring the current direction of each bridge arm, and judging the charging and discharging conditions of the bridge arm to the added sub-modules;
step S3: considering that the relative sequence of the capacitor voltages of the sub-modules in the two groups of the sub-modules in the switching-in and switching-off state is basically unchanged in one period, and delaying the sequencing result of the previous period, the sub-sequence L of the sub-modules in the switching-in and switching-off state is obtained1 *、L2 *The packet is subjected to the step-limited direct insertion ordering correction as shown in FIG. 2 to obtain a new subsequence L1、L2Step number S is defined by the maximum difference value DeltaU between the sub-module capacitor voltagesCmaxDetermining that the larger the difference value is, the more the steps are;
step S4: through the charging and discharging conditions of the sub-modules put into the bridge arms determined in the step S2, a retention factor slightly larger than 1 is introduced to the capacitance voltage of the corresponding sub-module. If the bridge arm current charges the input sub-module, the capacitance voltage of the sub-module in the cutting state and the capacitance voltage of the sub-module is higher than the lower voltage limit is multiplied by a holding factor slightly larger than 1 to obtain a new cutting sub-sequence L3. If the bridge arm current discharges the input sub-modules, the capacitance voltage of the sub-modules which are in the input state and the capacitance voltage of which is higher than the lower voltage limit is multiplied by a holding factor which is slightly larger than 1 to obtain a new input sub-sequence L4；
Step S5: merging the two subsequences in the input and cut states by 2 ways as shown in figure 3, updating and recording the sequencing result to obtain a new input group subsequence L and a new cut group subsequence L1 *、L2 *；
Step S6: a trigger pulse is generated.
The above description is only exemplary of the present invention and should not be taken as limiting the invention, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (3)
1. MMC capacitor voltage-sharing strategy with lower switching frequency and complexity, its characterized in that includes:
step S1: rapidly monitoring the capacitance voltage value of each submodule in a bridge arm;
step S2: determining the number of the added and cut-off sub-modules, monitoring the current direction of each bridge arm, and judging the charging and discharging conditions of the bridge arm to the added sub-modules;
step S3: according to the sequencing result of the previous period, performing insertion sequencing correction of the limited step number on the sub-module groups in the input and cut-off states;
step S4: and if the bridge arm current enables the input sub-modules to be charged, multiplying the capacitance voltage of the sub-modules which are in the cutting-off state and the capacitance voltage of which is higher than the lower voltage limit by a holding factor which is slightly larger than 1 to obtain a new cutting-off sub-sequence. If the bridge arm current enables the input sub-modules to discharge, multiplying the capacitance voltage of the sub-modules which are in the input state and the capacitance voltage of which is higher than the lower voltage limit by a holding factor which is slightly larger than 1 to obtain a new input sub-sequence;
step S5: merging the two subsequences in the input and cut states by adopting 2 paths, updating and recording the sequencing result;
step S6: a trigger pulse is generated.
2. Method according to claim 1, characterized in that, considering that the relative order of the capacitor voltages of the sub-modules in the groups of inputs and outputs is substantially unchanged during a cycle, the defined number of steps of the correction is performed on the two sub-sequences, using the result of the ordering in the previous cycle, the number of steps of the correction being determined by the difference between the maximum capacitor voltages auCmaxAnd determining that the larger the difference value is, the more the steps are, finally performing 2-way merging and sorting on the two groups of corrected subsequences to obtain a new sequence, and reducing the time complexity of a sorting algorithm.
3. The method according to claim 2, characterized in that a retention factor is introduced on the basis of the optimization of the sequencing algorithm, so that the probability that the sub-modules with the capacitor voltage not exceeding the limit keep the original switching state when the sub-modules trigger the next action is increased to a certain extent, the complexity of the sequencing algorithm is reduced, and the switching frequency of the device is reduced.
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Cited By (3)
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| CN112600451A (en) * | 2020-11-17 | 2021-04-02 | 西安西电电力系统有限公司 | Flexible direct current converter valve power module capacitor voltage equalizing method |
| CN113162042A (en) * | 2021-05-08 | 2021-07-23 | 重庆大学 | MPPF capacitor failure evaluation method in MMC system based on frequency band energy |
| CN117977919A (en) * | 2024-03-29 | 2024-05-03 | 南昌工程学院 | High-frequency suppression method for modularized multi-level converter and flexible direct current transmission system |
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Cited By (5)
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| CN117977919B (en) * | 2024-03-29 | 2024-06-04 | 南昌工程学院 | High-frequency suppression method for modularized multi-level converter and flexible direct current transmission system |
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