CN105958850A - Optimized merging and sorting based modular multilevel converter capacitor voltage equalizing method - Google Patents
Optimized merging and sorting based modular multilevel converter capacitor voltage equalizing method Download PDFInfo
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- CN105958850A CN105958850A CN201610311275.6A CN201610311275A CN105958850A CN 105958850 A CN105958850 A CN 105958850A CN 201610311275 A CN201610311275 A CN 201610311275A CN 105958850 A CN105958850 A CN 105958850A
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- submodule
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/36—Arrangements for transfer of electric power between ac networks via a high-tension dc link
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Supply And Distribution Of Alternating Current (AREA)
Abstract
The invention provides an optimized merging and sorting based modular multilevel converter capacitor voltage equalizing method, which is characterized in that a merging and sorting algorithm is optimized through analyzing a capacitor voltage law of nearest level modulation in an ideal condition by using a modular multilevel converter modulation technology, the time complexity of optimized merging and sorting is further reduced, the execution time of actual sorting is reduced to the minimum, the sorting efficiency is very high, and sorting is not restricted by the number of sub-modules. In addition, a non-ideal condition correction optimized merging and sorting algorithm is provided by combining a direct insertion sorting method, the sorting accuracy can be ensured by correcting the optimized algorithm, the voltage equalizing effect is good, and the extra time overhead is small.
Description
Technical field
The present invention relates to technical field of power systems, particularly relate to a kind of based on the modularity optimizing merger sequence
Multilevel converter capacitor voltage equalizing method.
Background technology
HVDC transmission system (VSC-HVDC) based on voltage source converter can independently control meritorious and
Reactive power, can be operated in passive inverter state, and development prospect is wide.But, should at high-power
In with, the pressure problem of switching device that traditional two level and three level VSC bring is difficult to solve.Such as Fig. 1 institute
Novel modularized multi-level converter topology (modular multilevel converter, MMC) shown can
Be effectively improved level number, reduce harmonic content, reduce switching frequency, and have facilitate modularized design and
The advantages such as cascade high voltage grade, have extensive use.Modulation system conventional for MMC can be divided into ladder
Ripple modulation technique and pulse width modulating technology, wherein recently level modulation (nearest level modulation,
NLM) as the one of Staircase wave, have that harmonic content is few, switching frequency is low and good output etc. is excellent
Point, it is adaptable to high level number inverter.
Document " novel many level VSC submodule capacitance parameter with all press strategy " (Proceedings of the CSEE,
Fourth champion, Ding Ming, the wide good fortune of soup etc., 2009) use NLM technology, first capacitance voltage is sorted, then root
Put into, according to bridge arm current set direction, some modules that voltage is the highest or minimum, make global voltage balance.Should
Method easily realizes, and is widely adopted, referred to as traditional method.But, when group number of modules is hundreds and thousands of,
The sequence amount of calculation of traditional method increases the most again, brings difficulty to control technology and hardware designs, increases
The enforcement difficulty of Practical Project, improves engineering cost.In addition, existing sort algorithm is not tied
Close the Volume control of MMC, simply the most different sort algorithms is applied in Pressure and Control.
Summary of the invention
The problem existed for prior art, the present invention proposes a kind of based on the modularity optimizing merger sequence
Multilevel converter capacitor voltage equalizing method, utilizes MMC modulation technique to optimize MERGING/SORTING ALGORITHM, makes computing
Amount greatly reduces, and will not acceptor number of modules limit, and the correction proposing non-ideality optimizes merger
Algorithm.
In order to realize object above, the present invention is achieved by the following technical solutions:
Based on optimizing the modularization multi-level converter capacitor voltage equalizing method that merger is sorted, first according to modularity
The input of multilevel converter submodule and excision state, be divided into input group and excision by submodule capacitor voltage
Group；Further according to the capacitance voltage size order of submodule previous moment sequence, and put into and the submodule of excision
Block number and the sense of current, determine the charge or discharge state of electric capacity；Finally according to charge or discharge state pair
Orderly two groups carry out 2 tunnel merger of pointer ascending order or pointer descending, obtain the ranking results of later moment in time.
Further, in the ideal case, in the case of the capacitance parameter of the most all submodules is identical, apply excellent
Change merger sort method capacitance voltage is ranked up, it may be assumed that first according to modularization multi-level converter submodule
The input of block and excision state, be divided into input group and excision group by submodule capacitor voltage；Further according to submodule
Previous moment sequence capacitance voltage size order, and put into and excision submodule number and the sense of current,
Determine the charge or discharge state of electric capacity；Pointer is carried out to orderly two groups finally according to charge or discharge state
Ascending order or 2 tunnel merger of pointer descending, obtain the ranking results of later moment in time.(as shown in Figure 2)
Further, under non-ideal conditions, in the case of i.e. assuming that the capacitance parameter of all submodules differs,
Application is revised optimization merger sort method and is ranked up capacitance voltage, it may be assumed that first according to modular multilevel
The input of inverter submodule and excision state, be divided into input group and excision group by submodule capacitor voltage；Again
According to the capacitance voltage size order of submodule previous moment sequence, and put into and the submodule number of excision
With the sense of current, determine the charge or discharge state of electric capacity；Further according to charge or discharge state to input group and
Excision group is respectively adopted pointer ascending order or the Straight Insertion Sort of pointer descending；Finally orderly two groups are carried out
Pointer ascending order or 2 tunnel merger of pointer descending, obtain the ranking results of later moment in time.
Sum up present invention advantage based on the modularization multi-level converter capacitor voltage equalizing method optimizing merger sequence
As follows:
1) compared with tradition bubble sort, merger sequence significantly reduces actual execution time, the row of improve
Sequence efficiency, time complexity reduces an order of magnitude.
2) in the ideal case, according to nearest level modulation Neutron module capacitance voltage rule, returning after optimization
And the time complexity that sorts reduces further, the execution time of actual sequence is minimized, and sequence efficiency is very
High.
3), under non-ideality, optimize merger sequence and can play the effect of equilibrium DC voltage, but concordance is not
Enough ideals；Revise optimized algorithm and ensure that the correctness of sequence, all press effective, and expense extra time
Less, speed still sorts far above merger.
Utilize MMC modulation technique, by analyzing the capacitance voltage rule of ideally level modulation recently,
Optimize MERGING/SORTING ALGORITHM, make operand greatly reduce, and will not acceptor number of modules limit, and propose
The correction of non-ideality optimizes conflation algorithm.
Accompanying drawing explanation
Fig. 1 is modularization multi-level converter topology
Fig. 2 is the method for equalizing voltage using and optimizing merger sequence
Fig. 3 is to use to revise the method for equalizing voltage optimizing merger sequence
Fig. 4 is 2 tunnel merger flow charts of pointer ascending order
Fig. 5 is 2 tunnel merger flow charts of pointer descending
Fig. 6 is Straight Insertion Sort (pointer ascending order) flow process limiting step number
Fig. 7 is Straight Insertion Sort (pointer descending) flow process limiting step number
Fig. 8 is merger sequence, optimizes merger and the execution time of correction algorithm
Fig. 9 is the changes in Δ t of 7 submodule capacitor voltage
Figure 10 is the changes in Δ t of 7 submodule capacitor voltage of non-ideal parameter
Detailed description of the invention
The disclosure will be further described referring to the drawings below.Special declaration, description below is substantially
Simply serve Macroscopical Explanation and the effect of example explanation, never carry out appointing to the disclosure and application thereof or use
What limits.Unless stated otherwise, otherwise, the parts that illustrate in an embodiment and step positioned opposite
And numerical expression and numerical value are not limiting as the scope of the present disclosure.It addition, it is well known by persons skilled in the art
Technology, method and apparatus may not be discussed in detail, but are meant as the one of description in appropriate circumstances
Part.
Based on optimizing the modularization multi-level converter capacitor voltage equalizing method that merger is sorted, comprise the following steps:
First n element is divided into the subsequence respectively containing n/2 element, then to two subsequence recurrence sequences,
Finally merge two ordering subsequences and obtain final ranking results；And recurrence when a length of the 1 of subsequence
Terminate, i.e. individual element is considered as the most orderly.
The core concept of merger sequence is the most sorted subsequence of merger, and conventional and simplest return
And mode is 2 tunnel merger, an orderly sequence will be merged into by two orderly subsequences, its pointer liter
As shown in Figure 4, Fig. 5 show the merging algorithm flow chart of pointer descending to the merging algorithm flow of sequence.Wherein,
If subnumber group A [p...q] and A [q+1...r] sequence sequence (being incremented by) the most respectively, being merged into one group has ordinal number
Row z [p]≤z [p+1]≤...≤z [r].Pointer ascending order is i.e. according to the ascending 2 tunnel merger of the index value of sequence, pointer
Descending is then that index value is descending, and ideally the ranking results of both approaches is identical, but non-ideal
Situation can cause different results, and affects the effect all pressed.
In the ideal case, i.e. assume that the capacitance parameter of all submodules is identical.If in time Δ t, in A phase
Brachium pontis has n1 submodule to be in input state, and n2 submodule is in excision state, and does not has in Δ t
Changing, now the bridge arm current n1 to having put into a sub-module capacitance is charged simultaneously.Due to its series connection and electric capacity
Be worth identical, so voltage variety is identical, therefore the size order of this n1 capacitance voltage in Δ t not
Having relative changes, and n2 the submodule capacitor voltage being in excision state keeps constant, its relative ranks is certainly
The most constant.It can thus be seen that the submodule of single brachium pontis to be divided into input and excision two groups, these two groups
Capacitance voltage relative ranks in group is constant in Δ t.Therefore, will be according to putting into/excise state and electric current
Two groups of sequences that direction divides carry out 2 tunnel merger, i.e. obtain the ranking results after the Δ t time.Meanwhile,
In order to obtain the best all pressures effect under non-ideality, when bridge arm current is charged to electric capacity, employing refers to
2 road conflation algorithms of pin ascending order；And bridge arm current is when discharging to electric capacity, use 2 tunnel merger of pointer descending
Algorithm.Fig. 2 show and uses the method for equalizing voltage block diagram optimizing merger sequence.
Under non-ideal conditions, i.e. it is difficult to ensure that all capacitances are identical in Practical Project, therefore when putting into electricity
Hold voltage close to time, the deviation of capacitance can cause the difference of voltage variety, and size order may change
Become.In like manner, the difference of module loss and electric capacity discharge resistance is likely to cause analogue to occur.Therefore,
It is a small amount of and adjacent feature in conjunction with mistake.
The present invention proposes following optimization merging method of revising: before 2 tunnel merger, in conjunction with the knot of upper minor sort
Really, input group and excision group are respectively adopted Straight Insertion Sort.The thought of this sequence is every time by a number
According to being inserted in the most orderly sequence and keeping new sequence still orderly, " directly " refers to that foundation sequence number size is suitable
Sequence compares one by one, meanwhile, for preventing the overlong time of correction algorithm, limits the sequence step of Straight Insertion Sort
Number, only does part correction.If treating that Sorted list A [1 ... N], Fig. 6 show and limit the direct of step number for one group
Insertion sort (pointer ascending order) flow process, Fig. 7 show the Straight Insertion Sort (pointer descending) limiting step number
Flow process.Wherein, Set is for limiting step number, it is possible to the number of times of artificial limitation sequence.Similarly, in order to limited
Step number in obtain best correction effect, when bridge arm current is charged to electric capacity, use pointer ascending order straight
Connect insertion sort；And bridge arm current is when discharging to electric capacity, use the Straight Insertion Sort of pointer descending.Algorithm
Fig. 3 show to use and revises the method for equalizing voltage block diagram optimizing merger sequence.
As shown in Figure 8 for merger sequence, optimize merger sequence and revise the matching of optimization MERGING/SORTING ALGORITHM
With the actual measurement execution time.
Below in conjunction with being embodied as row, the present invention will be described.
In the ideal case, i.e. assume that the capacitance parameter of all submodules is identical.Fig. 9 show 7 submodules
Block capacitance voltage situation of change in Δ t, it is assumed that having 4 submodules to put into, capacitance voltage is ascending
Order is 3 → 5 → 4 → 6, has 3 submodule excisions, and the size order of voltage is 2 → 1 → 7.Due to Δ t
The state of these 7 submodules interior is not changed in, so being classified as putting into and excision two groups.Because electric capacity is joined
Number is identical, and the capacitance voltage in these two groups of groups is the most parallel, although through the time of Δ t, global voltage value
Sequence changes the most completely, but the relative ranks in these two groups of groups is not changed in, and utilizes this feature, in conjunction with
Merger sequence can Optimal scheduling algorithm reduce operand further.
Analyze according to above, if the size order of capacitance voltage, such as Fig. 3 when have recorded last sequence
The ranking results in middle t1 moment, and have recorded the submodule number and the sense of current put into and excise, divide accordingly
Be two groups, then these two groups of sequences are all the most orderly in Δ t, therefore have only to 2 tunnel merger the most available
The ranking results in t2 moment, decomposition and the step of multilamellar recursive tree merger in merger sequence can be saved.
The time complexity of 2 tunnel merger of pointer ascending order and pointer descending the most only needs O (n), reduces compared with O (n2)
Two orders of magnitude.In the case of must traveling through whole sequence, it has been the fastest sequencing production the most.
Under non-ideal conditions, i.e. assume that the capacitance parameter of all submodules differs.Figure 10 show electric capacity
Module voltage change schematic diagram during parameter difference.Module 4 and 5 voltage is sufficiently close to, through Δ t size order
Exchange, and 2 tunnel merger after optimizing are the phases in ranking results (5 → 4) the prediction t2 moment according to the t1 moment
To relation (5 → 4), but after exchanging, there is mistake (4 → 5) in prediction.Other voltage phase difference are relatively big, therefore
The most constant.Use at this and revise the method for equalizing voltage optimizing merger sequence, i.e. before 2 tunnel merger, in conjunction with
The result of upper minor sort and the sense of current, be respectively adopted pointer ascending order or pointer descending to input group and excision group
Straight Insertion Sort.
Wherein, optimizing merger sorting time complexity is linear O (n), is inserted directly into approximately linear O (n), institute
Also approximately linear O (n) is optimized with total correction.Compared to tradition bubble sort and be not optimised merger, operand
Still it is substantially reduced, utilizes and limit the time that step number can also control to revise.
Although example embodiment describes the disclosure, it should be appreciated that the disclosure is not limited to above-mentioned exemplary
Embodiment.It will be obvious to those skilled in the art that can be without departing substantially from the scope of the present disclosure and spirit
Under the conditions of revise exemplary embodiments mentioned above.The scope of appended claim should be endowed the widest explanation,
To comprise all such amendments and the 26S Proteasome Structure and Function of equivalent.
Claims (3)
1. based on the modularization multi-level converter capacitor voltage equalizing method optimizing merger sequence, it is characterised in that:
First according to input and the excision state of Modularized multi-level converter sub-module, by submodule electric capacity electricity
Pressure is divided into input group and excision group；
Further according to the capacitance voltage size order of submodule previous moment sequence, and put into and the submodule of excision
Block number and the sense of current, determine the charge or discharge state of electric capacity；
Finally according to charge or discharge state, orderly two groups 2 tunnels carrying out pointer ascending order or pointer descending are returned
And, obtain the ranking results of later moment in time.
The most according to claim 1 equal based on the modularization multi-level converter electric capacity optimizing merger sequence
Pressure method, it is characterised in that: in the ideal case, in the case of the capacitance parameter of the most all submodules is identical,
Capacitance voltage is ranked up by optimizing application merger sort method, it may be assumed that
First according to input and the excision state of Modularized multi-level converter sub-module, by submodule electric capacity electricity
Pressure is divided into input group and excision group；
Further according to the capacitance voltage size order of submodule previous moment sequence, and put into and the submodule of excision
Block number and the sense of current, determine the charge or discharge state of electric capacity；
Finally according to charge or discharge state, orderly two groups 2 tunnels carrying out pointer ascending order or pointer descending are returned
And, obtain the ranking results of later moment in time.
The most according to claim 1 a kind of based on the modularization multi-level converter electricity optimizing merger sequence
Hold method for equalizing voltage, it is characterised in that: under non-ideal conditions, i.e. assume the capacitance parameter of all submodules not
In the case of identical, application is revised optimization merger sort method and is ranked up capacitance voltage, it may be assumed that
First according to input and the excision state of Modularized multi-level converter sub-module, by submodule electric capacity electricity
Pressure is divided into input group and excision group；
Further according to the capacitance voltage size order of submodule previous moment sequence, and put into and the submodule of excision
Block number and the sense of current, determine the charge or discharge state of electric capacity；
Further according to charge or discharge state, input group and excision group it is respectively adopted pointer ascending order or pointer descending
Straight Insertion Sort；
Finally orderly two groups are carried out 2 tunnel merger of pointer ascending order or pointer descending, obtains later moment in time
Ranking results.
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| CN106786910A (en) * | 2016-12-27 | 2017-05-31 | 中国西电电气股份有限公司 | It is a kind of at the same suitable for MMC converter valve submodules alternating current-direct current charge method |
| CN110912432A (en) * | 2018-09-17 | 2020-03-24 | 长沙理工大学 | MMC capacitor voltage-sharing strategy with lower switching frequency and complexity |
| CN111478597A (en) * | 2020-04-02 | 2020-07-31 | 广东安朴电力技术有限公司 | Voltage balance control method, controller and MMC cascade system |
| CN114264885A (en) * | 2021-12-03 | 2022-04-01 | 国网浙江省电力有限公司杭州供电公司 | Converter valve module capacitance online monitoring method based on sorting algorithm |
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| CN106786910A (en) * | 2016-12-27 | 2017-05-31 | 中国西电电气股份有限公司 | It is a kind of at the same suitable for MMC converter valve submodules alternating current-direct current charge method |
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| CN114264885A (en) * | 2021-12-03 | 2022-04-01 | 国网浙江省电力有限公司杭州供电公司 | Converter valve module capacitance online monitoring method based on sorting algorithm |
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