CN105958850B - Modularization multi-level converter capacitor voltage equalizing method based on optimization merger sequence - Google Patents
Modularization multi-level converter capacitor voltage equalizing method based on optimization merger sequence Download PDFInfo
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- CN105958850B CN105958850B CN201610311275.6A CN201610311275A CN105958850B CN 105958850 B CN105958850 B CN 105958850B CN 201610311275 A CN201610311275 A CN 201610311275A CN 105958850 B CN105958850 B CN 105958850B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/36—Arrangements for transfer of electric power between ac networks via a high-tension dc link
Abstract
The present invention provides a kind of modularization multi-level converter capacitor voltage equalizing method based on optimization merger sequence, utilize modularization multi-level converter modulation technique, by the capacitance voltage rule for analyzing ideally nearest level modulation, optimize MERGING/SORTING ALGORITHM, merger sorting time complexity after optimization further reduces, the execution time actually sorted minimizes, and sequence efficiency is very high, and will not the limitation of acceptor number of modules.In addition, with reference to Straight Insertion Sort method, there is provided the amendment optimization conflation algorithm of non-ideality, amendment optimized algorithm can ensure the correctness of sequence, and voltage equalizing is good, and extra time expense is smaller.
Description
Technical field
The present invention relates to technical field of power systems, more particularly to a kind of modular multilevel based on optimization merger sequence
Transverter capacitor voltage equalizing method.
Background technology
HVDC transmission system (VSC-HVDC) based on voltage source converter can independent control be active and reactive power,
Passive inverter state can be operated in, development prospect is wide.However, in high-power application, traditional two level and three electricity
The pressure-resistant problem of switching device that flat VSC is brought is difficult to solve.Novel modularized multi-level converter topology as shown in Figure 1
(modular multilevel converter, MMC) can effectively improve level number, reduce harmonic content, reduce switch frequency
Rate, and have the advantages that to facilitate modularized design and cascade high voltage grade that there is extensive use.Modulation conventional MMC
Mode can be divided into Staircase wave technology and pulse width modulating technology, wherein nearest level modulation (nearest level
Modulation, NLM) one kind as Staircase wave, have that harmonic content is few, switching frequency is low and good output etc. is excellent
Point, suitable for high level number transverter.
Document《New more level VSC submodules capacitance parameters and pressure strategy》(Proceedings of the CSEE, fourth champion,
Ding Ming, the wide good fortune of soup etc., 2009) NLM technologies are used, first capacitance voltage is sorted, electricity is put into further according to bridge arm current set direction
Highest or minimum some modules are pressed, balance global voltage.This method is easily realized, is widely adopted, and is referred to as tradition side
Method.However, when group number of modules is hundreds and thousands of, the sequence amount of calculation of conventional method exponentially increases again, to control technology and
Hardware design brings difficulty, adds the enforcement difficulty of Practical Project, improves engineering cost.In addition, existing sequence
Algorithm is not bound with MMC control feature, simply applies mathematically different sort algorithms in Pressure and Control.
The content of the invention
The problem of existing for prior art, the present invention propose a kind of modular multilevel based on optimization merger sequence
Transverter capacitor voltage equalizing method, optimize MERGING/SORTING ALGORITHM using MMC modulation techniques, greatly reduce operand, and will not be by
Submodule number limits, and proposes the amendment optimization conflation algorithm of non-ideality.
In order to realize the above object the present invention is achieved using following technical scheme：
Based on the modularization multi-level converter capacitor voltage equalizing method of optimization merger sequence, first according to modular multilevel
The input and excision state of transverter submodule, are divided into input group and excision group by submodule capacitor voltage；Further according to submodule
The capacitance voltage size order of previous moment sequence, and input and the submodule number and the sense of current of excision, determine electric capacity
Charge or discharge state；Finally enter the 2 of line pointer ascending order or pointer descending to orderly two groups according to charge or discharge state
Road merger, obtain the ranking results of later moment in time.
Further, in the ideal case, i.e., in the case of the capacitance parameter identical of all submodules, optimizing application merger row
Sequence method is ranked up to capacitance voltage, i.e.,：First according to the input of Modularized multi-level converter sub-module and state is cut off,
Submodule capacitor voltage is divided into input group and excision group；It is suitable further according to the capacitance voltage size of submodule previous moment sequence
Sequence, and input and the submodule number and the sense of current of excision, determine the charge or discharge state of electric capacity；Finally according to charging
Or discharge condition enters 2 tunnel merger of line pointer ascending order or pointer descending to orderly two groups, obtains the ranking results of later moment in time.
(as shown in Figure 2)
Further, under non-ideal conditions, that is, in the case of assuming that the capacitance parameter of all submodules differs, using repairing
Positive optimization merger sort method is ranked up to capacitance voltage, i.e.,：First according to the throwing of Modularized multi-level converter sub-module
Enter and cut off state, submodule capacitor voltage is divided into input group and excision group；Further according to the electricity of submodule previous moment sequence
Hold voltage swing order, and input and the submodule number and the sense of current of excision, determine the charge or discharge state of electric capacity；
Input group and excision group are respectively adopted further according to charge or discharge state the Straight Insertion Sort of pointer ascending order or pointer descending；
Finally orderly two groups are entered with 2 tunnel merger of line pointer ascending order or pointer descending, obtains the ranking results of later moment in time.
The advantage for summarizing modularization multi-level converter capacitor voltage equalizing method of the present invention based on optimization merger sequence is as follows：
1) compared with traditional bubble sort, merger sequence significantly reduces actual execution time, improves sequence efficiency,
Time complexity reduces an order of magnitude.
2) in the ideal case, according to nearest level modulation Neutron module capacitance voltage rule, the merger sequence after optimization
Time complexity further reduces, and the execution time actually sorted minimizes, and sequence efficiency is very high.
3) under non-ideality, optimization merger sequence can play the effect of balanced DC voltage, but uniformity is not ideal enough；
Amendment optimized algorithm can ensure the correctness of sequence, and voltage equalizing is good, and extra time expense is smaller, and speed, which is still far above, returns
And sort.
Using MMC modulation techniques, by analyzing the capacitance voltage rule of ideally nearest level modulation, optimize merger
Sort algorithm, greatly reduce operand, and will not acceptor number of modules limitation, and propose non-ideality amendment optimization
Conflation algorithm.
Brief description of the drawings
Fig. 1 is modularization multi-level converter topology
Fig. 2 is the method for equalizing voltage using optimization merger sequence
Fig. 3 is the method for equalizing voltage using amendment optimization merger sequence
Fig. 4 is 2 tunnel merger flow charts of pointer ascending order
Fig. 5 is 2 tunnel merger flow charts of pointer descending
Fig. 6 is Straight Insertion Sort (pointer ascending order) flow of limitation step number
Fig. 7 is Straight Insertion Sort (pointer descending) flow of limitation step number
Fig. 8 is the execution time of merger sequence, optimization merger and correction algorithm
Fig. 9 is change of 7 submodule capacitor voltages in Δ t
Figure 10 is change of 7 submodule capacitor voltages of non-ideal parameter in Δ t
Embodiment
The disclosure will be further described referring to the drawings below.Special declaration, following description are substantially
The effect that Macroscopical Explanation and example illustrate has been arrived, never to the disclosure and its application or has used progress any restrictions.Unless in addition
Special instruction, otherwise, the part and the positioned opposite and numerical expression and numerical value of step illustrated in embodiment is unlimited
The scope of the present disclosure processed.In addition, technology well known by persons skilled in the art, method and apparatus may not be discussed in detail, but
Part for specification is meant as in the case of appropriate.
Based on the modularization multi-level converter capacitor voltage equalizing method of optimization merger sequence, comprise the following steps：
N element is divided into the subsequence respectively containing n/2 element first, then two subsequence recurrence are sorted, is finally closed
And two ordering subsequences obtain final ranking results；And the length of subsequence be 1 when recurrence terminate, i.e., individual element regards
To be orderly.
The core concept of merger sequence is merger sorted subsequence, and conventional and simplest merger mode
2 tunnel merger, will two orderly subsequences merge into an orderly sequence, the merging algorithm flow of its pointer ascending order is such as
Shown in Fig. 4, Fig. 5 show the merging algorithm flow chart of pointer descending.Wherein, if subnumber group A [p...q] and A [q+1...r] all
Sequenced sequence (incremental) respectively, be merged into one group of ordered sequence z [p]≤z [p+1]≤...≤z [r].Pointer ascending order is pressed
According to the ascending 2 tunnel merger of index value of sequence, pointer descending is then that index value is descending, ideally both approaches
Ranking results it is identical, but non-ideality can cause different results, and influence the effect pressed.
In the ideal case, that is, assume that the capacitance parameter of all submodules is identical.If in time Δ t, bridge arm has n1 in A phases
Individual submodule is in input state, and n2 submodule is in excision state, and does not change in Δ t, now bridge arm current pair
The n1 that has put into sub- module capacitances while charge.Due to its series connection and capacitance is identical, so voltage variety is identical, therefore
The size order of this n1 capacitance voltage does not have relative changes in Δ t, and is in n2 sub- module capacitances of excision state
Voltage keeps constant, and its relative ranks is naturally also constant.It can thus be seen that the submodule of single bridge arm is divided into input and cut
Except two groups, the capacitance voltage relative ranks in this two groups of groups are constant in Δ t.Therefore, will according to input/excision state and
Two groups of sequences of sense of current division carry out 2 tunnel merger, that is, obtain the ranking results after the Δ t times.Meanwhile in order to obtain
Best voltage equalizing under non-ideality, when bridge arm current charges to electric capacity, calculated using 2 tunnel merger of pointer ascending order
Method；And bridge arm current is to electric capacity when discharging, using 2 road conflation algorithms of pointer descending.Fig. 2 is shown using optimization merger sequence
Method for equalizing voltage block diagram.
Under non-ideal conditions, i.e., in Practical Project it is difficult to ensure that all capacitances are identical, therefore when the electricity of input electric capacity
When crimping near, the deviation of capacitance can cause the difference of voltage variety, and size order may change.Similarly, module loss
And the difference of electric capacity discharge resistance may also cause analogue.Therefore, the characteristics of being a small amount of and adjacent with reference to mistake.
The present invention proposes following amendment optimization merging method：Before 2 tunnel merger, with reference to the result of upper minor sort, to throwing
Enter group and Straight Insertion Sort is respectively adopted in excision group.The thought of the sequence is that a data are inserted into orderly sequence every time
In row and keep new sequence still orderly, " direct " refers to one by one compare according to sequence number size order, meanwhile, to prevent from correcting
The overlong time of algorithm, the sequence step number of Straight Insertion Sort is limited, only does part amendment.If one group is treated Sorted list A
[1 ... N], Fig. 6 show Straight Insertion Sort (pointer ascending order) flow of limitation step number, and Fig. 7 show the direct of limitation step number
Insertion sort (pointer descending) flow.Wherein, Set is limitation step number, is capable of the number of artificial limitation sequence.Similarly, in order to
Best correction effect is obtained in limited step number, when bridge arm current charges to electric capacity, using directly inserting for pointer ascending order
Enter sequence；And bridge arm current is to electric capacity when discharging, using the Straight Insertion Sort of pointer descending.Algorithm pattern 3 show to use and repaiied
The method for equalizing voltage block diagram of positive optimization merger sequence.
It is as shown in Figure 8 merger sequence, optimization merger is sorted and the fitting and actual measurement of amendment optimization MERGING/SORTING ALGORITHM
Perform the time.
Below in conjunction with specific implementation row, the present invention will be described.
In the ideal case, that is, assume that the capacitance parameter of all submodules is identical.Fig. 9 show 7 sub- module capacitance electricity
The situation of change being pressed in Δ t, it is assumed that have 4 submodule inputs, the ascending order of capacitance voltage is 3 → 5 → 4 → 6, is had
3 submodule excisions, the size order of voltage is 2 → 1 → 7.Because the state of this 7 submodules in Δ t does not change, so
It is classified as putting into and cuts off two groups.Because capacitance parameter is identical, the capacitance voltage difference in this two groups of groups is parallel, although by
Δ t time, the sequence of global voltage value change completely, but the relative ranks in this two groups of groups do not change, and utilize this
One feature, Optimal scheduling algorithm and it can further reduce operand with reference to merger sequence.
Analyzed more than, if when have recorded last sequence capacitance voltage size order, such as t1 moment in Fig. 3
Ranking results, and have recorded input and excision submodule number and the sense of current, be divided into two groups accordingly, then this two groups of sequences
All it is orderly respectively in Δ t, therefore only needs 2 tunnel merger to can obtain the ranking results at t2 moment, during merger is sorted
The step of decomposition and multilayer recursive tree merger, can save.The time of 2 tunnel merger of pointer ascending order and pointer descending is complicated
Degree all only needs O (n), and two orders of magnitude are reduced compared with O (n2).In the case where whole sequence must be traveled through, in theory
It is most fast sequencing production.
Under non-ideal conditions, that is, assume that the capacitance parameter of all submodules differs.Figure 10 show capacitance parameter not
Module voltage change schematic diagram simultaneously.The voltage of module 4 and 5 is sufficiently close to, and is exchanged by Δ t size orders, and 2 tunnels after optimizing
Merger is that the relativeness (5 → 4) at t2 moment is predicted according to the ranking results (5 → 4) at t1 moment, but predicts occur after exchanging
Mistake (4 → 5).Other voltage phase differences are larger, therefore order is constant.The method for equalizing voltage to be sorted herein using amendment optimization merger,
I.e. before 2 tunnel merger, with reference to the result and the sense of current of upper minor sort, pointer ascending order is respectively adopted to input group and excision group
Or the Straight Insertion Sort of pointer descending.
Wherein, it is linear O (n) to optimize merger sorting time complexity, is inserted directly into approximately linear O (n), so total repaiies
It is positive to optimize also approximately linear O (n).Compared to traditional bubble sort and merger is not optimised, operand is still substantially reduced, and utilizes limit
Step number processed can also control the time of amendment.
Although example embodiment describes the disclosure, it should be appreciated that the disclosure is not limited to exemplary embodiments mentioned above.
It will be obvious to those skilled in the art that above-mentioned show can be changed under conditions of without departing substantially from the scope of the present disclosure and spirit
Example property embodiment.The scope of appended claim should be endowed most wide explanation, with comprising it is all it is such modification and wait
Same 26S Proteasome Structure and Function.
Claims (1)
1. the modularization multi-level converter capacitor voltage equalizing method based on optimization merger sequence, it is characterised in that：
In the ideal case, i.e., in the case of the capacitance parameter identical of all submodules, optimizing application merger sort method is to electricity
Hold voltage to be ranked up, i.e.,：
First according to the input of Modularized multi-level converter sub-module and excision state, submodule capacitor voltage is divided into input
Group and excision group；
Further according to the capacitance voltage size order of submodule previous moment sequence, and input and the submodule number of excision and electricity
Direction is flowed, determines the charge or discharge state of electric capacity；
Finally according to charge or discharge state orderly two groups are entered with 2 tunnel merger of line pointer ascending order or pointer descending, after obtaining
The ranking results at one moment；
Under non-ideal conditions, that is, in the case of assuming that the capacitance parameter of all submodules differs, merger is optimized using amendment
Sort method is ranked up to capacitance voltage, i.e.,：
First according to the input of Modularized multi-level converter sub-module and excision state, submodule capacitor voltage is divided into input
Group and excision group；
Further according to the capacitance voltage size order of submodule previous moment sequence, and input and the submodule number of excision and electricity
Direction is flowed, determines the charge or discharge state of electric capacity；
Pointer ascending order is respectively adopted to input group and excision group further according to charge or discharge state or pointer descending is inserted directly into
Sequence；
Finally orderly two groups are entered with 2 tunnel merger of line pointer ascending order or pointer descending, obtains the ranking results of later moment in time.
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| CN106786910B (en) * | 2016-12-27 | 2019-12-27 | 中国西电电气股份有限公司 | Method simultaneously suitable for AC/DC charging of submodule of MMC converter valve |
| CN110912432A (en) * | 2018-09-17 | 2020-03-24 | 长沙理工大学 | MMC capacitor voltage-sharing strategy with lower switching frequency and complexity |
| CN111478597B (en) * | 2020-04-02 | 2021-07-13 | 广东安朴电力技术有限公司 | Voltage balance control method, controller and MMC cascade system |
| CN114264885A (en) * | 2021-12-03 | 2022-04-01 | 国网浙江省电力有限公司杭州供电公司 | Converter valve module capacitance online monitoring method based on sorting algorithm |
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| CN104135177B (en) * | 2014-07-24 | 2016-08-24 | 华北电力大学 | A kind of pressure equalizing control method of the submodule capacitor voltage layering being applicable to high level MMC |
| CN104932864A (en) * | 2015-06-25 | 2015-09-23 | 许继电气股份有限公司 | Merging-sorting method based on assembly line process and valve control device using merging-sorting method |
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