CN109889052B

CN109889052B - Method and device for controlling capacitor voltage of modular multilevel matrix converter

Info

Publication number: CN109889052B
Application number: CN201910096251.7A
Authority: CN
Inventors: 孙鹏伟; 张帆; 张野; 李俊杰; 袁豪
Original assignee: China Southern Power Grid Co Ltd; Research Institute of Southern Power Grid Co Ltd
Current assignee: China Southern Power Grid Co Ltd; Research Institute of Southern Power Grid Co Ltd
Priority date: 2019-01-31
Filing date: 2019-01-31
Publication date: 2020-08-18
Anticipated expiration: 2039-01-31
Also published as: CN109889052A

Abstract

The invention discloses a method and a device for controlling the capacitor voltage of a modular multilevel matrix converter, wherein the method comprises the following steps: the capacitors of the sub-modules in the bridge arm of the modular multilevel matrix converter are uniformly divided into a first sub-module capacitor and a second sub-module capacitor, when the period of the bridge arm current is detected to be an odd period, based on a logic operation unit of the FPGA, the first sub-module capacitors are sequenced in parallel within two preset clock cycles according to the voltage of the first sub-module capacitors, and controlling the action of the insulated gate bipolar transistor of the submodule according to the direction of the bridge arm current and a first modulation result, the capacitor of the sub-module is charged or discharged, the problem of unbalanced voltage of the capacitor of the sub-module in a bridge arm in the modulation process of the modular multi-level matrix converter can be effectively solved, the speed of a sorting algorithm can be effectively increased, the operation resources of an FPGA (field programmable gate array) are saved, and therefore the normal operation of the modular multi-level matrix converter can be effectively guaranteed.

Description

Method and device for controlling capacitor voltage of modular multilevel matrix converter

Technical Field

The invention relates to the technical field of power electronic device control, in particular to a method and a device for controlling capacitor voltage of a modular multilevel matrix converter.

Background

The Modular Multilevel Matrix Converter (MMMC) is a new type of frequency converter, which can realize bidirectional flow of power and is mainly used in the frequency conversion between ac systems (such as frequency division transmission systems) and the driving of medium and high voltage motors. Compared with the traditional matrix converter, the application of the modularization technology improves the expandability and the voltage withstanding level of the device. Because of using the full control switch, when the MMMC is used for a frequency division transmission system, the generated harmonic waves are less, and reactive compensation is not needed, so that the frequency converter has excellent performance.

The prior art is due to the following two points: firstly, the on-off time of each sub-module IGBT is not completely the same; and secondly, even for the devices in the same batch, the circuit parameters of the devices are not completely the same, so that the loss of each submodule is different, and the power provided by each submodule is not completely the same. The sub-module capacitor voltage imbalance in the bridge arm may occur in the MMMC modulation process, and at this time, although the control system ensures that the average voltage of the sub-module capacitor is always kept constant, the voltage difference between the sub-modules is larger and larger, and the normal operation of the MMMC is finally influenced.

Disclosure of Invention

The embodiment of the invention provides a method and a device for controlling capacitance and voltage of a modular multilevel matrix converter, which can effectively solve the problem of unbalanced capacitance and voltage of sub-modules in a bridge arm in the modulation process of the modular multilevel matrix converter, effectively improve the speed of a sorting algorithm, save the operation resources of an FPGA (field programmable gate array), and further effectively ensure the normal operation of the modular multilevel matrix converter.

An embodiment of the present invention provides a method for controlling a capacitor voltage of a modular multilevel matrix converter, including:

uniformly dividing the capacitance of the sub-modules in the bridge arm of the modular multilevel matrix converter into a first sub-module capacitance and a second sub-module capacitance;

when the odd-numbered period of the bridge arm current is detected, the FPGA-based logic operation unit performs parallel sequencing on the first sub-module capacitor within two preset clock periods according to the voltage of the first sub-module capacitor, and controls the insulated gate bipolar transistor of the sub-module to act according to the direction of the bridge arm current and a first modulation result so as to charge or discharge the capacitor of the sub-module; when the period of the bridge arm current is an odd number period, the number of the submodules outputting a positive level in a single bridge arm after the modular multilevel matrix converter is modulated is the first modulation result;

when the even cycle of the bridge arm current is detected, based on the logic operation unit of the FPGA, the second sub-module capacitors are sequenced in parallel in the two preset clock cycles according to the voltage of the second sub-module capacitors, and the insulated gate bipolar transistors of the sub-modules are controlled to act according to the direction of the bridge arm current and a second modulation result, so that the capacitors of the sub-modules are charged or discharged; and the second modulation result is the number of sub-modules which output positive levels in a single bridge arm after the modular multilevel matrix converter is modulated when the period of the bridge arm current is an even period.

Preferably, when the detected cycle of the bridge arm current is an odd cycle, the parallel sequencing of the first sub-module capacitors in two preset clock cycles according to the voltage of the first sub-module capacitors by the logic operation unit based on the FPGA specifically includes:

when the period of the bridge arm current is detected to be an odd period, in a first clock period, comparing the voltages of the first sub-module capacitors pairwise based on the logic operation unit of the FPGA to obtain a first sub-module capacitor voltage comparison value;

in a second clock period, calculating the voltage comparison value of the first sub-module capacitor based on the logic operation unit of the FPGA, and sequencing the voltages of the first sub-module capacitors from large to small according to the calculation result;

responding to a modulation instruction of the modular multilevel matrix converter, taking the number of sub-modules outputting positive levels in a single bridge arm of the modular multilevel matrix converter after modulation as a first modulation result, and judging the size relation between the number of the sub-modules outputting the positive levels and the number of the first sub-module capacitors according to the first modulation result.

Preferably, when it is detected that the period of the bridge arm current is an odd-numbered period, the FPGA-based logical operation unit performs parallel sequencing on the first sub-module capacitor within two preset clock periods according to the voltage of the first sub-module capacitor, and controls the igbt of the sub-module to operate according to the direction of the bridge arm current and the first modulation result, so as to perform an operation of charging or discharging the capacitor of the sub-module, specifically including:

when the number of the sub-modules outputting the positive level is judged to be not more than the number of the first sub-module capacitors and the direction of the bridge arm current is detected to be positive, the insulated gate bipolar transistors of the sub-modules are controlled to act, so that the capacitors which are sequenced to be the last n bits in the first sub-module capacitors are in a charging state, and the rest of the first sub-module capacitors and the rest of the second sub-module capacitors are in a discharging state; n is more than 0 and less than or equal to N, wherein N is the number of sub-modules outputting the positive level, and N is the number of capacitors of sub-modules in a bridge arm of the modular multilevel matrix converter;

and when the number of the sub-modules outputting the positive level is judged to be not more than the number of the first sub-module capacitors and the direction of the bridge arm current is detected to be negative, controlling the insulated gate bipolar transistors of the sub-modules to act so that the capacitors with the first n bits in sequence in the first sub-module capacitors are in a discharging state, and the rest of the first sub-module capacitors and the rest of the second sub-module capacitors are in a charging state.

Preferably, the method further comprises:

when the number of the sub-modules outputting the positive level is judged to be larger than the number of the first sub-module capacitors and the direction of the bridge arm current is detected to be positive, the insulated gate bipolar transistors of the sub-modules are controlled to act, so that the capacitors which are sequenced to be the first N-N bits in the first sub-module capacitors are in a discharging state, and the rest of the first sub-module capacitors and the rest of the second sub-module capacitors are in a charging state;

and when the number of the sub-modules outputting the positive level is judged to be larger than the number of the first sub-module capacitors and the direction of the bridge arm current is detected to be negative, controlling the insulated gate bipolar transistors of the sub-modules to act so that the capacitors with the last N-N bits in the first sub-module capacitors are in a charging state, and the rest of the first sub-module capacitors and the rest of the second sub-module capacitors are in a discharging state.

Preferably, when it is detected that the period of the bridge arm current is an even period, the parallel sequencing of the second sub-module capacitors in the two preset clock periods according to the voltage of the second sub-module capacitors based on the logic operation unit of the FPGA specifically includes:

when the period of the bridge arm current is detected to be an even period, in a first clock period, the voltages of the second sub-module capacitors are compared pairwise based on the logic operation unit of the FPGA to obtain a second sub-module capacitor voltage comparison value;

in a second clock period, calculating the voltage comparison value of the capacitor of the second sub-module based on a logic operation unit of the FPGA, and sequencing the voltages of the capacitors of the second sub-module from large to small according to the calculation result;

responding to a modulation instruction of the modular multilevel matrix converter, taking the number of sub-modules outputting positive levels in a single bridge arm of the modular multilevel matrix converter after modulation as a second modulation result, and judging the size relation between the number of the sub-modules outputting the positive levels and the number of capacitors of the second sub-modules according to the second modulation result.

Preferably, when it is detected that the period of the bridge arm current is an even period, the logic operation unit based on the FPGA sequences the second sub-module capacitors in parallel in the two preset clock periods according to the voltage of the second sub-module capacitor, and controls the igbt of the sub-module to operate according to the direction of the bridge arm current and the second modulation result, so as to charge or discharge the capacitors of the sub-module, specifically including:

when the number of the sub-modules outputting the positive level is judged to be not more than the number of the second sub-module capacitors and the direction of the bridge arm current is detected to be positive, the insulated gate bipolar transistors of the sub-modules are controlled to act, so that the capacitors which are sequenced to be the last n bits in the second sub-module capacitors are in a charging state, and the rest of the second sub-module capacitors and the first sub-module capacitors are in a discharging state; n is more than 0 and less than or equal to N, wherein N is the number of sub-modules outputting the positive level, and N is the number of capacitors of sub-modules in a bridge arm of the modular multilevel matrix converter;

and when the number of the sub-modules outputting the positive level is judged to be not more than the number of the second sub-module capacitors and the direction of the bridge arm current is detected to be negative, controlling the insulated gate bipolar transistors of the sub-modules to act so that the capacitors which are sequenced to be the first n bits in the second sub-module capacitors are in a discharging state, and the rest of the second sub-module capacitors and the first sub-module capacitors are in a charging state.

Preferably, the method further comprises:

when the number of the sub-modules outputting the positive level is judged to be larger than the number of the second sub-module capacitors and the direction of the bridge arm current is detected to be positive, the insulated gate bipolar transistors of the sub-modules are controlled to act, so that the capacitors which are sequenced to be the first N-N bits in the second sub-module capacitors are in a discharging state, and the rest of the second sub-module capacitors and the first sub-module capacitors are in a charging state;

and when the number of the sub-modules outputting the positive level is judged to be larger than that of the second sub-module capacitors and the direction of the bridge arm current is detected to be negative, controlling the insulated gate bipolar transistors of the sub-modules to act so that the capacitors with the last N-N bits in the second sub-module capacitors are in a charging state, and the rest of the second sub-module capacitors and the first sub-module capacitors are in a discharging state.

Another embodiment of the present invention correspondingly provides a device for controlling capacitor voltage of a modular multilevel matrix converter, including:

the data dividing module is used for uniformly dividing the capacitance of the sub-modules in the bridge arm of the modular multilevel matrix converter into a first sub-module capacitance and a second sub-module capacitance;

the first data processing module is used for carrying out parallel sequencing on the first sub-module capacitor within two preset clock cycles according to the voltage of the first sub-module capacitor and controlling the action of the insulated gate bipolar transistor of the sub-module according to the direction of the bridge arm current and a first modulation result based on a logic operation unit of the FPGA when the condition that the period of the bridge arm current is an odd-numbered period is detected, so that the capacitor of the sub-module is charged or discharged; when the period of the bridge arm current is an odd number period, the number of the submodules outputting a positive level in a single bridge arm after the modular multilevel matrix converter is modulated is the first modulation result;

the second data processing module is used for carrying out parallel sequencing on the capacitors of the second sub-modules in the two preset clock cycles according to the voltages of the capacitors of the second sub-modules based on the logic operation unit of the FPGA when the fact that the period of the bridge arm current is an even period is detected, and controlling the insulated gate bipolar transistors of the sub-modules to act according to the direction of the bridge arm current and a second modulation result so as to charge or discharge the capacitors of the sub-modules; and the second modulation result is the number of sub-modules which output positive levels in a single bridge arm after the modular multilevel matrix converter is modulated when the period of the bridge arm current is an even period.

Compared with the prior art, the method and the device for controlling the capacitance and the voltage of the modular multilevel matrix converter disclosed by the embodiment of the invention have the advantages that the capacitance of the sub-modules in the bridge arm of the modular multilevel matrix converter is uniformly divided into the first sub-module capacitance and the second sub-module capacitance, when the cycle of the bridge arm current is detected to be an odd cycle, the first sub-module capacitance is sequenced in parallel in two preset clock cycles according to the voltage of the first sub-module capacitance based on the logic operation unit of the FPGA, the insulated gate bipolar transistor of the sub-modules is controlled to act according to the direction of the bridge arm current and the first modulation result so as to charge or discharge the capacitance of the sub-modules, and when the cycle of the bridge arm current is detected to be an even cycle, the second sub-module capacitance is charged or discharged in the two preset clock cycles according to the voltage of the second sub-module capacitance based on the logic operation unit of the FPGA And the rows are sorted in parallel, the action of the insulated gate bipolar transistor of the submodule is controlled according to the direction of the bridge arm current and the second modulation result, so that the capacitor of the submodule is charged or discharged, the sorting speed can be effectively increased by adopting a parallel sorting mode, the real-time performance is good, the operation resource of an FPGA (field programmable gate array) can be effectively saved, the cost is reduced, the problem of unbalanced voltage of the capacitor of the submodule in the bridge arm in the modulation process of the modular multilevel matrix converter can be effectively solved, and the normal operation of the modular multilevel matrix converter is ensured.

Another embodiment of the present invention provides a device for controlling capacitor voltage of a modular multilevel matrix converter, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, where the processor implements the method for controlling capacitor voltage of a modular multilevel matrix converter according to the above embodiment of the present invention when executing the computer program.

Another embodiment of the present invention provides a storage medium, where the storage medium includes a stored computer program, where when the computer program runs, an apparatus where the computer readable storage medium is located is controlled to execute the method for controlling capacitor voltage of a modular multilevel matrix converter according to the above embodiment of the present invention.

Drawings

Fig. 1 is a schematic flowchart of a method for controlling capacitor voltage of a modular multilevel matrix converter according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a modular multilevel matrix converter according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a sub-module circuit in a bridge arm of the modular multilevel matrix converter according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a method for controlling capacitor voltages of a modular multilevel matrix converter according to an embodiment of the invention;

fig. 5 is a schematic structural diagram of a device for controlling capacitor voltage of a modular multilevel matrix converter according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a schematic flow chart of a method for controlling a capacitor voltage of a modular multilevel matrix converter according to an embodiment of the present invention, including:

and S11, uniformly dividing the capacitance of the sub-modules in the bridge arm of the modular multilevel matrix converter into a first sub-module capacitance and a second sub-module capacitance.

Referring to fig. 2, a schematic structural diagram of a modular multilevel matrix converter according to an embodiment of the present invention includes e_u,e_vAnd e_wRespectively representing three-phase voltages on the divider system side, e_a,e_bAnd e_cRespectively representing three-phase voltage at power frequency side, the modular multilevel matrix converter has 9 bridge arms, and the bridge arms are named according to the connected end points, such as connection e_uAnd e_aThe leg of (a) is named leg ua. Each bridge arm is provided with N series submodules and a reactor.

Referring to fig. 3, which is a schematic structural diagram of a sub-module circuit in a bridge arm of the modular multilevel matrix converter according to an embodiment of the present invention, the series sub-module circuit in the bridge arm of the modular multilevel matrix converter is a single-phase full-bridge rectifier circuit, and includes 4 insulated gate bipolar transistors (IGBT1, IGBT 2, IGBT 3, and IGBT 4), 4 diodes connected in anti-parallel with the insulated gate bipolar transistors (D1, D2, D3, and D4), and a capacitor C. All the amounts of current are in the prescribed positive direction as indicated in fig. 3. For example, as shown in fig. 3, when the IGBT1 and the IGBT 4 are controlled to be turned on, the terminal voltage of the submodule is equal to Uc, and if the bridge arm current i is a forward current, the capacitor will be charged. Conversely, if the sign of the bridge arm current i is negative at this time, the capacitor will discharge. When the IGBT 2 and IGBT 3 are turned on, the terminal voltage of the sub-module is equal to-Uc. If the sign of current i is positive then the capacitor will discharge, and if the sign of current i is negative then the capacitor will charge.

Preferably, in the embodiment, the number of the sub-modules in the bridge arm of the modular multilevel matrix converter is N, where N is an even number, that is, the number of the levels is an odd number, and the sub-module capacitors in each bridge arm are divided into two groups, each group includes N/2 sub-modules, so that the number of the first sub-module capacitors is N/2, and the number of the second sub-module capacitors is N/2. The algorithm divides the sub-module capacitors on each bridge arm into two groups in advance, sequences the two groups of sub-module capacitor voltages in two periods of bridge arm current respectively, controls the balance of the first group of capacitor voltages in the first period, and controls the second group in the second period.

And S12, when the condition that the period of the bridge arm current is an odd period is detected, the logic operation unit based on the FPGA sequences the first sub-module capacitor in parallel in two preset clock periods according to the voltage of the first sub-module capacitor, and controls the insulated gate bipolar transistor of the sub-module to act according to the direction of the bridge arm current and a first modulation result, so that the capacitor of the sub-module is charged or discharged.

Specifically, when the period of the bridge arm current is detected to be an odd period, in a first clock period, the voltages of the first sub-module capacitors are compared pairwise based on the logic operation unit of the FPGA to obtain a first sub-module capacitor voltage comparison value;

and in the second clock period, calculating the voltage comparison value of the first sub-module capacitor based on the logic operation unit of the FPGA, and sequencing the voltages of the first sub-module capacitors from large to small according to the calculation result.

It can be understood that, the comparator based on the FPGA compares the voltages of the N/2 first sub-module capacitors two by two to obtain the first sub-module capacitor voltage comparison values, the comparison value outputs of which can be defined as 0 and 1 respectively, and then the adder based on the FPGA accumulates the obtained first sub-module capacitor voltage comparison values to obtain the sequence of the voltages of the first sub-module capacitors in the N/2 capacitor voltages. The two-to-two comparison between the voltages can be carried out in the FPGA at the same time, only the time of one clock is needed, and the time of accumulated calculation of output results is added, so that the sequencing can be realized by only 2 clock periods in total. The parallel sequencing method can complete sequencing of the capacitor voltage of the sub-modules on each bridge arm of the modular multilevel matrix converter in two clock periods, sequencing time is not increased along with the increase of the number of the sub-modules, real-time performance is good, and actual engineering requirements can be met. However, the parallel sorting method has high requirements on operation resources, and the comparators and adders which need to be used increase with the increase of the number of the sub-modules, so that the parallel sorting method is a sorting method which uses space to replace time, and can exert the advantage of abundant logic element resources of the FPGA.

In consideration of the possibility of the capacitor voltages being equal, the same voltage is defined in the order of priority as to which is in front of the bridge arm. Therefore, when performing the comparison, it is necessary to change the type of the comparator according to the order of the two capacitances in the bridge arm. By way of example, U will be_mComparing with other capacitor voltage, when going to sum U_nWhen comparing, if m>n, selecting a comparator of ≧ to judge U_m≥U_nIf true, 1 is output, if false, 0 is output, if m is output<n, selected ">"comparator, i.e. judgment U_m>U_nIf true, 1 is output, and if false, 0 is output.

Further, in response to a modulation instruction of the modular multilevel matrix converter, the number of sub-modules outputting a positive level in a single bridge arm of the modular multilevel matrix converter after modulation is used as a first modulation result, and the relationship between the number of sub-modules outputting the positive level and the number of capacitors of the first sub-module is judged according to the first modulation result.

And the first modulation result is the number of sub-modules which output positive levels in a single bridge arm after the modular multilevel matrix converter is modulated when the period of the bridge arm current is an odd period.

Fig. 4 is a schematic diagram of a method for controlling the capacitor voltage of the modular multilevel matrix converter according to an embodiment of the present invention.

It can be understood that after the function of capacitor-voltage balance of the sub-modules in the bridge arm of the modular multilevel matrix converter is enabled, the control system counts the current period of the bridge arm, and only sorts the capacitors of the first group of sub-modules in the odd period of the bridge arm current, and only sorts the capacitors of the second group of sub-modules in the even period of the bridge arm current.

Preferably, in an odd cycle of the bridge arm current, when the modulation result is that N sub-modules output a positive level and the remaining sub-modules output a negative level, when the number of sub-modules outputting the positive level is not greater than the number of the first sub-module capacitors, that is, N is equal to or less than N/2, the following operations are performed:

in an optional embodiment, when it is determined that the number of sub-modules outputting positive levels is not greater than the number of capacitors of the first sub-module and the direction of the bridge arm current is detected to be positive, the igbt of the sub-modules is controlled to operate, so that capacitors which are sequenced to be the last n bits in the capacitors of the first sub-module are in a charging state, and the capacitors of the remaining first sub-module and the capacitors of the second sub-module are in a discharging state; and N is more than 0 and less than or equal to N, wherein N is the number of sub-modules outputting the positive level, and N is the number of capacitors of the sub-modules in the bridge arm of the modular multilevel matrix converter.

In another optional embodiment, when it is determined that the number of the sub-modules outputting the positive level is not greater than the number of the first sub-module capacitors and it is detected that the direction of the bridge arm current is negative, the igbt of the sub-modules is controlled to operate, so that the capacitors in the first sub-module capacitors, which are sorted into the first n bits, are in a discharge state, and the other capacitors of the first sub-module capacitors and the second sub-module capacitors are in a charge state.

Preferably, in odd cycles of the bridge arm current, when the modulation result is that N sub-modules output a positive level and the remaining sub-modules output a negative level, when the number of sub-modules outputting the positive level is greater than the number of first sub-module capacitors, that is, N > N/2, the following operations are performed:

in an optional embodiment, when it is determined that the number of sub-modules outputting positive levels is greater than the number of capacitors of the first sub-module and the direction of the bridge arm current is detected to be positive, the igbt of the sub-modules is controlled to operate, so that the capacitors in the first sub-module, which are sequenced to be the first N-N bits, are in a discharge state, and the capacitors of the remaining first sub-module and the capacitors of the second sub-module are in a charge state.

In another optional embodiment, when it is determined that the number of the sub-modules outputting the positive level is greater than the number of the first sub-module capacitors and it is detected that the direction of the bridge arm current is negative, the igbt of the sub-modules is controlled to operate, so that the capacitors in the first sub-module capacitors, which are sequenced into the last N-N bits, are in a charging state, and the other capacitors of the first sub-module capacitors and the second sub-module capacitors are in a discharging state.

The operation of controlling the insulated gate bipolar transistor of the submodule in the bridge arm of the modular multilevel matrix converter to act can be understood as the operation of charging or discharging the capacitor by controlling the insulated gate bipolar transistor to be turned off or turned on.

And S13, when the period of the bridge arm current is detected to be an even period, based on the logic operation unit of the FPGA, the capacitors of the second sub-modules are sequenced in parallel in the two preset clock periods according to the voltage of the capacitors of the second sub-modules, and the insulated gate bipolar transistors of the sub-modules are controlled to act according to the direction of the bridge arm current and a second modulation result, so that the capacitors of the sub-modules are charged or discharged.

It can be understood that when the current cycle of the current bridge arm is detected to be an even cycle, the control principle is the same as that of the odd cycle.

Specifically, when the period of the bridge arm current is detected to be an even period, in a first clock period, the voltage of the second sub-module capacitor is compared pairwise based on the logic operation unit of the FPGA to obtain a second sub-module capacitor voltage comparison value;

And the second modulation result is the number of sub-modules which output positive levels in a single bridge arm after the modular multilevel matrix converter is modulated when the period of the bridge arm current is an even period.

Preferably, in even cycles of the bridge arm current, when the modulation result is that N sub-modules output a positive level and the remaining sub-modules output a negative level, when the number of sub-modules outputting the positive level is not greater than the number of first sub-module capacitors, that is, N is less than or equal to N/2, the following operations are performed:

in an optional embodiment, when it is determined that the number of sub-modules outputting positive levels is not greater than the number of capacitors of the second sub-module and the direction of the bridge arm current is detected to be positive, the igbt of the sub-modules is controlled to operate, so that capacitors which are sequenced to be the last n bits in the capacitors of the second sub-module are in a charging state, and the capacitors of the remaining second sub-module and the capacitors of the first sub-module are in a discharging state; and N is more than 0 and less than or equal to N, wherein N is the number of sub-modules outputting the positive level, and N is the number of capacitors of the sub-modules in the bridge arm of the modular multilevel matrix converter.

In another optional embodiment, when it is determined that the number of the sub-modules outputting the positive level is not greater than the number of the capacitors of the second sub-module and it is detected that the direction of the bridge arm current is negative, the igbt of the sub-module is controlled to operate, so that the capacitors in the second sub-module, which are sorted into the first n bits, are in a discharge state, and the capacitors of the remaining second sub-module and the capacitors of the first sub-module are in a charge state.

Preferably, in even cycles of the bridge arm current, when the modulation result is that N sub-modules output a positive level and the remaining sub-modules output a negative level, when the number of sub-modules outputting the positive level is greater than the number of first sub-module capacitors, that is, m > N/2, the following operations are performed:

in an optional embodiment, when it is determined that the number of sub-modules outputting positive levels is greater than the number of capacitors of the second sub-module and the direction of the bridge arm current is detected to be positive, the igbt of the sub-modules is controlled to operate, so that capacitors, which are sequenced to be the first N-N bits, in the capacitors of the second sub-module are in a discharge state, and the capacitors of the remaining second sub-module and the capacitors of the first sub-module are in a charge state.

In another optional embodiment, when it is determined that the number of the sub-modules outputting the positive level is greater than the number of the second sub-module capacitors and it is detected that the direction of the bridge arm current is negative, the igbt of the sub-modules is controlled to operate, so that the capacitors in the second sub-module capacitors, which are sequenced into the last N-N bits, are in a charging state, and the other capacitors of the second sub-module and the first sub-module capacitors are in a discharging state.

The method for controlling the capacitance and voltage of the modular multilevel matrix converter provided by the embodiment of the invention comprises the steps of uniformly dividing the capacitance of sub-modules in a bridge arm of the modular multilevel matrix converter into a first sub-module capacitance and a second sub-module capacitance, when the period of bridge arm current is detected to be an odd number period, carrying out parallel sequencing on the first sub-module capacitance in two preset clock periods according to the voltage of the first sub-module capacitance based on a logic operation unit of an FPGA, controlling the action of an insulated gate bipolar transistor of the sub-modules according to the direction of the bridge arm current and a first modulation result so as to charge or discharge the capacitance of the sub-modules, when the period of the bridge arm current is detected to be an even number period, carrying out parallel sequencing on the second sub-module capacitance in two preset clock periods according to the voltage of the second sub-module capacitance based on the logic operation unit of the FPGA, and according to the direction of the bridge arm current and a second modulation result, the action of the insulated gate bipolar transistor of the submodule is controlled, so that the capacitor of the submodule is charged or discharged, the parallel sequencing mode is adopted, the sequencing speed can be effectively improved, the real-time performance is good, the operation resource of an FPGA (field programmable gate array) can be effectively saved, the cost is reduced, the problem of unbalanced capacitor voltage of the submodule in the bridge arm in the modulation process of the modular multilevel matrix converter can be effectively solved, and the normal operation of the modular multilevel matrix converter is ensured.

In another preferred embodiment, on the basis of the above embodiments, the control method of the capacitor voltage of the modular multilevel matrix converter is applied to an actual circuit.

Suppose that each bridge arm of the modular multilevel matrix converter is provided with 8 sub-modules, respectively SM₀～SM₇Their capacitor voltages are respectively U_c0～U_c7The sub-modules are divided into two groups, U respectively_c0～U_c3And U_c4～U_c7. After the function of enabling the sub-module to balance the capacitance and the voltage is started, in the first period of the bridge arm current, U is paired_c0～U_c3And performing parallel sorting. The specific sorting method is as follows:

in the first clock cycle of FPGA, firstly, U is processed_c0～U_c3And (4) carrying out pairwise comparison:

//U_c0comparison with other capacitor voltages

If(U_c0>U_c1)x₀₀＝0；else x₀₀＝1；

If(U_c0>U_c2)x₀₁＝0；else x₀₁＝1；

If(U_c0>U_c3)x₀₂＝0；else x₀₂＝1；

// Uc1 comparison with other capacitor voltages

If(U_c1≥U_c0)x₁₀＝0；else x₁₀＝1；

If(U_c1>U_c2)x₁₁＝0；else x₁₁＝1；

If(U_c1>U_c3)x₁₂＝0；else x₁₂＝1；

......

//U_c3Comparison with other capacitor voltages

If(U_c3≥U_c0)x₃₀＝0；else x₃₀＝1；

If(U_c3≥U_c1)x₃₁＝0；else x₃₁＝1；

If(U_c3≥U_c2)x₃₂＝0；else x₃₂＝1.

And accumulating the comparison values in the second clock period of the FPGA to obtain the position of each sub-module capacitor in the capacitor voltage.

X₀＝x₀₀+x₀₁+x₀₂；

X₁＝x₁₀+x₁₁+x₁₂；

X₂＝x₂₀+x₂₁+x₂₂；

X₃＝x₃₀+x₃₁+x₃₂.

The control method of the capacitor voltage of the modular multilevel matrix converter only needs 2 FPGA clock cycles to complete sequencing, and the operation time does not change along with the data volume. On the other hand, the method needs to occupy a large amount of processing space, namely, a large amount of FPGA logic units are used, and FPGA logic element resources are rich, so that the method is very suitable for the space-to-time sequencing algorithm.

After the control system finds that the first period of the bridge arm current is over by detecting the direction of the bridge arm current and the counting module, the control system starts to count the U_c4～U_c7The sorting is performed in the same way as above. Cycling in sequence, i.e. odd cycles of bridge arm current to U_c0～U_c3Sorting is performed, even cycles to U_c4～U_c7And (6) sorting.

The number of the sub-modules of the modular multilevel matrix converter applied to high-voltage large-capacity occasions is usually large, the sequencing method of the embodiment is shorter in time consumption than a traditional serial sequencing method (such as bubble sequencing) and the sequencing time is irrelevant to the data size, and the real-time requirement when the number of the sub-modules is large can be met. Compared with a full-comparison parallel sorting algorithm, the sorting method of the embodiment saves half of the required computing resources (FPGA logic units) and has better economy. Meanwhile, the traditional sorting algorithm-based submodule capacitor voltage balance control has a bridge arm current direction judging module, and the method can be realized only by adding a counting module and an odd-even number judging module in an FPGA source code.

Furthermore, the voltage balance of the modular multilevel matrix converter submodule capacitor is finally realized through the selective switching of the submodule. As shown in fig. 4, in odd cycles of the bridge arm current, when the modulation result is that n sub-modules output positive levels and the other sub-modules output negative levels, if n is less than or equal to 4 and the bridge arm current direction is positive, the IGBT is controlled to let the SM output₀～SM₃All of X in_iAnd the sub-module capacitors larger than or equal to n are in a charging state, and the other sub-module capacitors are in a discharging state. Otherwise, when the current direction of the bridge arm is negative, the IGBT is controlled to enable the SM₀～SM₃All of X in_iAnd the sub-module capacitors smaller than n are in a discharging state, and the other sub-module capacitors are in a charging state. If n is>4, when the current direction of the bridge arm is positive, controlling the IGBT to enable the SM₀～SM₃All of X in_iSub-module capacitance less than n-4And in a discharging state, the capacitors of the other sub-modules are in a charging state. Otherwise, when the current direction of the bridge arm is negative, the IGBT is controlled to enable the SM₀～SM₃All of X in_iAnd the sub-module capacitors which are larger than or equal to n-4 are in a charging state, and the other sub-module capacitors are in a discharging state.

As shown in fig. 4, in even cycles of the bridge arm current, when the modulation result is that n sub-modules output a positive level and the other sub-modules output a negative level, if n is less than or equal to 4 and the bridge arm current direction is positive, the IGBT is controlled to let the SM output₄～SM₇All of X in_iAnd the sub-module capacitors larger than or equal to n are in a charging state, and the other sub-module capacitors are in a discharging state. Otherwise, when the current direction of the bridge arm is negative, the IGBT is controlled to enable the SM₄～SM₇All of X in_iAnd the sub-module capacitors smaller than n are in a discharging state, and the other sub-module capacitors are in a charging state. If n is>4, when the current direction of the bridge arm is positive, controlling the IGBT to enable the SM₄～SM₇All of X in_iAnd the sub-module capacitor smaller than n-4 is in a discharging state, and the other sub-module capacitors are in a charging state. Otherwise, when the current direction of the bridge arm is negative, the IGBT is controlled to enable the SM₄～SM₇All of X in_iAnd the sub-module capacitors which are larger than or equal to n-4 are in a charging state, and the other sub-module capacitors are in a discharging state.

According to the method for controlling the capacitance voltage of the modular multilevel matrix converter, provided by the embodiment of the invention, a parallel sorting mode is adopted, compared with the traditional sorting method, the time consumption is short, the sorting time is irrelevant to the data volume, the real-time requirement when the number of sub-modules is large can be met, half of required computing resources (FPGA logic units) can be saved, the economy is better, the sorting speed can be effectively improved, the real-time performance is good, the cost is reduced, the problem of unbalanced capacitance voltage of sub-modules in a bridge arm in the modulation process of the modular multilevel matrix converter can be effectively solved, and the normal operation of the modular multilevel matrix converter is ensured.

Referring to fig. 5, a schematic structural diagram of a control apparatus for capacitor voltage of a modular multilevel matrix converter according to an embodiment of the present invention is shown, including:

the data dividing module 1 is used for uniformly dividing the capacitance of the sub-module in the bridge arm of the modular multilevel matrix converter into a first sub-module capacitance and a second sub-module capacitance;

the first data processing module 2 is configured to, when it is detected that the period of the bridge arm current is an odd-numbered period, perform parallel sequencing on the first sub-module capacitors within two preset clock periods according to the voltage of the first sub-module capacitors based on a logic operation unit of the FPGA, and control the insulated gate bipolar transistors of the sub-modules to operate according to the direction of the bridge arm current and a first modulation result, so as to perform charging or discharging operations on the capacitors of the sub-modules; when the period of the bridge arm current is an odd number period, the number of the submodules outputting a positive level in a single bridge arm after the modular multilevel matrix converter is modulated is the first modulation result;

the second data processing module 3 is configured to, when it is detected that the period of the bridge arm current is an even number of periods, perform parallel sequencing on the capacitors of the second sub-modules within the two preset clock periods according to the voltages of the capacitors of the second sub-modules based on the logic operation unit of the FPGA, and control the insulated gate bipolar transistors of the sub-modules to operate according to the direction of the bridge arm current and a second modulation result, so as to perform charging or discharging operations on the capacitors of the sub-modules; and the second modulation result is the number of sub-modules which output positive levels in a single bridge arm after the modular multilevel matrix converter is modulated when the period of the bridge arm current is an even period.

Preferably, the first data processing module 2 comprises:

the first comparison unit is used for comparing the voltages of the first sub-module capacitors pairwise in a first clock period based on the logic operation unit of the FPGA when the period of the bridge arm current is detected to be an odd period to obtain a first sub-module capacitor voltage comparison value;

the first calculation unit is used for calculating the voltage comparison value of the first sub-module capacitor based on the logic operation unit of the FPGA in a second clock cycle and sequencing the voltage of the first sub-module capacitor from large to small according to the calculation result;

and the first response unit is used for responding to a modulation instruction of the modular multilevel matrix converter, taking the number of sub-modules outputting positive levels in a single bridge arm of the modular multilevel matrix converter after modulation as a first modulation result, and judging the size relationship between the number of the sub-modules outputting the positive levels and the number of the first sub-module capacitors according to the first modulation result.

Further, the first data processing module 2 further includes:

the first judgment unit is used for controlling the insulated gate bipolar transistors of the submodules to act when the number of the submodules outputting the positive level is judged to be not more than the number of the first submodule capacitors and the direction of the bridge arm current is detected to be positive, so that the capacitors which are sequenced into the last n bits in the first submodule capacitors are in a charging state, and the rest capacitors of the first submodule and the second submodule capacitors are in a discharging state; n is more than 0 and less than or equal to N, wherein N is the number of sub-modules outputting the positive level, and N is the number of capacitors of sub-modules in a bridge arm of the modular multilevel matrix converter;

and the second judging unit is used for controlling the insulated gate bipolar transistor of the sub-module to act when the number of the sub-modules outputting the positive level is judged to be not more than the number of the first sub-module capacitors and the direction of the bridge arm current is detected to be negative, so that the capacitors which are sequenced to be the first n bits in the first sub-module capacitors are in a discharging state, and the rest of the first sub-module capacitors and the rest of the second sub-module capacitors are in a charging state.

Further, the first data processing module 2 further includes:

and the third judging unit is used for controlling the insulated gate bipolar transistors of the submodules to act when the number of the submodules outputting the positive level is judged to be larger than the number of the first submodule capacitors and the direction of the bridge arm current is detected to be positive, so that the capacitors which are sequenced into the first N-N bits in the first submodule capacitors are in a discharging state, and the rest of the first submodule capacitors and the rest of the second submodule capacitors are in a charging state.

And the fourth judging unit is used for controlling the insulated gate bipolar transistors of the sub-modules to act when the number of the sub-modules outputting the positive level is judged to be larger than the number of the first sub-module capacitors and the direction of the bridge arm current is detected to be negative, so that the capacitors with the last N-N bits in the first sub-module capacitors are in a charging state, and the rest of the first sub-module capacitors and the rest of the second sub-module capacitors are in a discharging state.

Preferably, the second data processing module 3 comprises:

the second comparison unit is used for comparing the voltages of the second sub-module capacitors in pairs based on the logic operation unit of the FPGA in a first clock cycle to obtain a second sub-module capacitor voltage comparison value when the period of the bridge arm current is detected to be an even period;

the second calculation unit is used for calculating the comparison value of the capacitor voltage of the second sub-module based on the logic operation unit of the FPGA in a second clock cycle and sequencing the voltage of the capacitor of the second sub-module from large to small according to the calculation result;

and the second response unit is used for responding to a modulation instruction of the modular multilevel matrix converter, using the number of sub-modules outputting positive levels in a single bridge arm of the modular multilevel matrix converter after modulation as a second modulation result, and judging the size relationship between the number of the sub-modules outputting the positive levels and the number of capacitors of the second sub-modules according to the second modulation result.

Preferably, the second data processing module 3 further comprises:

a fifth judging unit, configured to control an igbt of the sub-module to operate when it is judged that the number of sub-modules outputting the positive level is not greater than the number of capacitors of the second sub-module and it is detected that the direction of the bridge arm current is positive, so that capacitors of last n bits in the capacitors of the second sub-module are in a charging state, and capacitors of the remaining second sub-module and the capacitors of the first sub-module are in a discharging state; n is more than 0 and less than or equal to N, wherein N is the number of sub-modules outputting the positive level, and N is the number of capacitors of sub-modules in a bridge arm of the modular multilevel matrix converter;

and the sixth judging unit is used for controlling the insulated gate bipolar transistors of the submodules to act when the number of the submodules outputting the positive level is judged to be not more than the number of the capacitors of the second submodule and the direction of the bridge arm current is detected to be negative, so that the capacitors which are sequenced into the first n bits in the capacitors of the second submodule are in a discharging state, and the capacitors of the rest second submodules and the capacitors of the first submodule are in a charging state.

Preferably, the second data processing module 3 further comprises:

a seventh judging unit, configured to control an igbt of the sub-module to operate when it is judged that the number of sub-modules outputting the positive level is greater than the number of capacitors of the second sub-module and it is detected that the direction of the bridge arm current is positive, so that capacitors sorted into first N-N bits in the capacitors of the second sub-module are in a discharging state, and capacitors of the remaining second sub-module and the capacitors of the first sub-module are in a charging state;

and the eighth judging unit is used for controlling the insulated gate bipolar transistors of the submodules to act when the number of the submodules outputting the positive level is judged to be larger than the number of the second submodule capacitors and the direction of the bridge arm current is detected to be negative, so that the capacitors which are sequenced into the last N-N bits in the second submodule capacitors are in a charging state, and the rest of the second submodule capacitors and the first submodule capacitors are in a discharging state.

Fig. 5 is a schematic structural diagram of a control apparatus for capacitor voltage of a modular multilevel matrix converter according to an embodiment of the present invention. The control device for the capacitor voltage of the modular multilevel matrix converter of the embodiment comprises: a processor, a memory, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, to implement the steps in the above embodiments of the method for controlling the capacitor voltage of the modular multilevel matrix converter, for example, in step S12 shown in fig. 1, when it is detected that the current bridge arm current cycle is an odd cycle, the FPGA-based logic operation unit performs parallel sorting on the voltage of the first sub-module capacitor in two preset clock cycles, and controls the igbt of the sub-modules in the bridge arm of the modular multilevel matrix converter to operate according to the direction of the bridge arm current, so as to charge or discharge the sorted first sub-module capacitor. Or, the processor implements the functions of the modules/units in the embodiments of the apparatus when executing the computer program, for example, the first data processing module 2 is configured to, when it is detected that the current bridge arm current cycle is an odd cycle, perform parallel sequencing on the voltages of the capacitors of the first sub-modules in two preset clock cycles by using a logic operation unit based on an FPGA, and control the operation of the insulated gate bipolar transistors of the sub-modules in the bridge arm of the modular multilevel matrix converter according to the direction of the bridge arm current, so as to charge or discharge the capacitors of the first sub-modules after sequencing.

Illustratively, the computer program may be partitioned into one or more modules/units that are stored in the memory and executed by the processor to implement the invention. The one or more modules/cells may be a series of computer program instruction segments capable of performing a specific function for describing the execution of the computer program in the control apparatus of the capacitor voltage of the modular multilevel matrix converter.

The control device of the capacitance voltage of the modular multilevel matrix converter can be computing equipment such as a desktop computer, a notebook computer, a palm computer and a cloud server. The control device of the capacitor voltage of the modular multilevel matrix converter can comprise, but is not limited to, a processor and a memory. It will be appreciated by a person skilled in the art that the schematic diagram is merely an example of a control arrangement for the capacitor voltage of the modular multilevel matrix converter and does not constitute a limitation of the control arrangement for the capacitor voltage of the modular multilevel matrix converter, and may comprise more or less components than those shown, or some components in combination, or different components, for example, the control arrangement for the capacitor voltage of the modular multilevel matrix converter may further comprise input and output devices, network access devices, buses, etc.

The Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, the processor is a control center of the control device of the capacitor voltage of the modular multilevel matrix converter, and various interfaces and lines are used for connecting various parts of the control device of the capacitor voltage of the whole modular multilevel matrix converter.

The memory may be used for storing the computer program and/or the module, and the processor may implement various functions of the control device of the capacitor voltage of the modular multilevel matrix converter by operating or executing the computer program and/or the module stored in the memory and calling the data stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the cellular phone, and the like. In addition, the memory may include high speed random access memory, and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other volatile solid state storage device.

Wherein, the module/unit integrated by the control device of the capacitance voltage of the modular multilevel matrix converter can be stored in a computer readable storage medium if the module/unit is realized in the form of a software functional unit and is sold or used as an independent product. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method embodiments may be implemented. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.

It should be noted that the above-described device embodiments are merely illustrative, where the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. In addition, in the drawings of the embodiment of the apparatus provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, and may be specifically implemented as one or more communication buses or signal lines. One of ordinary skill in the art can understand and implement it without inventive effort.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.

Claims

1. A method for controlling the capacitor voltage of a modular multilevel matrix converter is characterized by comprising the following steps:

2. The method according to claim 1, wherein when the period of the detected bridge arm current is an odd-numbered period, the FPGA-based logic operation unit performs parallel sequencing on the first sub-module capacitor according to the voltage of the first sub-module capacitor in two preset clock periods, specifically comprising:

3. The method according to claim 2, wherein when the period of the bridge arm current is detected to be an odd period, the FPGA-based logic operation unit sequences the first sub-module capacitor in parallel for two preset clock periods according to the voltage of the first sub-module capacitor, and controls the igbt of the sub-module to operate according to the direction of the bridge arm current and the first modulation result, so as to charge or discharge the capacitor of the sub-module, specifically comprising:

4. A method of controlling capacitor voltage of a modular multilevel matrix converter according to claim 3, the method further comprising:

5. The method according to claim 1, wherein when the period of the bridge arm current is detected to be an even number period, the step of sorting the second sub-module capacitors in parallel in the preset two clock periods according to the voltages of the second sub-module capacitors based on a logic operation unit of the FPGA according to the voltage of the second sub-module capacitors comprises:

6. The method according to claim 5, wherein when it is detected that the period of the bridge arm current is an even number, the method, based on the logic operation unit of the FPGA, performs parallel sorting on the second sub-module capacitance according to the voltage of the second sub-module capacitance in the preset two clock periods, and controls the igbt of the sub-module to operate according to the direction of the bridge arm current and the second modulation result, so as to charge or discharge the capacitance of the sub-module, specifically comprises:

7. The method of controlling capacitor voltages of a modular multilevel matrix converter according to claim 6, the method further comprising:

8. A control device for capacitor voltage of a modular multilevel matrix converter is characterized by comprising:

9. An apparatus for controlling a capacitor voltage of a modular multilevel matrix converter, comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, the processor implementing the method of controlling a capacitor voltage of a modular multilevel matrix converter according to any of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, comprising a stored computer program, wherein the computer program, when executed, controls an apparatus in which the computer-readable storage medium is located to perform the method for controlling capacitor voltages of a modular multilevel matrix converter according to any of claims 1 to 7.