CN109889052A - A kind of control method and device of modular multilevel matrix inverter capacitance voltage - Google Patents
A kind of control method and device of modular multilevel matrix inverter capacitance voltage Download PDFInfo
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Abstract
The invention discloses a kind of control method and device of modular multilevel matrix inverter capacitance voltage, it include: that the capacitor of submodule in modular multilevel matrix converter bridge arm is evenly dividing as the first submodule capacitor and second submodule capacitor, when the period for detecting bridge arm current is odd cycle, logical unit based on FPGA, sorting in parallel is carried out within preset two clock cycle to the first submodule capacitor according to the voltage of the first submodule capacitor, and according to the direction of the bridge arm current and the first modulation result, control the insulated gate bipolar transistor movement of the submodule, so as to carry out the operation of charge or discharge to the capacitor of the submodule, it can effectively solve the unbalanced problem of submodule capacitor voltage in modular multilevel matrix inverter modulated process bridge arm, it can effectively improve The speed of sort algorithm saves the calculation resources of FPGA, so as to which the normal operation of modular multilevel matrix inverter is effectively ensured.
Description
Technical field
The present invention relates to power electronic devices control technology field more particularly to a kind of modular multilevel matrix inverters
The control method and device of capacitance voltage.
Background technique
Modular multilevel matrix inverter (MMMC) is a kind of new type inverter, and the bidirectional flow of power may be implemented in it
It is dynamic, in terms of the frequency conversion (such as Fractional Frequency Power Transmission System) and mesohigh motor driven that are used primarily between AC system.Compared with
Traditional matrix inverter, the application of modular technology improve the scalability and resistance to voltage levels of device.Due to using full control
Switch, it is that a kind of performance is very excellent that when MMMC is used for Fractional Frequency Power Transmission System, the harmonic wave of generation is less, and is not necessarily to reactive compensation
Good frequency converter.
In the prior art due to following two points: first is that the on-off moment of each submodule IGBT is not exactly the same；Second is that even if
To with a batch of device, their circuit parameter will not be identical, so the loss of each submodule can have differences, respectively
The power that submodule provides is also not exactly the same.Lead to be likely to occur in bridge arm submodule capacitor voltage in MMMC modulated process not
Balance, although at this time control system guarantee submodule capacitor average voltage be always maintained at it is constant, between each submodule
Voltage difference can be increasing, and finally influences the normal operation of MMMC.
Summary of the invention
The embodiment of the present invention provides a kind of control method and device of modular multilevel matrix inverter capacitance voltage, energy
Effectively solve the problems, such as that submodule capacitor voltage is unbalanced in modular multilevel matrix inverter modulated process bridge arm, can have
Effect improves the speed of sort algorithm, the calculation resources of FPGA is saved, so as to which modular multilevel matrix inverter is effectively ensured
Normal operation.
One embodiment of the invention provides a kind of control method of modular multilevel matrix inverter capacitance voltage, comprising:
The capacitor of submodule in modular multilevel matrix converter bridge arm is evenly dividing as the first submodule capacitor and
Second submodule capacitor；
When the period for detecting bridge arm current is odd cycle, the logical unit based on FPGA, according to described the
The voltage of one submodule capacitor carries out sorting in parallel, and root within preset two clock cycle to the first submodule capacitor
Direction and the first modulation result according to the bridge arm current control the insulated gate bipolar transistor movement of the submodule, with
Make the operation that charge or discharge are carried out to the capacitor of the submodule；
When the period for detecting the bridge arm current is even cycle, based on the logical unit of the FPGA, press
The second submodule capacitor is carried out within preset two clock cycle according to the voltage of the second submodule capacitor
Sorting in parallel, and according to the direction of the bridge arm current and the second modulation result, control the insulated gate bipolar of the submodule
Transistor action, so as to carry out the operation of charge or discharge to the capacitor of the submodule.
Preferably, described when the period for detecting bridge arm current is odd cycle, the logical unit based on FPGA,
The first submodule capacitor is carried out simultaneously within preset two clock cycle according to the voltage of the first submodule capacitor
Row sequence, specifically includes:
When the period for detecting the bridge arm current is odd cycle, within first clock cycle, it is based on institute
The logical unit for stating FPGA compares the voltage of the first submodule capacitor two-by-two, obtains the first submodule capacitor
Voltage fiducial value；
Within second clock cycle, the logical unit based on the FPGA is to the first submodule capacitor
Voltage fiducial value is calculated, and according to calculated result, by the voltage of the first submodule capacitor by arranging from big to small
Sequence；
In response to the modulation instructions of the modular multilevel matrix inverter, by modular multilevel square described after modulation
Battle array inverter individually adjust as the first modulation result, and according to described first by the interior submodule quantity for exporting positive level of the bridge arm
System is as a result, judge the size relation of the submodule quantity of the output positive level and the quantity of the first submodule capacitor.
Preferably, described when the period for detecting bridge arm current is odd cycle, the logical unit based on FPGA,
The first submodule capacitor is carried out simultaneously within preset two clock cycle according to the voltage of the first submodule capacitor
Row sequence, and according to the direction of the bridge arm current and the first modulation result, the insulated gate bipolar for controlling the submodule is brilliant
The movement of body pipe specifically includes so as to carry out the operation of charge or discharge to the capacitor of the submodule:
When the submodule quantity for determining the output positive level is not more than the quantity of the first submodule capacitor, and inspection
The direction for measuring the bridge arm current is timing, the insulated gate bipolar transistor movement of the submodule is controlled, so that described
It is ordered as rear n of capacitor in first submodule capacitor and is in charged state, remaining described first submodule capacitor and described
Two submodule capacitors are in discharge condition；Wherein, 0 < n≤N, n are the submodule quantity of the output positive level, and N is the mould
The capacitor quantity of submodule in block multi-level matrix converter bridge arm；
When the submodule quantity for determining the output positive level is not more than the quantity of the first submodule capacitor, and inspection
When measuring the direction of the bridge arm current and being negative, the insulated gate bipolar transistor movement of the submodule is controlled, so that described
N capacitors are in discharge condition before being ordered as in first submodule capacitor, remaining described first submodule capacitor and described the
Two submodule capacitors are in charged state.
Preferably, the method also includes:
When the submodule quantity for determining the output positive level is greater than the quantity of the first submodule capacitor, and detection
It is timing to the direction of the bridge arm current, the insulated gate bipolar transistor movement of the submodule is controlled, so that described the
N-n capacitors are in discharge condition before being ordered as in one submodule capacitor, remaining described first submodule capacitor and described the
Two submodule capacitors are in charged state；
When the submodule quantity for determining the output positive level is greater than the quantity of the first submodule capacitor, and detection
When being negative to the direction of the bridge arm current, the insulated gate bipolar transistor of control submodule is acted, so that first son
It is ordered as rear N-n of capacitor in module capacitance and is in charged state, remaining described first submodule capacitor and second son
Module capacitance is in discharge condition.
Preferably, described when the period for detecting the bridge arm current is even cycle, the logic based on the FPGA
Arithmetic element, according to the voltage of the second submodule capacitor to the second submodule capacitor in preset two clocks
Sorting in parallel is carried out in period, is specifically included:
When the period for detecting the bridge arm current is even cycle, within first clock cycle, it is based on institute
The logical unit for stating FPGA compares the voltage of the second submodule capacitor two-by-two, obtains second submodule capacitor
Voltage fiducial value；
Within second clock cycle, the logical unit based on the FPGA is to the second submodule capacitor
Voltage fiducial value is calculated, and according to calculated result, by the voltage of the second submodule capacitor by arranging from big to small
Sequence；
In response to the modulation instructions of the modular multilevel matrix inverter, by modular multilevel square described after modulation
Battle array inverter individually adjust as the second modulation result, and according to described second by the interior submodule quantity for exporting positive level of the bridge arm
System is as a result, judge the size relation of the submodule quantity of the output positive level and the quantity of the second submodule capacitor.
Preferably, described when the period for detecting the bridge arm current is even cycle, the logic based on the FPGA
Arithmetic element, according to the voltage of the second submodule capacitor to the second submodule capacitor in preset two clocks
Sorting in parallel is carried out in period, and according to the direction of the bridge arm current and the second modulation result, controls the exhausted of the submodule
The movement of edge grid bipolar junction transistor specifically includes so as to carry out the operation of charge or discharge to the capacitor of the submodule:
When the submodule quantity for determining the output positive level is not more than the quantity of the second submodule capacitor, and inspection
The direction for measuring the bridge arm current is timing, the insulated gate bipolar transistor movement of the submodule is controlled, so that described
It is ordered as rear n of capacitor in second submodule capacitor and is in charged state, remaining described second submodule capacitor and described
One submodule capacitor is in discharge condition；Wherein, 0 < n≤N, n are the submodule quantity of the output positive level, and N is the mould
The capacitor quantity of submodule in block multi-level matrix converter bridge arm；
When the submodule quantity for determining the output positive level is not more than the quantity of the second submodule capacitor, and inspection
When measuring the direction of the bridge arm current and being negative, the insulated gate bipolar transistor movement of the submodule is controlled, so that described
N capacitors are in discharge condition before being ordered as in second submodule capacitor, remaining described second submodule capacitor and described the
One submodule capacitor is in charged state.
Preferably, the method also includes:
When the submodule quantity for determining the output positive level is greater than the quantity of the second submodule capacitor, and detection
It is timing to the direction of the bridge arm current, the insulated gate bipolar transistor movement of the submodule is controlled, so that described the
N-n capacitors are in discharge condition before being ordered as in two submodule capacitors, remaining described second submodule capacitor and described the
One submodule capacitor is in charged state；
When the submodule quantity for determining the output positive level is greater than the quantity of the second submodule capacitor, and detection
When being negative to the direction of the bridge arm current, the insulated gate bipolar transistor movement of the submodule is controlled, so that described the
It is ordered as rear N-n of capacitor in two submodule capacitors and is in charged state, remaining described second submodule capacitor and described
One submodule capacitor is in discharge condition.
Another embodiment of the present invention is corresponding to provide a kind of control dress of modular multilevel matrix inverter capacitance voltage
It sets, comprising:
Data division module, for by the capacitor of submodule in modular multilevel matrix converter bridge arm be evenly dividing for
First submodule capacitor and second submodule capacitor；
First data processing module, for when detect bridge arm current period be odd cycle when, patrolling based on FPGA
Arithmetic element is collected, according to the voltage of the first submodule capacitor to the first submodule capacitor in preset two clock weeks
Sorting in parallel is carried out in phase, and according to the direction of the bridge arm current and the first modulation result, controls the insulation of the submodule
Grid bipolar junction transistor movement, so as to carry out the operation of charge or discharge to the capacitor of the submodule；
Second data processing module, for being based on described when the period for detecting the bridge arm current is even cycle
The logical unit of FPGA, according to the voltage of the second submodule capacitor to the second submodule capacitor described default
Two clock cycle in carry out sorting in parallel, and according to the direction of the bridge arm current and the second modulation result, described in control
The insulated gate bipolar transistor of submodule acts, so as to carry out the operation of charge or discharge to the capacitor of the submodule.
Compared with prior art, the control of modular multilevel matrix inverter capacitance voltage disclosed by the embodiments of the present invention
Method and device, by being evenly dividing the capacitor of submodule in modular multilevel matrix converter bridge arm for the first submodule
Capacitor and second submodule capacitor, when the period for detecting bridge arm current is odd cycle, the logical operation list based on FPGA
Member carries out the first submodule capacitor according to the voltage of the first submodule capacitor within preset two clock cycle
Sorting in parallel, and according to the direction of the bridge arm current and the first modulation result, control the insulated gate bipolar of the submodule
Transistor action, so as to carry out the operation of charge or discharge to the capacitor of the submodule, when detecting the bridge arm current
When period is even cycle, based on the logical unit of the FPGA, according to the voltage of the second submodule capacitor to institute
It states second submodule capacitor and carries out sorting in parallel within preset two clock cycle, and according to the side of the bridge arm current
To with the second modulation result, control the submodule insulated gate bipolar transistor movement so as to the electricity of the submodule
The operation for holding progress charge or discharge can effectively improve the speed of sequence, and real-time is good, energy by the way of sorting in parallel
The calculation resources of effectively save FPGA reduce cost, and then can effectively solve modular multilevel matrix inverter modulated process
The unbalanced problem of submodule capacitor voltage in bridge arm guarantees the normal operation of modular multilevel matrix inverter.
Another embodiment of the present invention provides a kind of control device of modular multilevel matrix inverter capacitance voltage, packets
It includes processor, memory and storage in the memory and is configured as the computer program executed by the processor,
The processor realizes modular multilevel matrix inverter described in foregoing invention embodiment when executing the computer program
The control method of capacitance voltage.
Another embodiment of the present invention provides a kind of storage medium, the computer readable storage medium includes the meter of storage
Calculation machine program, wherein control equipment where the computer readable storage medium in computer program operation and execute
State the control method of modular multilevel matrix inverter capacitance voltage described in inventive embodiments.
Detailed description of the invention
Fig. 1 is a kind of control method for modular multilevel matrix inverter capacitance voltage that one embodiment of the invention provides
Flow diagram；
Fig. 2 is the structural schematic diagram for the modular multilevel matrix inverter that one embodiment of the invention provides；
Fig. 3 is the structure of submodular circuits in the modular multilevel matrix converter bridge arm of one embodiment of the invention offer
Schematic diagram；
Fig. 4 is the control method signal for the modular multilevel matrix inverter capacitance voltage that one embodiment of the invention provides
Figure；
Fig. 5 is a kind of control device for modular multilevel matrix inverter capacitance voltage that one embodiment of the invention provides
Structural schematic diagram.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
It is a kind of control for modular multilevel matrix inverter capacitance voltage that one embodiment of the invention provides referring to Fig. 1
The flow diagram of method, comprising:
S11, the capacitor of submodule in modular multilevel matrix converter bridge arm is evenly dividing as the first submodule electricity
Hold and second submodule capacitor.
It referring to fig. 2, is the structural schematic diagram for the modular multilevel matrix inverter that one embodiment of the invention provides, including
eu,evAnd ewRespectively represent the three-phase voltage of frequency division system side, ea,ebAnd ecPower frequency side three-phase voltage is respectively represented, modularization is more
Level matrix inverter has 9 bridge arms, and bridge arm is named according to the endpoint that it is connected, and such as connects euAnd eaBridge arm ordered
Entitled bridge arm ua.Wherein, each bridge arm has N number of series connection submodule and a reactor.
It is submodular circuits in the modular multilevel matrix converter bridge arm of one embodiment of the invention offer referring to Fig. 3
Structural schematic diagram, series connection submodular circuits are a single-phase full bridge rectified currents in modular multilevel matrix converter bridge arm
Road, including 4 insulated gate bipolar transistors (IGBT1, IGBT 2, IGBT 3 and IGBT4), 4 antiparallel two poles therewith
Manage (D1, D2, D3 and D4) and a capacitor C.The direction that all magnitudes of current such as Fig. 3 is indicated is defined positive direction.Its
In, end or be connected the behaviour realized to the charge or discharge of capacitor by the insulated gate bipolar transistor of control submodule
Make, as an example, as shown in Figure 3 when controlling IGBT 1 and IGBT 4 conducting, the end voltage of submodule is equal to Uc, if at this time
Bridge arm current i is forward current, and capacitor will be electrically charged.On the contrary, capacitor will if the symbol of bridge arm current i is negative at this time
Electric discharge.When IGBT 2 and IGBT 3 is connected, the end voltage of submodule is equal to-Uc.If the symbol of electric current i is positive at this time, electricity
Holding will discharge, if the symbol of electric current i is negative at this time, capacitor will charge.
Preferably, the submodule quantity N in the present embodiment in modular multilevel matrix converter bridge arm, and N is even number,
I.e. level number is odd number, and the submodule capacitor in each bridge arm is divided into two groups, and every group of N/2 is a, therefore, the first submodule capacitor
Quantity is N/2, and second submodule capacitor quantity is N/2.Submodule capacitor on each bridge arm is divided into two groups in advance by the algorithm,
This two groups of submodule capacitor voltages are ranked up respectively within two periods of bridge arm current, control first in a cycle
The balance of capacitance voltage is organized, then controls second group in second period, this mode is compared to the parallel sorting algorithm compared entirely
Required fpga logic arithmetic element can be reduced into half or so.
S12, when detect bridge arm current period be odd cycle when, the logical unit based on FPGA, according to institute
The voltage for stating the first submodule capacitor carries out sorting in parallel within preset two clock cycle to the first submodule capacitor,
And according to the direction of the bridge arm current and the first modulation result, the insulated gate bipolar transistor for controlling the submodule is dynamic
Make, so as to carry out the operation of charge or discharge to the capacitor of the submodule.
Specifically, when the period for detecting the bridge arm current is odd cycle, within first clock cycle,
Logical unit based on the FPGA compares the voltage of the first submodule capacitor two-by-two, obtains the first submodule
Block capacitance voltage fiducial value；
Within second clock cycle, the logical unit based on the FPGA is to the first submodule capacitor
Voltage fiducial value is calculated, and according to calculated result, by the voltage of the first submodule capacitor by arranging from big to small
Sequence.
It is appreciated that the comparator based on FPGA, the voltage of N/2 the first submodule capacitors is first compared two-by-two,
The first submodule capacitor voltage fiducial value is obtained, the fiducial value output that can define them is respectively 0 and 1, is then based on FPGA
Adder the first submodule capacitor voltage fiducial value obtained to these add up, the first submodule capacitor can be obtained
Sequence of the voltage in N/2 capacitance voltage.Wherein, comparing between voltage two-by-two in FPGA while can carry out, it is only necessary to
The time of one clock only needs 2 clock cycle to can be achieved with arranging in total along with the time of output result accumulation calculating
Sequence.The sorting in parallel method of use can be completed within two clock cycle to each bridge arm of modular multilevel matrix inverter
The sequence of upper submodule capacitor voltage, sorting time do not increase with the increase of submodule quantity, and real-time is good, can satisfy
Actual requirement of engineering.But requirement of the sorting in parallel method to calculation resources is very high, and the comparator and adder for needing to use are with submodule
The increase of number of blocks and increase, be a kind of sort method traded space for time, can play fpga logic member it is resourceful
Advantage.
Furthermore, it is contemplated that capacitance voltage is possible to equal, the identical voltage of prescribed level is in sequence according in bridge here
Who is in whose preceding preferential principle in arm.Therefore, when being compared, the sequence according to two capacitors in bridge arm is needed to change ratio
Compared with the type of device.As an example, by UmIt is compared with other capacitance voltages, when proceeding to and UnWhen comparing, if m > n, select
" >=" comparator, that is, judge Um≥UnThe true and false, if true, output 1, if vacation, if output 0. m<n, selects ">" comparator,
Judge Um>UnThe true and false, if true, output 1, if vacation, output 0.
Further, in response to the modulation instructions of the modular multilevel matrix inverter, by module described after modulation
Change multi-level matrix inverter individually in the bridge arm submodule quantity of output positive level as the first modulation result, and according to
First modulation result judges the big of submodule quantity and the quantity of the first submodule capacitor of the output positive level
Small relationship.
Wherein, first modulation result is when the period of the bridge arm current is odd cycle, and the modularization is more
Level matrix inverter is modulated the submodule quantity of output positive level in the rear single bridge arm.
It referring to fig. 4, is the controlling party for the modular multilevel matrix inverter capacitance voltage that one embodiment of the invention provides
Method schematic diagram.
It is appreciated that after submodule capacitor voltage equilibrium function is enabled in modular multilevel matrix converter bridge arm, control
System processed counts the bridge arm current period, and in bridge arm current odd cycle, control system is only to first group of submodule capacitor
Sequence, and in even cycle, only sort to second group of submodule capacitor.
Preferably, in the odd cycle of bridge arm current, when the result of modulation is n submodule output positive level, remaining
When submodule exports negative level, when the submodule quantity of the output positive level is not more than the number of the first submodule capacitor
Amount when i.e. n≤N/2, performs the following operations:
In an alternative embodiment, when the submodule quantity for determining the output positive level is not more than described first
The quantity of submodule capacitor, and detect that the direction of the bridge arm current is timing, control the insulated gate bipolar of the submodule
Transistor npn npn movement, so that being ordered as rear n of capacitor in the first submodule capacitor is in charged state, remaining described the
One submodule capacitor and the second submodule capacitor are in discharge condition；Wherein, 0 < n≤N, n are the output positive level
Submodule quantity, N are the capacitor quantity of submodule in the modular multilevel matrix converter bridge arm.
In an alternative embodiment, when determining the submodule quantity of the output positive level no more than described the
The quantity of one submodule capacitor, and when detecting that the direction of the bridge arm current is negative, the insulated gate for controlling the submodule is double
Bipolar transistor movement, so that n capacitors are in discharge condition before being ordered as in the first submodule capacitor, described in remaining
First submodule capacitor and the second submodule capacitor are in charged state.
Preferably, in the odd cycle of bridge arm current, when the result of modulation is n submodule output positive level, remaining
Submodule export negative level when, when it is described output positive level submodule quantity be greater than the first submodule capacitor quantity,
That is it when n > N/2, performs the following operations:
In an alternative embodiment, when the submodule quantity for determining the output positive level is greater than first son
The quantity of module capacitance, and detect that the direction of the bridge arm current is timing, control the insulated gate bipolar of the submodule
Transistor action, so that N-n capacitors are in discharge condition before being ordered as in the first submodule capacitor, remaining described the
One submodule capacitor and the second submodule capacitor are in charged state.
In an alternative embodiment, when the submodule quantity for determining the output positive level is greater than described first
The quantity of submodule capacitor, and when detecting that the direction of the bridge arm current is negative, the insulated gate bipolar of control submodule is brilliant
The movement of body pipe, so that being ordered as rear N-n of capacitor in the first submodule capacitor is in charged state, remaining described first
Submodule capacitor and the second submodule capacitor are in discharge condition.
Wherein, the insulated gate bipolar transistor for controlling submodule in the modular multilevel matrix converter bridge arm is dynamic
Make, it can be understood as realized by the cut-off of control insulated gate bipolar transistor or conducting to the charge or discharge of capacitor
Operation.
S13, when detect the bridge arm current period be even cycle when, the logical operation list based on the FPGA
Member, according to the voltage of the second submodule capacitor to the second submodule capacitor within preset two clock cycle
Sorting in parallel is carried out, and according to the direction of the bridge arm current and the second modulation result, the insulated gate for controlling the submodule is double
Bipolar transistor movement, so as to carry out the operation of charge or discharge to the capacitor of the submodule.
It is appreciated that when detecting the current bridge arm current period is even cycle, control principle and odd cycle phase
Together.
Specifically, when the period for detecting the bridge arm current is even cycle, within first clock cycle,
Logical unit based on the FPGA compares the voltage of the second submodule capacitor two-by-two, obtains the second submodule
Block capacitance voltage fiducial value；
Within second clock cycle, the logical unit based on the FPGA is to the second submodule capacitor
Voltage fiducial value is calculated, and according to calculated result, by the voltage of the second submodule capacitor by arranging from big to small
Sequence；
In response to the modulation instructions of the modular multilevel matrix inverter, by modular multilevel square described after modulation
Battle array inverter individually adjust as the second modulation result, and according to described second by the interior submodule quantity for exporting positive level of the bridge arm
System is as a result, judge the size relation of the submodule quantity of the output positive level and the quantity of the second submodule capacitor.
Wherein, second modulation result is when the period of the bridge arm current is even cycle, and the modularization is more
Level matrix inverter is modulated the submodule quantity of output positive level in the rear single bridge arm.
Preferably, in the even cycle of bridge arm current, when the result of modulation is n submodule output positive level, remaining
When submodule exports negative level, when the submodule quantity of the output positive level is not more than the number of the first submodule capacitor
Amount when i.e. n≤N/2, performs the following operations:
In an alternative embodiment, when the submodule quantity for determining the output positive level is not more than described second
The quantity of submodule capacitor, and detect that the direction of the bridge arm current is timing, control the insulated gate bipolar of the submodule
Transistor npn npn movement, so that being ordered as rear n of capacitor in the second submodule capacitor is in charged state, remaining described the
Two submodule capacitors and the first submodule capacitor are in discharge condition；Wherein, 0 < n≤N, n are the output positive level
Submodule quantity, N are the capacitor quantity of submodule in the modular multilevel matrix converter bridge arm.
In an alternative embodiment, when determining the submodule quantity of the output positive level no more than described the
The quantity of two submodule capacitors, and when detecting that the direction of the bridge arm current is negative, the insulated gate for controlling the submodule is double
Bipolar transistor movement, so that n capacitors are in discharge condition before being ordered as in the second submodule capacitor, described in remaining
Second submodule capacitor and the first submodule capacitor are in charged state.
Preferably, in the even cycle of bridge arm current, when the result of modulation is n submodule output positive level, remaining
Submodule export negative level when, when it is described output positive level submodule quantity be greater than the first submodule capacitor quantity,
That is it when m > N/2, performs the following operations:
In an alternative embodiment, when the submodule quantity for determining the output positive level is greater than second son
The quantity of module capacitance, and detect that the direction of the bridge arm current is timing, control the insulated gate bipolar of the submodule
Transistor action, so that N-n capacitors are in discharge condition before being ordered as in the second submodule capacitor, remaining described the
Two submodule capacitors and the first submodule capacitor are in charged state.
In an alternative embodiment, when the submodule quantity for determining the output positive level is greater than described second
The quantity of submodule capacitor, and when detecting that the direction of the bridge arm current is negative, control the insulated gate bipolar of the submodule
Transistor npn npn movement, so that being ordered as rear N-n of capacitor in the second submodule capacitor is in charged state, described in remaining
Second submodule capacitor and the first submodule capacitor are in discharge condition.
A kind of control method of modular multilevel matrix inverter capacitance voltage provided in an embodiment of the present invention, pass through by
The capacitor of submodule is evenly dividing as the first submodule capacitor and second submodule in modular multilevel matrix converter bridge arm
Capacitor, when the period for detecting bridge arm current is odd cycle, the logical unit based on FPGA, according to first son
The voltage of module capacitance carries out sorting in parallel within preset two clock cycle to the first submodule capacitor, and according to institute
Direction and the first modulation result for stating bridge arm current control the insulated gate bipolar transistor movement of the submodule, so that right
The capacitor of the submodule carries out the operation of charge or discharge, when the period for detecting the bridge arm current is even cycle,
Based on the logical unit of the FPGA, exist according to the voltage of the second submodule capacitor to the second submodule capacitor
Carry out sorting in parallel in preset two clock cycle, and according to the direction of the bridge arm current and the second modulation result,
The insulated gate bipolar transistor movement of the submodule is controlled, so that the capacitor to the submodule carries out charge or discharge
Operation, by the way of sorting in parallel, can effectively improve the speed of sequence, and real-time is good, the operation of the effectively save FPGA of energy
Resource reduces cost, and then can effectively solve submodule capacitor in modular multilevel matrix inverter modulated process bridge arm
The problem of Voltage unbalance, guarantees the normal operation of modular multilevel matrix inverter.
In another preferred embodiment, on the basis of the above embodiments, the modular multilevel matrix inverter electricity
The control method for holding voltage is applied in actual circuit.
Assuming that having 8 submodules, respectively SM on each bridge arm of modular multilevel matrix inverter0~SM7, they
Capacitance voltage is respectively Uc0~Uc7, submodule is divided into two groups, respectively U in advancec0~Uc3And Uc4~Uc7.Start enabled submodule
After block capacitor voltage balance function, in a cycle of bridge arm current, to Uc0~Uc3Carry out sorting in parallel.Specific sequence side
Method is as follows:
In first clock cycle of FPGA, first to Uc0~Uc3Compared two-by-two:
//Uc0Compared with other capacitance voltages
If(Uc0>Uc1)x00=0；else x00=1；
If(Uc0>Uc2)x01=0；else x01=1；
If(Uc0>Uc3)x02=0；else x02=1；
//Uc1 is compared with other capacitance voltages
If(Uc1≥Uc0)x10=0；else x10=1；
If(Uc1>Uc2)x11=0；else x11=1；
If(Uc1>Uc3)x12=0；else x12=1；
……
//Uc3Compared with other capacitance voltages
If(Uc3≥Uc0)x30=0；else x30=1；
If(Uc3≥Uc1)x31=0；else x31=1；
If(Uc3≥Uc2)x32=0；else x32=1.
In second clock cycle of FPGA, fiducial value is added up, obtains each submodule capacitor in this group of capacitance voltage
Position.
X0=x00+x01+x02；
X1=x10+x11+x12；
X2=x20+x21+x22；
X3=x30+x31+x32.
The control method of the modular multilevel matrix inverter capacitance voltage only needs 2 FPGA clock cycle with regard to complete
At sequence, and operation time does not change with data volume, compared to traditional sort algorithm, is greatly saved and calculates the time.But it is another
One side this method needs to occupy a large amount of processing space, that is, needs using a large amount of FPGA logic cell, and FPGA is patrolled
It is resourceful to collect member, therefore is applicable in very much the sort algorithm of this space for time.
After control system finds first end cycle of bridge arm current by detection bridge arm current direction and counting module, open
Begin to Uc4~Uc7It is ranked up, sort method is same as above.It circuits sequentially, i.e. bridge arm current odd cycle is to Uc0~Uc3It is ranked up,
Even cycle is to Uc4~Uc7It is ranked up.
Modular multilevel matrix inverter submodule number applied to high-voltage large-capacity occasion is usually more, the present embodiment
Sort method it is time-consuming compared with traditional serial sort method (such as bubble sort) short, and sorting time is unrelated with data volume,
Can satisfy submodule number it is more when requirement of real-time.Compared to the parallel sorting algorithm compared entirely, the sequence of the present embodiment
Computing resource needed for method (FPGA logic cell) saves half, has preferable economy.Meanwhile it is traditional based on row
The submodule capacitor voltage balance control of sequence algorithm just has bridge arm current discriminating direction module, and this method only needed in the source FPGA generation
Increasing a counting module and odevity judgment module in code can realize.
Further, modular multilevel matrix inverter submodule capacitor voltage balance is finally the choosing by submodule
What selecting property switching was realized.As shown in figure 4, in the odd cycle of bridge arm current, when the result of modulation is that n submodule exports just
Level, when remaining submodule exports negative level, if n≤4, bridge arm current direction is positive, then controls IGBT and allow SM0~SM3Middle institute
There is XiSubmodule capacitor more than or equal to n is in charged state, remaining submodule capacitor is then in discharge condition.Conversely, working as bridge
When arm current direction is negative, control IGBT allows SM0~SM3In all XiSubmodule capacitor less than n is in discharge condition, remaining
Submodule capacitor is then in charged state.If n > 4, bridge arm current direction is timing, and control IGBT allows SM0~SM3In all Xi
Submodule capacitor less than n-4 is in discharge condition, remaining submodule capacitor is then in charged state.Conversely, working as bridge arm current
When direction is negative, control IGBT allows SM0~SM3In all XiSubmodule capacitor more than or equal to n-4 is in charged state, remaining
Submodule capacitor is then in discharge condition.
As shown in figure 4, in the even cycle of bridge arm current, when the result of modulation is n submodule output positive level,
When minor module exports negative level, if n≤4, bridge arm current direction is positive, then controls IGBT and allow SM4~SM7In all XiGreatly
It is in charged state in the submodule capacitor equal to n, remaining submodule capacitor is then in discharge condition.Conversely, working as bridge arm current
When direction is negative, control IGBT allows SM4~SM7In all XiSubmodule capacitor less than n is in discharge condition, remaining submodule
Capacitor is then in charged state.If n > 4, bridge arm current direction is timing, and control IGBT allows SM4~SM7In all XiLess than n-
4 submodule capacitor is in discharge condition, remaining submodule capacitor is then in charged state.Conversely, when bridge arm current direction is
When negative, control IGBT allows SM4~SM7In all XiSubmodule capacitor more than or equal to n-4 is in charged state, remaining submodule
Capacitor is then in discharge condition.
The control method of a kind of modular multilevel matrix inverter capacitance voltage provided in an embodiment of the present invention, using simultaneously
The mode of row sequence, it is short compared to traditional sort method time-consuming, and sorting time is unrelated with data volume, can satisfy submodule
Requirement of real-time when number is more, computing resource needed for capable of saving half (FPGA logic cell) have preferable economy,
And then the speed of sequence can be effectively improved, and real-time is good, reduces cost, and then can effectively solve modular multilevel matrix and change
The unbalanced problem of submodule capacitor voltage in device modulated process bridge arm is flowed, is guaranteeing modular multilevel matrix inverter just
Often operation.
It is a kind of control for modular multilevel matrix inverter capacitance voltage that one embodiment of the invention provides referring to Fig. 5
The structural schematic diagram of device processed, comprising:
Data division module 1, for the capacitor of submodule in modular multilevel matrix converter bridge arm to be evenly dividing
For the first submodule capacitor and second submodule capacitor；
First data processing module 2, for when detect bridge arm current period be odd cycle when, patrolling based on FPGA
Arithmetic element is collected, according to the voltage of the first submodule capacitor to the first submodule capacitor in preset two clock weeks
Sorting in parallel is carried out in phase, and according to the direction of the bridge arm current and the first modulation result, controls the insulation of the submodule
Grid bipolar junction transistor movement, so as to carry out the operation of charge or discharge to the capacitor of the submodule；
Second data processing module 3, for being based on described when the period for detecting the bridge arm current is even cycle
The logical unit of FPGA, according to the voltage of the second submodule capacitor to the second submodule capacitor described default
Two clock cycle in carry out sorting in parallel, and according to the direction of the bridge arm current and the second modulation result, described in control
The insulated gate bipolar transistor of submodule acts, so as to carry out the operation of charge or discharge to the capacitor of the submodule.
Preferably, which includes:
First comparing unit, for when detect the bridge arm current period be odd cycle when, described in first
In clock cycle, the logical unit based on the FPGA compares the voltage of the first submodule capacitor two-by-two,
Obtain the first submodule capacitor voltage fiducial value；
First computing unit is used for the logical unit pair based on the FPGA within second clock cycle
The first submodule capacitor voltage fiducial value is calculated, and according to calculated result, by the electricity of the first submodule capacitor
It presses and is ranked up from big to small；
First response unit, for the modulation instructions in response to the modular multilevel matrix inverter, after modulation
The modular multilevel matrix inverter individually tie as the first modulation by the interior submodule quantity for exporting positive level of the bridge arm
Fruit, and according to first modulation result, judge the submodule quantity for exporting positive level and the first submodule capacitor
Quantity size relation.
Further, first data processing module 2 further include:
First judging unit, for being not more than first submodule when the submodule quantity for determining the output positive level
The quantity of block capacitor, and detect that the direction of the bridge arm current is timing, the insulated gate bipolar for controlling the submodule is brilliant
The movement of body pipe, so that rear n of capacitor is ordered as in the first submodule capacitor is in charged state, remaining described first son
Module capacitance and the second submodule capacitor are in discharge condition；Wherein, 0 < n≤N, n are the submodule of the output positive level
Number of blocks, N are the capacitor quantity of submodule in the modular multilevel matrix converter bridge arm；
Second judgment unit, for being not more than first submodule when the submodule quantity for determining the output positive level
The quantity of block capacitor, and when detecting that the direction of the bridge arm current is negative, the insulated gate bipolar for controlling the submodule is brilliant
The movement of body pipe, so that n capacitors are in discharge condition before being ordered as in the first submodule capacitor, remaining described first son
Module capacitance and the second submodule capacitor are in charged state.
Further, first data processing module 2 further include:
Third judging unit, for being greater than first submodule when the submodule quantity for determining the output positive level
The quantity of capacitor, and detect that the direction of the bridge arm current is timing, control the insulated gate bipolar crystal of the submodule
Pipe movement, so that N-n capacitors are in discharge condition before being ordered as in the first submodule capacitor, remaining described first son
Module capacitance and the second submodule capacitor are in charged state.
4th judging unit, for being greater than first submodule when the submodule quantity for determining the output positive level
The quantity of capacitor, and when detecting that the direction of the bridge arm current is negative, the insulated gate bipolar transistor of control submodule is dynamic
Make, so that rear N-n of capacitor is ordered as in the first submodule capacitor is in charged state, remaining described first submodule
Capacitor and the second submodule capacitor are in discharge condition.
Preferably, which includes:
Second comparing unit, for when detect the bridge arm current period be even cycle when, described in first
In clock cycle, the logical unit based on the FPGA compares the voltage of the second submodule capacitor two-by-two,
Obtain second submodule capacitance voltage fiducial value；
Second computing unit is used for the logical unit pair based on the FPGA within second clock cycle
The second submodule capacitance voltage fiducial value is calculated, and according to calculated result, by the electricity of the second submodule capacitor
It presses and is ranked up from big to small；
Second response unit, for the modulation instructions in response to the modular multilevel matrix inverter, after modulation
The modular multilevel matrix inverter individually tie as the second modulation by the interior submodule quantity for exporting positive level of the bridge arm
Fruit, and according to second modulation result, judge the submodule quantity for exporting positive level and the second submodule capacitor
Quantity size relation.
Preferably, second data processing module 3 further include:
5th judging unit, for being not more than second submodule when the submodule quantity for determining the output positive level
The quantity of block capacitor, and detect that the direction of the bridge arm current is timing, the insulated gate bipolar for controlling the submodule is brilliant
The movement of body pipe, so that rear n of capacitor is ordered as in the second submodule capacitor is in charged state, remaining described second son
Module capacitance and the first submodule capacitor are in discharge condition；Wherein, 0 < n≤N, n are the submodule of the output positive level
Number of blocks, N are the capacitor quantity of submodule in the modular multilevel matrix converter bridge arm；
6th judging unit, for being not more than second submodule when the submodule quantity for determining the output positive level
The quantity of block capacitor, and when detecting that the direction of the bridge arm current is negative, the insulated gate bipolar for controlling the submodule is brilliant
The movement of body pipe, so that n capacitors are in discharge condition before being ordered as in the second submodule capacitor, remaining described second son
Module capacitance and the first submodule capacitor are in charged state.
Preferably, second data processing module 3 further include:
7th judging unit, for being greater than the second submodule when the submodule quantity for determining the output positive level
The quantity of capacitor, and detect that the direction of the bridge arm current is timing, control the insulated gate bipolar crystal of the submodule
Pipe movement, so that N-n capacitors are in discharge condition before being ordered as in the second submodule capacitor, remaining described second son
Module capacitance and the first submodule capacitor are in charged state；
8th judging unit, for being greater than the second submodule when the submodule quantity for determining the output positive level
The quantity of capacitor, and when detecting that the direction of the bridge arm current is negative, control the insulated gate bipolar crystal of the submodule
Pipe movement, so that rear N-n of capacitor is ordered as in the second submodule capacitor is in charged state, remaining described second son
Module capacitance and the first submodule capacitor are in discharge condition.
It is a kind of control for modular multilevel matrix inverter capacitance voltage that one embodiment of the invention provides referring to Fig. 5
The structural schematic diagram of device processed.The control device of the modular multilevel matrix inverter capacitance voltage of the embodiment includes: place
The computer program managing device, memory and storage in the memory and can running on the processor.The processing
Device realizes that the control method of above-mentioned modules multi-level matrix inverter capacitance voltage is real when executing the computer program
The step in example is applied, such as step S12 shown in FIG. 1 is based on when detecting the current bridge arm current period is odd cycle
The logical unit of FPGA arranges the voltage of the first submodule capacitor parallel within preset two clock cycle
Sequence, and according to the direction of bridge arm current, the insulated gate for controlling submodule in the modular multilevel matrix converter bridge arm is double
Bipolar transistor movement, so as to carry out the operation of charge or discharge to the first submodule capacitor after sequence.Alternatively, the processing
Device realizes the function of each module/unit in above-mentioned each Installation practice when executing the computer program, such as at the first data
Manage module 2, for when detect the current bridge arm current period be odd cycle when, based on the logical unit of FPGA to described
The voltage of first submodule capacitor carries out sorting in parallel within preset two clock cycle, and according to the direction of bridge arm current,
The insulated gate bipolar transistor movement for controlling submodule in the modular multilevel matrix converter bridge arm, so as to sequence
The first submodule capacitor afterwards carries out the operation of charge or discharge.
Illustratively, the computer program can be divided into one or more module/units, one or more
A module/unit is stored in the memory, and is executed by the processor, to complete the present invention.It is one or more
A module/unit can be the series of computation machine program instruction section that can complete specific function, and the instruction segment is for describing institute
State implementation procedure of the computer program in the control device of the modular multilevel matrix inverter capacitance voltage.
The control device of the modular multilevel matrix inverter capacitance voltage can be desktop PC, notes
Originally, palm PC and cloud server etc. calculate equipment.The control of the modular multilevel matrix inverter capacitance voltage fills
It sets and may include, but be not limited only to, processor, memory.It will be understood by those skilled in the art that the schematic diagram is only module
The example for changing the control device of multi-level matrix inverter capacitance voltage is not constituted to modular multilevel matrix inverter electricity
The restriction for holding the control device of voltage may include perhaps combining certain components or not than illustrating more or fewer components
Same component, such as the control device of the modular multilevel matrix inverter capacitance voltage can also be set including input and output
Standby, network access equipment, bus etc..
Alleged processor can be central processing unit (Central Processing Unit, CPU), can also be it
His general processor, digital signal processor (Digital Signal Processor, DSP), specific integrated circuit
(Application Specific Integrated Circuit, ASIC), ready-made programmable gate array (Field-
Programmable Gate Array, FPGA) either other programmable logic device, discrete gate or transistor logic,
Discrete hardware components etc..General processor can be microprocessor or the processor is also possible to any conventional processor
Deng the processor is the control centre of the control device of the modular multilevel matrix inverter capacitance voltage, using each
The various pieces of the control device of kind interface and the entire modular multilevel matrix inverter capacitance voltage of connection.
The memory can be used for storing the computer program and/or module, and the processor is by operation or executes
Computer program in the memory and/or module are stored, and calls the data being stored in memory, described in realization
The various functions of the control device of modular multilevel matrix inverter capacitance voltage.The memory can mainly include storage journey
Sequence area and storage data area, wherein storing program area can the (ratio of application program needed for storage program area, at least one function
Such as sound-playing function, image player function) etc.；Storage data area, which can be stored, uses created data according to mobile phone
(such as audio data, phone directory etc.) etc..In addition, memory may include high-speed random access memory, it can also include non-
Volatile memory, such as hard disk, memory, plug-in type hard disk, intelligent memory card (Smart Media Card, SMC), safe number
Word (Secure Digital, SD) card, flash card (Flash Card), at least one disk memory, flush memory device or its
His volatile solid-state part.
Wherein, if module/unit that the control device of the modular multilevel matrix inverter capacitance voltage integrates
It is realized in the form of SFU software functional unit and when sold or used as an independent product, can store computer-readable at one
It takes in storage medium.Based on this understanding, the present invention realizes all or part of the process in above-described embodiment method, can also be with
Relevant hardware is instructed to complete by computer program, the computer program can be stored in a computer-readable storage
In medium, the computer program is when being executed by processor, it can be achieved that the step of above-mentioned each embodiment of the method.Wherein, described
Computer program includes computer program code, the computer program code can for source code form, object identification code form,
Executable file or certain intermediate forms etc..The computer-readable medium may include: that can carry the computer program
Any entity or device of code, recording medium, USB flash disk, mobile hard disk, magnetic disk, CD, computer storage, read-only memory
(ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, electricity
Believe signal and software distribution medium etc..It should be noted that the content that the computer-readable medium includes can be according to department
Make laws in method administrative area and the requirement of patent practice carry out increase and decrease appropriate, such as in certain jurisdictions, according to legislation and
Patent practice, computer-readable medium do not include electric carrier signal and telecommunication signal.
It should be noted that the apparatus embodiments described above are merely exemplary, wherein described be used as separation unit
The unit of explanation may or may not be physically separated, and component shown as a unit can be or can also be with
It is not physical unit, it can it is in one place, or may be distributed over multiple network units.It can be according to actual
It needs that some or all of the modules therein is selected to achieve the purpose of the solution of this embodiment.In addition, device provided by the invention
In embodiment attached drawing, the connection relationship between module indicate between them have communication connection, specifically can be implemented as one or
A plurality of communication bus or signal wire.Those of ordinary skill in the art are without creative efforts, it can understand
And implement.
The above is a preferred embodiment of the present invention, it is noted that for those skilled in the art
For, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also considered as
Protection scope of the present invention.
Claims (10)
1. a kind of control method of modular multilevel matrix inverter capacitance voltage characterized by comprising
The capacitor of submodule in modular multilevel matrix converter bridge arm is evenly dividing as the first submodule capacitor and second
Submodule capacitor；
When the period for detecting bridge arm current is odd cycle, the logical unit based on FPGA, according to first son
The voltage of module capacitance carries out sorting in parallel within preset two clock cycle to the first submodule capacitor, and according to institute
Direction and the first modulation result for stating bridge arm current control the insulated gate bipolar transistor movement of the submodule, so that right
The capacitor of the submodule carries out the operation of charge or discharge；
When the period for detecting the bridge arm current is even cycle, based on the logical unit of the FPGA, according to institute
The voltage for stating second submodule capacitor carries out the second submodule capacitor parallel within preset two clock cycle
Sequence, and according to the direction of the bridge arm current and the second modulation result, control the insulated gate bipolar crystal of the submodule
Pipe movement, so as to carry out the operation of charge or discharge to the capacitor of the submodule.
2. the control method of modular multilevel matrix inverter capacitance voltage as described in claim 1, which is characterized in that institute
It states when the period for detecting bridge arm current is odd cycle, the logical unit based on FPGA, according to first submodule
The voltage of block capacitor carries out sorting in parallel within preset two clock cycle to the first submodule capacitor, specifically includes:
When the period for detecting the bridge arm current is odd cycle, within first clock cycle, based on described
The logical unit of FPGA compares the voltage of the first submodule capacitor two-by-two, obtains the first submodule capacitor electricity
Press fiducial value；
Within second clock cycle, the logical unit based on the FPGA is to first submodule capacitor voltage
Fiducial value is calculated, and according to calculated result, by the voltage of the first submodule capacitor by being ranked up from big to small；
In response to the modulation instructions of the modular multilevel matrix inverter, modular multilevel matrix described after modulation is changed
Flowing device, individually the interior submodule quantity for exporting positive level of the bridge arm is tied as the first modulation result, and according to first modulation
Fruit judges the size relation of the submodule quantity of the output positive level and the quantity of the first submodule capacitor.
3. the control method of modular multilevel matrix inverter capacitance voltage as claimed in claim 2, which is characterized in that institute
It states when the period for detecting bridge arm current is odd cycle, the logical unit based on FPGA, according to first submodule
The voltage of block capacitor carries out sorting in parallel within preset two clock cycle to the first submodule capacitor, and according to described
The direction of bridge arm current and the first modulation result control the insulated gate bipolar transistor movement of the submodule, so as to institute
The capacitor for stating submodule carries out the operation of charge or discharge, specifically includes:
It is not more than the quantity of the first submodule capacitor when determining the submodule quantity for exporting positive level, and detects
The direction of the bridge arm current is timing, the insulated gate bipolar transistor movement of the submodule is controlled, so that described first
It is ordered as rear n of capacitor in submodule capacitor and is in charged state, remaining described first submodule capacitor and second son
Module capacitance is in discharge condition；Wherein, 0 < n≤N, n are the submodule quantity of the output positive level, and N is the modularization
The capacitor quantity of submodule in multi-level matrix converter bridge arm；
It is not more than the quantity of the first submodule capacitor when determining the submodule quantity for exporting positive level, and detects
When the direction of the bridge arm current is negative, the insulated gate bipolar transistor movement of the submodule is controlled, so that described first
N capacitors are in discharge condition before being ordered as in submodule capacitor, remaining described first submodule capacitor and second son
Module capacitance is in charged state.
4. the control method of modular multilevel matrix inverter capacitance voltage as claimed in claim 3, which is characterized in that institute
State method further include:
It is greater than the quantity of the first submodule capacitor when determining the submodule quantity for exporting positive level, and detects institute
The direction for stating bridge arm current is timing, controls the insulated gate bipolar transistor movement of the submodule, so that first son
N-n capacitors are in discharge condition before being ordered as in module capacitance, remaining described first submodule capacitor and second son
Module capacitance is in charged state；
It is greater than the quantity of the first submodule capacitor when determining the submodule quantity for exporting positive level, and detects institute
When stating the direction of bridge arm current and being negative, the insulated gate bipolar transistor movement of control submodule, so that first submodule
It is ordered as rear N-n of capacitor in capacitor and is in charged state, remaining the first submodule capacitor and the second submodule
Capacitor is in discharge condition.
5. the control method of modular multilevel matrix inverter capacitance voltage as described in claim 1, which is characterized in that institute
It states when the period for detecting the bridge arm current is even cycle, based on the logical unit of the FPGA, according to described
The voltage of second submodule capacitor arranges the second submodule capacitor parallel within preset two clock cycle
Sequence specifically includes:
When the period for detecting the bridge arm current is even cycle, within first clock cycle, based on described
The logical unit of FPGA compares the voltage of the second submodule capacitor two-by-two, obtains second submodule capacitor electricity
Press fiducial value；
Within second clock cycle, the logical unit based on the FPGA is to the second submodule capacitance voltage
Fiducial value is calculated, and according to calculated result, by the voltage of the second submodule capacitor by being ranked up from big to small；
In response to the modulation instructions of the modular multilevel matrix inverter, modular multilevel matrix described after modulation is changed
Flowing device, individually the interior submodule quantity for exporting positive level of the bridge arm is tied as the second modulation result, and according to second modulation
Fruit judges the size relation of the submodule quantity of the output positive level and the quantity of the second submodule capacitor.
6. the control method of modular multilevel matrix inverter capacitance voltage as claimed in claim 5, which is characterized in that institute
It states when the period for detecting the bridge arm current is even cycle, based on the logical unit of the FPGA, according to described
The voltage of second submodule capacitor arranges the second submodule capacitor parallel within preset two clock cycle
Sequence, and according to the direction of the bridge arm current and the second modulation result, control the insulated gate bipolar transistor of the submodule
Movement specifically includes so as to carry out the operation of charge or discharge to the capacitor of the submodule:
It is not more than the quantity of the second submodule capacitor when determining the submodule quantity for exporting positive level, and detects
The direction of the bridge arm current is timing, the insulated gate bipolar transistor movement of the submodule is controlled, so that described second
It is ordered as rear n of capacitor in submodule capacitor and is in charged state, remaining described second submodule capacitor and first son
Module capacitance is in discharge condition；Wherein, 0 < n≤N, n are the submodule quantity of the output positive level, and N is the modularization
The capacitor quantity of submodule in multi-level matrix converter bridge arm；
It is not more than the quantity of the second submodule capacitor when determining the submodule quantity for exporting positive level, and detects
When the direction of the bridge arm current is negative, the insulated gate bipolar transistor movement of the submodule is controlled, so that described second
N capacitors are in discharge condition before being ordered as in submodule capacitor, remaining described second submodule capacitor and first son
Module capacitance is in charged state.
7. the control method of modular multilevel matrix inverter capacitance voltage as claimed in claim 6, which is characterized in that institute
State method further include:
It is greater than the quantity of the second submodule capacitor when determining the submodule quantity for exporting positive level, and detects institute
The direction for stating bridge arm current is timing, controls the insulated gate bipolar transistor movement of the submodule, so that second son
N-n capacitors are in discharge condition before being ordered as in module capacitance, remaining described second submodule capacitor and first son
Module capacitance is in charged state；
It is greater than the quantity of the second submodule capacitor when determining the submodule quantity for exporting positive level, and detects institute
When stating the direction of bridge arm current and being negative, the insulated gate bipolar transistor movement of the submodule is controlled, so that second son
It is ordered as rear N-n of capacitor in module capacitance and is in charged state, remaining described second submodule capacitor and first son
Module capacitance is in discharge condition.
8. a kind of control device of modular multilevel matrix inverter capacitance voltage characterized by comprising
Data division module is first for the capacitor of submodule in modular multilevel matrix converter bridge arm to be evenly dividing
Submodule capacitor and second submodule capacitor；
First data processing module, for when the period for detecting bridge arm current is odd cycle, the logic based on FPGA to be transported
Calculate unit, according to the voltage of the first submodule capacitor to the first submodule capacitor within preset two clock cycle
Sorting in parallel is carried out, and according to the direction of the bridge arm current and the first modulation result, the insulated gate for controlling the submodule is double
Bipolar transistor movement, so as to carry out the operation of charge or discharge to the capacitor of the submodule；
Second data processing module, for being based on the FPGA when the period for detecting the bridge arm current is even cycle
Logical unit, according to the voltage of the second submodule capacitor to the second submodule capacitor described preset two
Sorting in parallel is carried out in a clock cycle, and according to the direction of the bridge arm current and the second modulation result, controls the submodule
The insulated gate bipolar transistor of block acts, so as to carry out the operation of charge or discharge to the capacitor of the submodule.
9. a kind of control device of modular multilevel matrix inverter capacitance voltage, including processor, memory and storage
In the memory and it is configured as the computer program executed by the processor, the processor executes the computer
The control of modular multilevel matrix inverter capacitance voltage as claimed in any of claims 1 to 7 in one of claims is realized when program
Method.
10. a kind of computer readable storage medium, which is characterized in that the computer readable storage medium includes the calculating of storage
Machine program, wherein equipment where controlling the computer readable storage medium in computer program operation is executed as weighed
Benefit require any one of 1 to 7 described in modular multilevel matrix inverter capacitance voltage control method.
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| CN110798080A (en) * | 2019-11-15 | 2020-02-14 | 华北电力大学 | Parallel control system and method for modular multilevel converter |
| CN111211677A (en) * | 2020-02-19 | 2020-05-29 | 南京工程学院 | Direct-current fault quick restart method of MMC type multi-port solid-state transformer |
| CN113472230A (en) * | 2021-06-22 | 2021-10-01 | 中国南方电网有限责任公司超高压输电公司天生桥局 | Bridge arm conduction control method, device and equipment of modular multilevel converter |
| CN114123805A (en) * | 2021-11-23 | 2022-03-01 | 西安交通大学 | Capacitor dynamic voltage-sharing control method of modular multilevel matrix converter |
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| CN110798080A (en) * | 2019-11-15 | 2020-02-14 | 华北电力大学 | Parallel control system and method for modular multilevel converter |
| CN110798080B (en) * | 2019-11-15 | 2020-10-30 | 华北电力大学 | Parallel control system and method for modular multilevel converter |
| CN111211677A (en) * | 2020-02-19 | 2020-05-29 | 南京工程学院 | Direct-current fault quick restart method of MMC type multi-port solid-state transformer |
| CN111211677B (en) * | 2020-02-19 | 2021-06-01 | 南京工程学院 | Direct-current fault quick restart method of MMC type multi-port solid-state transformer |
| CN113472230A (en) * | 2021-06-22 | 2021-10-01 | 中国南方电网有限责任公司超高压输电公司天生桥局 | Bridge arm conduction control method, device and equipment of modular multilevel converter |
| CN114123805A (en) * | 2021-11-23 | 2022-03-01 | 西安交通大学 | Capacitor dynamic voltage-sharing control method of modular multilevel matrix converter |
| CN114123805B (en) * | 2021-11-23 | 2024-04-02 | 西安交通大学 | Capacitive dynamic voltage-sharing control method of modularized multi-level matrix converter |
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