CN107505524B - Converter valve routine test circuit and test method - Google Patents
Converter valve routine test circuit and test method Download PDFInfo
- Publication number
- CN107505524B CN107505524B CN201710771748.5A CN201710771748A CN107505524B CN 107505524 B CN107505524 B CN 107505524B CN 201710771748 A CN201710771748 A CN 201710771748A CN 107505524 B CN107505524 B CN 107505524B
- Authority
- CN
- China
- Prior art keywords
- bridge arm
- modules
- arm
- mmc
- sub
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/003—Environmental or reliability tests
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R17/00—Measuring arrangements involving comparison with a reference value, e.g. bridge
- G01R17/10—AC or DC measuring bridges
- G01R17/12—AC or DC measuring bridges using comparison of currents, e.g. bridges with differential current output
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R17/00—Measuring arrangements involving comparison with a reference value, e.g. bridge
- G01R17/10—AC or DC measuring bridges
- G01R17/16—AC or DC measuring bridges with discharge tubes or semiconductor devices in one or more arms of the bridge, e.g. voltmeter using a difference amplifier
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/327—Testing of circuit interrupters, switches or circuit-breakers
- G01R31/3271—Testing of circuit interrupters, switches or circuit-breakers of high voltage or medium voltage devices
- G01R31/3272—Apparatus, systems or circuits therefor
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Inverter Devices (AREA)
- Rectifiers (AREA)
Abstract
The invention provides a converter valve routine test circuit and a test method, which comprises the following steps: the power supply, the load reactor L, the bridge arm 1 and the bridge arm 2; the bridge arm 1 is formed by connecting m MMC sub-modules in series; the bridge arm 2 is formed by connecting n MMC sub-modules in series; the load reactor L is connected between the bridge arm 1 and the bridge arm 2; the output end of the power supply is provided with m pairs of independent output ports which are respectively connected with each MMC sub-module capacitor of the bridge arm 1 to charge the bridge arm 1. The invention solves the problems of lower test efficiency and overhigh switching loss of an IGBT device when a half-bridge split-dragging mode formed by two MMC sub-modules is adopted to carry out an electrical performance test on the MMC valve in the prior art.
Description
Technical Field
The invention relates to the technical field of flexible direct current transmission of a power system, in particular to a converter valve routine test circuit and a test method.
Background
The VSC-HVDC (Voltage source Converter based) technology, which uses a Voltage source Converter, is a novel dc transmission technology, and is called Flexible dc transmission (HVDC-Flexible) in the academic and industrial areas of China. The existing engineering operation experience shows that the technology is very suitable for being applied to the engineering fields of new energy access power grids, island power supply, city center power supply, weak alternating current power grid interconnection and the like. Current converters for VSC-HVDC direct current engineering mainly adopt two-level, three-level and modular multi-level topological structures. Compared with a two-Level, three-Level and clamping type Multi-Level topological structure, the Modular Multi-Level Converter (MMC) has the characteristics that the working frequency of a switching device is low, and the output voltage waveform is close to a sine wave.
At present, China is accelerating to advance flexible direct current transmission technology research and engineering application based on MMC technology, from the first flexible direct current engineering- +/-30 kV/18MW Shanghai province demonstration engineering in 2011, there are +/-160 kV/200MW south Australian three-terminal flexible direct current transmission engineering, +/-200 kV/400MW Zhoushan five-terminal flexible direct current engineering and +/-320 kV/1000MW mansion engineering, and +/-350 kV/1000MW Luxi asynchronous networking flexible direct current transmission engineering, Yubei back-to-back +/-400 kV/4 1250MW flexible direct current engineering and +/-500 kV North direct current power grid engineering also enter engineering implementation stages.
As a core device of a flexible direct current transmission system, electrical performance of a modular multilevel converter valve (hereinafter referred to as an MMC valve) directly affects safe and reliable operation of the system, and each link of design, development, delivery, field application and the like of the system needs to be checked and examined through a strict test. The routine test is used for testing the installation correctness and the qualification of basic functions of a Sub-module (SM) of the MMC, and is commonly used for factory test and field test of the converter valve, which is one of important contents of the test of the flexible direct current converter valve.
As a brand new electric power device, domestic and foreign related research institutions and manufacturers are still exploring the routine test method research of the MMC converter valve submodule, related documents are few, and reported documents show that the routine test is completed by a half-bridge split mode formed by two submodules. However, with the continuous increase of the capacity of the flexible direct current transmission project, the total number of the sub-modules of a single direct current project reaches thousands or even tens of thousands, the test mode of the two sub-modules dragging can only complete the test of two sub-modules each time, the routine test of all the sub-modules of a project needs 1-2 years, and the flexible direct current transmission project has no feasibility in terms of project period and labor cost. In addition, the switching loss of the IGBT device used by the MMC sub-module is multiplied along with the voltage and current level of the device and is in direct proportion to the switching frequency, the switching frequency requirement of the sub-modules under the test mode that the two sub-modules drag each other is far higher than the actual operating frequency and is close to 1kHz, and the loss heating under the test mode cannot be borne by the IGBT device of the level above 3kV according to the current manufacturing level of the IGBT.
Disclosure of Invention
In view of this, the embodiment of the invention provides a converter valve routine test circuit and a test method, so as to solve the problems that in the prior art, a half-bridge split mode formed by two MMC submodules is adopted to perform an electrical performance test on an MMC valve, the test efficiency is low, and the switching loss of an IGBT device is too high.
Therefore, the embodiment of the invention provides the following technical scheme:
in a first aspect of the present invention, a converter valve routine test circuit is provided, including: the power supply, the load reactor (L), the bridge arm (1) and the bridge arm (2); the bridge arm (1) is formed by connecting m MMC sub-modules in series; the bridge arm (2) is formed by connecting n MMC sub-modules in series; the load reactor (L) is connected between the bridge arm (1) and the bridge arm (2); the output end of the power supply is provided with m pairs of independent output ports which are respectively connected with each MMC sub-module capacitor of the bridge arm (1) to charge the bridge arm (1).
Optionally, the MMC sub-module is composed of a capacitor (C), an upper tube IGBT (T1) and a diode (D1) connected in anti-parallel with the upper tube IGBT (T1), a lower tube IGBT (T2) and a diode (D2) connected in anti-parallel with the lower tube IGBT (T2), a thyristor (Thy) and a bypass switch (K); wherein, go up pipe IGBT (T1) with down pipe IGBT (T2) establish ties after the series with condenser (C) are parallelly connected, thyristor (Thy) and bypass switch (K) with down pipe IGBT (T2) are parallelly connected, just thyristor (Thy) switch on the direction with diode (D2) are unanimous, go up pipe IGBT (T1) with tie point between down pipe IGBT (T2) is the positive pole of MMC submodule piece, the other end of down pipe IGBT (T2) is the negative pole of MMC submodule piece.
Optionally, m is the same as n, and m is less than or equal to 10.
In a second aspect of the present invention, a converter valve routine testing method is provided, which is applied to the converter valve routine testing circuit, and includes: carrying out input or output control on MMC sub-modules in the bridge arm (1) and the bridge arm (2) through carrier phase-shift sine pulse width modulation; adjusting the amplitude and the phase difference between the first modulation wave signal and the second modulation wave signal to obtain a first alternating current and direct current superposed current of the bridge arm (1) and a second alternating current and direct current superposed current of the bridge arm (2); the first modulation wave signal is a modulation signal acting on the bridge arm (1), and the second modulation wave signal is a modulation signal acting on the bridge arm (2); judging whether the first alternating current-direct current superposed current and the second alternating current-direct current superposed current are respectively greater than a first preset threshold value and a second preset threshold value to obtain a judgment result; and determining whether the MMC sub-modules in the bridge arm (1) and the bridge arm (2) are qualified or not according to the judgment result.
Optionally, predetermined additional components are superimposed in the first modulated wave signal and the second modulated wave signal, respectively; wherein the predetermined additional component is (a-S) 'sgn (i)' k; a represents the average value of the voltages of all MMC sub-modules of the bridge arm (1) or the bridge arm (2); s represents the sum of the voltages of all MMC sub-modules of the bridge arm (1) or the bridge arm (2); sgn (i) is 1 when the current of the arm (1) or the arm (2) is greater than 1, is-1 when the current of the arm (1) or the arm (2) is less than 1, and is 0 when the current of the arm (1) or the arm (2) is 0.
Optionally, before the input or output control is performed on the MMC sub-modules in the bridge arm (1) and the bridge arm (2) through carrier phase-shift sine pulse width modulation, the method further includes: starting the power supply to charge an MMC sub-module in the bridge arm (1); and charging the bridge arm (2) through the bridge arm (1) for smooth charging.
Optionally, the charging the bridge arm (2) through the bridge arm (1) for smooth charging includes: acquiring a square wave signal; and controlling all MMC sub-modules in the bridge arm (1) to be switched in or out according to the square wave signals.
Optionally, after determining whether the MMC sub-modules in the bridge arm (1) and the bridge arm (2) are qualified according to the determination result, the method further includes: gradually adjusting a phase difference between the first modulated wave signal and the second modulated wave signal to zero; and locking the bridge arm (1) and the bridge arm (2).
The technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a converter valve routine test circuit and a test method, wherein the test circuit comprises: the power supply, the load reactor (L), the bridge arm (1) and the bridge arm (2); wherein the bridge arm (1) is formed by connecting m MMC sub-modules in series; the bridge arm (2) is formed by connecting n MMC sub-modules in series; the load reactor (L) is connected between the bridge arm (1) and the bridge arm (2); the output end of the power supply is provided with m pairs of independent output ports which are respectively connected with each MMC sub-module capacitor of the bridge arm (1) to charge the bridge arm (1). The problems that in the prior art, the half-bridge split-dragging mode formed by two MMC sub-modules is adopted to carry out an electrical performance test on the MMC valve, the test efficiency is low and the switching loss of an IGBT device is too high are solved through adjusting the test circuit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic block diagram of a converter valve routine test circuit according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a half-bridge MMC sub-module according to an embodiment of the present invention;
FIG. 3 is a flow chart of a converter valve routine testing method according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a routine trial carrier phase shift modulation according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a bridge arm current waveform according to an embodiment of the invention;
FIG. 6 is a schematic diagram of an additional control algorithm for bridge arm submodule voltage balancing according to an embodiment of the invention;
FIG. 7 is a schematic of a square wave;
fig. 8 is a schematic voltage waveform diagram of bridge arm sub-modules before and after the voltage balance additional control is applied according to the embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a converter valve routine test circuit, as shown in fig. 1, including: the power supply, the load reactor L, the arm 1, and the arm 2. The power supply may be a dc voltage source, for example. The bridge arm 1 is formed by connecting m MMC sub-modules in series; the bridge arm 2 is formed by connecting n MMC sub-modules in series, in order to ensure the test efficiency and avoid overhigh voltage level and overlarge capacity of the test equipment, the value of the number n of the bridge arm sub-modules is m and can be between 3 and 10 (10 is more than or equal to n and more than or equal to 3). The load reactor L is connected between the bridge arm 1 and the bridge arm 2; the output end of the power supply is provided with m pairs of independent output ports which are respectively connected with each MMC sub-module capacitor of the bridge arm 1 to charge the bridge arm 1.
In an alternative embodiment, as shown in fig. 2, the MMC sub-module is composed of a capacitor C, a top tube T1 and a diode D1 connected in anti-parallel with the top tube T1, a bottom tube T2 and a diode D2 connected in anti-parallel with the bottom tube T2, a thyristor Thy and a bypass switch K; the upper tube T1 and the lower tube T2 are connected in series and then connected in parallel with the capacitor C, the thyristor Thy and the bypass switch K are connected in parallel with the lower tube T2, the conduction direction of the thyristor Thy is consistent with the diode D2, the connection point between the upper tube T1 and the lower tube T2 is the anode of the MMC submodule, and the other end of the lower tube T2 is the cathode of the MMC submodule. In the use process, the capacitor C has a certain level of voltage, and the submodule is put into use when T1 is turned on and T2 is turned off; the sub-modules switch out when T1 turns off T2 turns on.
Through to above-mentioned converter valve routine test circuit, adopt the double bridge arm that contains a plurality of submodule pieces to dragging the main circuit topology, the routine experiment of a plurality of MMC submodule pieces can be accomplished in once experimental, the half-bridge that has solved among the prior art and has adopted two MMC submodule pieces to constitute carries out the electrical property test to the MMC valve to the mode of dragging, lower and the too high problem of IGBT device switching loss of efficiency of software testing to improved efficiency of software testing, satisfied the big experimental requirement in batches of engineering.
In another embodiment, a converter valve routine testing method is provided, which is used in the converter valve routine testing circuit, and fig. 3 is a flow chart of the converter valve routine testing method according to the embodiment of the invention, as shown in fig. 3, the flow chart includes the following steps:
and S301, carrying out input or cut-out control on MMC sub-modules in the bridge arm 1 and the bridge arm 2 through carrier phase shift sine pulse width modulation. Specifically, after the process of charging the bridge arm 1 and the bridge arm 2 by the power supply is completed, the sub-modules of the bridge arm 1 and the bridge arm 2 are switched in or out according to a Carrier Phase Shifting sinusoidal pulse width modulation (CPS-SPWM) method. As shown in fig. 4, the carrier signals of the two bridge arms are the same and are triangular waves with amplitude of 1, the modulation wave signals are sine waves with the same amplitude (less than or equal to 1) and adjustable phase angle difference, wc _1, wc _2 and wc _3 respectively represent the carrier signals of the two bridge arms 3 sub-modules, and wr1 and wr2 respectively represent the modulation wave signals of the bridge arm 1 and the bridge arm 2. The test circuit adopts a carrier phase shift modulation control technology for a bridge arm, can ensure the waveform quality of test current, can obviously reduce the switching loss of a device, and solves the problem of overhigh switching loss of a split scheme of two sub-modules.
Step S302, adjusting the amplitude and the phase difference between the first modulation wave signal and the second modulation wave signal to obtain a first alternating current and direct current superposed current of the bridge arm 1 and a second alternating current and direct current superposed current of the bridge arm 2; the first modulated wave signal is a modulated signal applied to the arm 1, and the second modulated wave signal is a modulated signal applied to the arm 2. Specifically, when a phase difference exists between the modulated wave signals of the two bridge arms, the two bridge arms generate output voltages with superimposed ac and dc, and after the operating energy of the circuit is balanced, superimposed ac and dc currents are generated, as shown in fig. 5. The amplitude and the phase difference of the modulation wave signals are adjusted, so that the magnitude of alternating current and direct current can be adjusted.
Step S303, judging whether the first alternating current and direct current superposed current and the second alternating current and direct current superposed current are respectively greater than a first preset threshold value and a second preset threshold value to obtain a judgment result;
and step S304, determining whether the MMC sub-modules in the bridge arm 1 and the bridge arm 2 are qualified or not according to the judgment result. Specifically, when the first alternating current-direct current superposed current and the second alternating current-direct current superposed current can be respectively greater than a first preset threshold and a second preset threshold, the MMC sub-modules in the bridge arm 1 and the bridge arm 2 are determined to be qualified. In a more preferred embodiment, on the basis that the first alternating current/direct current superposed current and the second alternating current/direct current superposed current can both be greater than a first preset threshold and a second preset threshold respectively, and under the condition that the continuous operation time exceeds the test requirement time, the judgment result is obtained.
Through the steps, the double-bridge-arm pair-dragging main circuit topology containing the multiple sub-modules is adopted, routine tests of the multiple sub-modules can be completed through one-time tests, test efficiency is improved, and the requirement of large-scale engineering tests is met.
In the operation process of the test circuit, the fluctuation of bridge arm current can cause the fluctuation of bridge arm submodule capacitor voltage, and a voltage-sharing strategy is needed to ensure the balance and stability of submodule voltage in a bridge arm. Therefore, in an alternative embodiment, predetermined additional components are superimposed in the first modulated wave signal and the second modulated wave signal, respectively. Wherein the predetermined additional component is (a-S) × sgn (i) × k; a represents the average value of the voltages of all MMC sub-modules of a bridge arm 1 or a bridge arm 2; s represents the sum of the voltages of all MMC sub-modules of the bridge arm 1 or the bridge arm 2; sgn (i) is 1 when the current of arm 1 or arm 2 is greater than 1, is-1 when the current of arm 1 or arm 2 is less than 1, and is 0 when the current of arm 1 or arm 2 is 0. Namely, the basic idea of the voltage-sharing strategy is to superimpose a certain additional component on a sinusoidal modulation wave signal to adjust the capacitance voltage of the bridge arm submodule, and a control algorithm of the additional component is shown in fig. 6. Firstly, summing (Σ) voltage real-time values of all sub-modules of the bridge arm, then calculating an average value (multiplying by 1/n), subtracting a capacitance voltage ec (i) (i is 1,2 … … n) of each sub-module from the obtained average value, then multiplying the obtained difference value by a sign function sgn (i) of the bridge arm current i, then multiplying by a proportionality coefficient k, and obtaining an additional component after a limiting link. Wherein sgn (i) takes the following values:
according to the step, a capacitance-voltage balance additional control strategy is adopted for the bridge arm sub-modules, so that the bridge arm voltage balance is realized.
In an optional embodiment, before the MMC sub-modules in the bridge arm 1 and the bridge arm 2 are controlled to be switched in or out through carrier phase-shift sine pulse width modulation, the power supply is started to charge the MMC sub-modules in the bridge arm 1, and the bridge arm 1 is used for charging the bridge arm 2 for smooth charging. In a specific optional embodiment, a square wave signal is obtained, and all MMC sub-modules in the bridge arm 1 are controlled to be switched in or out according to the square wave signal, so that the bridge arm 1 charges the bridge arm 2 for smooth charging. Specifically, after the test is started, the direct-current power supply is started to charge the capacitor of the submodule of the bridge arm 1, so that the voltage of the capacitor reaches the level required by the test. After the charging of the sub-module capacitor of the bridge arm 1 is completed and the control circuit normally obtains energy from the sub-module capacitor, the bridge arm 1 is unlocked, all sub-modules are switched according to the square wave signals shown in fig. 7, and the bridge arm 2 is charged. The period of square wave is T, and the high level and low level time of each period are T respectivelyonAnd ToffWhen the square wave is high level, all the submodules are put into use, and when the square wave is low levelAll sub-modules are usually switched out. Reasonable selection of frequency (1/T) and duty ratio (T) of square wave signalonand/T), smooth charging of the bridge arm 2 by the bridge arm 1 can be realized, namely after a certain time passes after the bridge arm 1 is unlocked, the capacitor voltage of the submodule of the bridge arm 2 is charged to the level of the capacitor voltage of the submodule of the bridge arm 1.
In an optional embodiment, after determining whether the MMC sub-modules in the bridge arm 1 and the bridge arm 2 are qualified according to the determination result, the phase difference between the first modulation wave signal and the second modulation wave signal is gradually adjusted to be zero, and the bridge arm 1 and the bridge arm 2 are locked. Namely, after the current reaches the test required value and the time required by test examination is passed, the wave phase angle difference of the modulation signal is gradually reduced to 0, then the bridge arm 1 and the bridge arm 2 are locked, the test power supply is withdrawn, and the test is finished.
Fig. 8 shows the capacitance-voltage variation of the bridge arm sub-modules before and after the additional component of voltage balance control is added when the number n of the bridge arm sub-modules is 3, and the waveforms show that the capacitance-voltage fluctuations of the sub-modules tend to be consistent after the additional component is added, and the voltage-equalizing effect is good.
It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.
Claims (8)
1. A converter valve routine test circuit, comprising:
the power supply, the load reactor (L), the bridge arm (1) and the bridge arm (2); the bridge arm (1) is formed by connecting m MMC sub-modules in series; the bridge arm (2) is formed by connecting n MMC sub-modules in series; the load reactor (L) is connected between the bridge arm (1) and the bridge arm (2); the output end of the power supply is provided with m pairs of independent output ports which are respectively connected with each MMC sub-module capacitor of the bridge arm (1) to charge the bridge arm (1).
2. Converter valve routine test circuit according to claim 1, characterized in that the MMC submodule consists of a capacitor (C), an upper tube IGBT (T1) and a diode (D1) anti-parallel to the upper tube IGBT (T1), a lower tube IGBT (T2) and a diode (D2) anti-parallel to the lower tube IGBT (T2), a thyristor (Thy) and a bypass switch (K); wherein, go up pipe IGBT (T1) with down pipe IGBT (T2) establish ties after the series with condenser (C) are parallelly connected, thyristor (Thy) and bypass switch (K) with down pipe IGBT (T2) are parallelly connected, just thyristor (Thy) switch on the direction with diode (D2) are unanimous, go up pipe IGBT (T1) with tie point between down pipe IGBT (T2) is the positive pole of MMC submodule piece, the other end of down pipe IGBT (T2) is the negative pole of MMC submodule piece.
3. The converter valve routine test circuit of claim 1, wherein m and n are the same, and m is 10 or less.
4. A converter valve routine testing method, applied to the converter valve routine testing circuit of claim 1, comprising:
carrying out input or output control on MMC sub-modules in the bridge arm (1) and the bridge arm (2) through carrier phase-shift sine pulse width modulation;
adjusting the amplitude and the phase difference between the first modulation wave signal and the second modulation wave signal to obtain a first alternating current and direct current superposed current of the bridge arm (1) and a second alternating current and direct current superposed current of the bridge arm (2); the first modulation wave signal is a modulation signal acting on the bridge arm (1), and the second modulation wave signal is a modulation signal acting on the bridge arm (2);
judging whether the first alternating current-direct current superposed current and the second alternating current-direct current superposed current are respectively greater than a first preset threshold value and a second preset threshold value to obtain a judgment result;
and determining whether the MMC sub-modules in the bridge arm (1) and the bridge arm (2) are qualified or not according to the judgment result.
5. The method according to claim 4, characterized in that predetermined additional components are superimposed in the first modulated wave signal and the second modulated wave signal, respectively; wherein the predetermined additional component is (a-S) 'sgn (i)' k; a represents the average value of the voltages of all MMC sub-modules of the bridge arm (1) or the bridge arm (2); s represents the sum of the voltages of all MMC sub-modules of the bridge arm (1) or the bridge arm (2); sgn (i) is 1 when the current of the arm (1) or the arm (2) is greater than 1, is-1 when the current of the arm (1) or the arm (2) is less than 1, and is 0 when the current of the arm (1) or the arm (2) is 0.
6. The method of claim 4, wherein before performing the switching-in or switching-out control on the MMC sub-modules in the bridge arm (1) and the bridge arm (2) through carrier phase-shifted sinusoidal pulse width modulation, the method further comprises:
starting the power supply to charge an MMC sub-module in the bridge arm (1);
and charging the bridge arm (2) through the bridge arm (1) for smooth charging.
7. The method according to claim 6, wherein charging the bridge leg (2) through the bridge leg (1) for smooth charging comprises:
acquiring a square wave signal;
and controlling all MMC sub-modules in the bridge arm (1) to be switched in or out according to the square wave signals.
8. The method according to claim 4, after determining whether the MMC sub-modules in the bridge arm (1) and the bridge arm (2) are qualified according to the judgment result, the method further comprises the following steps:
gradually adjusting a phase difference between the first modulated wave signal and the second modulated wave signal to zero;
and locking the bridge arm (1) and the bridge arm (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710771748.5A CN107505524B (en) | 2017-08-31 | 2017-08-31 | Converter valve routine test circuit and test method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710771748.5A CN107505524B (en) | 2017-08-31 | 2017-08-31 | Converter valve routine test circuit and test method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107505524A CN107505524A (en) | 2017-12-22 |
| CN107505524B true CN107505524B (en) | 2020-01-03 |
Family
ID=60694581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710771748.5A Active CN107505524B (en) | 2017-08-31 | 2017-08-31 | Converter valve routine test circuit and test method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107505524B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108279378B (en) * | 2017-12-29 | 2022-03-18 | 中电普瑞电力工程有限公司 | Steady-state test device and method for modular multi-level converter valve |
| CN109946600B (en) * | 2019-04-03 | 2024-02-13 | 国网冀北电力有限公司电力科学研究院 | Device for detecting internal electrical performance of converter valve submodule and control method |
| CN110441630B (en) * | 2019-07-30 | 2021-10-22 | 国电南瑞科技股份有限公司 | Flexibly configurable MMC sub-module function detection device and method |
| CN110596580B (en) * | 2019-09-05 | 2021-12-24 | 许继集团有限公司 | Flexible-straight converter valve overvoltage bypass test method and device |
| CN111505419B (en) * | 2020-04-28 | 2022-06-17 | 南方电网科学研究院有限责任公司 | Opposite impact test circuit for SiC MMC valve section and control method, system and equipment thereof |
| CN111579981B (en) * | 2020-06-05 | 2022-07-19 | 全球能源互联网研究院有限公司 | Circuit and method for simulating switching-on and switching-off voltage of converter valve |
| CN111650504B (en) * | 2020-06-05 | 2022-12-09 | 全球能源互联网研究院有限公司 | Circuit and method for simulating switching-on and switching-off voltage of converter valve |
| CN114325366A (en) * | 2021-12-06 | 2022-04-12 | 国网浙江省电力有限公司杭州供电公司 | System and method for batch testing of converter valve sub-modules |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102323545A (en) * | 2011-08-25 | 2012-01-18 | 中国电力科学研究院 | Power loop test method for steady-state operation test of flexible direct current power transmission MMC (Modular Multilevel Converter) valve |
| CN202230181U (en) * | 2011-08-25 | 2012-05-23 | 中国电力科学研究院 | Power ring test apparatus for flexible DC power transmission MMC valve stable state operation test |
| CN103197241A (en) * | 2013-03-20 | 2013-07-10 | 许继集团有限公司 | Testing device and testing method of flexible direct-current transmission modular multilevel converter (MMC) converter valve operating |
| CN103809114A (en) * | 2014-01-21 | 2014-05-21 | 清华大学 | Power hedge testing apparatus for converter valves of modularized multi-level converter |
| CN106546851A (en) * | 2016-11-01 | 2017-03-29 | 全球能源互联网研究院 | A kind of stable control method and device of MMC converter valve operating tests circuit |
-
2017
- 2017-08-31 CN CN201710771748.5A patent/CN107505524B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102323545A (en) * | 2011-08-25 | 2012-01-18 | 中国电力科学研究院 | Power loop test method for steady-state operation test of flexible direct current power transmission MMC (Modular Multilevel Converter) valve |
| CN202230181U (en) * | 2011-08-25 | 2012-05-23 | 中国电力科学研究院 | Power ring test apparatus for flexible DC power transmission MMC valve stable state operation test |
| CN103197241A (en) * | 2013-03-20 | 2013-07-10 | 许继集团有限公司 | Testing device and testing method of flexible direct-current transmission modular multilevel converter (MMC) converter valve operating |
| CN103809114A (en) * | 2014-01-21 | 2014-05-21 | 清华大学 | Power hedge testing apparatus for converter valves of modularized multi-level converter |
| CN106546851A (en) * | 2016-11-01 | 2017-03-29 | 全球能源互联网研究院 | A kind of stable control method and device of MMC converter valve operating tests circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107505524A (en) | 2017-12-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107505524B (en) | Converter valve routine test circuit and test method | |
| CN106877365B (en) | The alternate unbalanced power control method of modular multi-level converter | |
| CN107210684B (en) | Five level topology units and five-electrical level inverter | |
| Shehu et al. | A review of multilevel inverter topology and control techniques | |
| CN105406748B (en) | A kind of control method of suppression module Multilevel Inverters output current harmonics | |
| CN104578869B (en) | A kind of electric capacity for having dc bus presses three-phase multi-level converter circuit certainly | |
| CN106208737B (en) | Model prediction current control method based on third-harmonic zero-sequence voltage matrix converter | |
| CN105553310B (en) | A kind of low-key system control method of modularization multi-level converter | |
| Xu et al. | Open-loop voltage balancing algorithm for two-port full-bridge MMC-HVDC system | |
| CN102842912A (en) | Single carrier control method applicable to cascaded SVG | |
| CN110858754A (en) | Two-stage control method and system of MMC type energy router | |
| CN105024578A (en) | Three-phase modular multilevel converter parallel system and control method thereof | |
| Ghoreishy et al. | A fast-processing modulation strategy for three-phase four-leg neutral-point-clamped inverter based on the circuit-level decoupling concept | |
| CN109039124B (en) | MMC capacitor voltage balance control method based on phase-shift space vector modulation | |
| Martinez-Rodrigo et al. | Calculation of the number of modules and the switching frequency of a modular multilevel converter using near level control | |
| CN114553020B (en) | Capacitor multiplexing type modular multilevel converter and control method thereof | |
| Etxeberria et al. | Operational limits of a three level neutral point clamped converter used for controlling a hybrid energy storage system | |
| CN114362549B (en) | Cascade multi-level converter based on non-isolated back-to-back topology and control strategy thereof | |
| CN204794752U (en) | Many level converter parallel system of three -phase modularization | |
| Gadalla et al. | State-of-charge balancing control strategy for battery energy storage systems based on a modern cascaded multilevel PWM converter | |
| Jin et al. | Neutral points voltage balancing control of a four-level π-type converter | |
| Mishra et al. | Novel voltage balancing techniques for modular multilevel PV inverters | |
| Salehahari et al. | New coupled-inductor based multilevel inverter with extension capability | |
| Mahmoud et al. | Virtual Flux DPC of a Three-Level NPC Inverter with DC Bus Neutral Point Voltage Balancing | |
| Yi et al. | A novel quasi-Z source cascaded multilevel photovoltaic power system applied to smart microgrid |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |