CN109039124B - MMC capacitor voltage balance control method based on phase-shift space vector modulation - Google Patents
MMC capacitor voltage balance control method based on phase-shift space vector modulation Download PDFInfo
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- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
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Abstract
The invention discloses an MMC capacitor voltage balance control method based on phase-shift space vector modulation, which is used for realizing capacitor voltage balance of each submodule based on the phase-shift space vector modulation, wherein a space vector of a first three-phase submodule is calculated by utilizing a two-level space vector modulation algorithm under α '- β' coordinates, in order to realize control of the rest (n-1) three-phase submodules, the space vector modulation signal of the first three-phase submodule is subjected to phase shift to obtain modulation signals of the other (n-1) three-phase submodules, pulse signals are formed on the basis of the modulation signals and distributed to each half-bridge submodule to control the on-off of each half-bridge submodule in 6 bridge arms, and in order to realize capacitor voltage balance, the space vectors of n groups of three-phase submodules are circularly distributed according to reference voltage periods in the next (n-1) reference voltage periods.
Description
Technical Field
The invention relates to the field of a sub-module capacitance voltage balance control method of a modular multilevel converter (MMC for short) in the field of power electronics and automatic control, in particular to a MMC sub-module capacitance voltage balance control method based on phase-shift space vector modulation, and particularly relates to a control method for realizing MMC sub-module capacitance voltage balance by adopting a cyclic phase-shift space vector modulation strategy under α '- β' coordinates.
Background
The MMC is used as a very popular circuit topology of a medium-high voltage high-power converter, and has the following main advantages: the high modular structure is convenient for expanding the system capacity and industrial production; a direct-current power supply and an output transformer which are isolated in a multipath manner are not needed, so that the circuit structure is simplified, and the system loss is reduced; the high-voltage multi-level output is realized by using a low-voltage-resistant switching device, so that the output waveform is improved, and the switching loss is reduced; the method is easy to realize redundancy control, and has good maintainability, fault ride-through and recovery capability.
The input of MMC topology adopts public direct current bus, with energy dispersion storage in the suspension capacitor of each submodule piece, in order to realize many level output, each submodule piece of establishing ties on same bridge arm adopts the timesharing to switch on or turn-off control, because the discreteness and the nonconformity of device parameter lead to the unbalanced phenomenon of capacitor voltage very easily, will appear when serious that the capacitor voltage of part submodule piece is too high, cause system overvoltage protection, device damage scheduling problem even. Therefore, keeping the capacitor voltage balance of all sub-modules in the bridge arm is one of the primary goals of MMC control.
For voltage-sharing control of an MMC energy storage capacitor, two types of distributed and centralized control methods are mainly adopted at present. Distributed voltage balance control is realized by carrying out independent closed-loop regulation on capacitor voltage of each submodule, when the number of serial submodules of the MMC is increased, the number of the voltage sampling module and the closed-loop regulation module is increased, the hardware cost of the system is greatly improved, the control system is very complex, and the realization difficulty is increased.
Centralized voltage balance control (also called sequencing algorithm) is to perform periodic sampling and sequencing on the capacitor voltages of all the sub-modules of the same bridge arm, and then select a proper sub-module to perform on-off control by combining the direction of the current of the bridge arm and the current state of each sub-module. When the number of serial sub-modules of the MMC increases, a heavy calculation burden is imposed on the control system, and even the highest equivalent switching frequency of the MMC may be limited. Therefore, this approach is not suitable for MMC systems with a large number of modules.
The open-loop-based centralized capacitor voltage balance control method for circularly distributing PWM signals, such as Carrier Phase Shifted Pulse-Width Modulation (CPSPWM), can avoid periodic sampling of capacitor voltages of each sub-module. Because each submodule alternately outputs when CPSPWM is adopted, the capacitance energy distribution is relatively balanced, and therefore the capacitance voltage balance control can be better realized. However, implementing CPSPWM requires a large number of modulation comparison units, which is especially prominent when the number of sub-modules of MMC is large.
Compared with the carrier phase shift modulation method, the Space Vector Pulse-width modulation (SVPWM) method has the advantages of low switching frequency, high direct-current voltage utilization rate, small harmonic content of output waveform, easy digital implementation and the like, and is concerned by many experts and scholars. However, when the SVPWM method is applied to a multilevel converter, the number of basic vectors is greatly increased and the number of redundant switch state vectors is also greatly increased with the increase of the number of levels, and the selection of the switch state vectors and the calculation of the action time thereof are very complicated, so that the SVPWM method is difficult to implement, and particularly when the SVPWM method is applied to the modulation of an MMC, the sub-module capacitor voltage balance control is difficult to implement, so that the SVPWM method is not suitable for the MMC.
Therefore, it is necessary to design a new MMC capacitor voltage balance control method.
Disclosure of Invention
The invention aims to solve the technical problem of providing an MMC capacitor voltage equalization control method based on phase-shifting space vector modulation, and the voltage equalization control method is small in calculation amount and easy to implement.
The technical solution of the invention is as follows:
a MMC capacitor voltage balance control method based on phase-shift space vector modulation is characterized in that the MMC is a three-phase modular multilevel converter, the three-phase modular multilevel converter is provided with 6 three-phase bridge arms, and each bridge arm is formed by cascading (connecting) n submodules (also called half-bridge submodules); each bridge arm is connected with an inductor L; in the 6 bridge arms, 3 upper bridge arms are respectively butted with three lower bridge arms with 3 inductors L through 3 inductors L, the 6 inductors are connected in series in pairs, and 3 series points are used as 3 output ends of the three-phase modular multilevel converter;
the capacitor voltage balance of each submodule is realized based on phase-shift space vector modulation, and the principle is as follows:
three half-bridge sub-modules at the same position of a three-phase bridge arm are regarded as a suspended three-phase sub-module, a three-phase MMC system with n cascaded half-bridge sub-modules can be equivalent to n three-phase sub-modules, and the n three-phase sub-modules are subjected to space vector modulation by utilizing a two-level space vector modulation algorithm under α '- β' coordinates.
The reference voltage of the three-phase submodule is a given three-phase sinusoidal voltage signal corresponding to the desired output sinusoidal voltage, and the three-phase submodule reference voltage vector trajectory model under α '- β' coordinates is:
formula (III) αr' and βr' respectively correspond to reference vectors VrIn the coordinate values of the α '- β', m represents a modulation factor, the magnitude of m reflects the dc voltage utilization rate, and when m is 1, the dc voltage utilization rate is highest.
α in formula (1)r' and βr' expressed as a function of time:
where ω is the sinusoidal reference voltage angular frequency.
α '- β' coordinate system, the basic vector expression of the three-phase submodule is as follows:
in the formula (3), α 'and β' respectively represent coordinate values corresponding to the basic vector in the α '- β' coordinate system, and a, b, and c respectively represent output levels of the respective phase modules, and the values thereof are 0 or 1.
The reference voltage vector track models of the n three-phase submodules are the same, and a reference voltage vector track of one of the three-phase submodules is sampled to obtain a reference vector VrCalculating the time of one sampling period T by using a space vector modulation algorithmSThe corresponding switch state of the inner three-phase submodule and completes the pulseAnd (4) signal distribution.
In order to realize the control of the rest n-1 three-phase submodules, the space vector modulation signal of the previous three-phase submodule is subjected to phase shift to obtain the modulation signals of the other (n-1) three-phase submodules, pulse signals are formed based on the modulation signals and distributed to the submodules to control the on-off of each submodule in 6 bridge arms, the phase difference of the adjacent three-phase submodules is △ theta,
fSis the sampling frequency, fS＝1/TSF is the sinusoidal reference voltage frequency, and f is ω/(2 π).
The method comprises the steps of calculating a space vector of a first three-phase submodule by using a two-level space vector modulation algorithm under α '- β' coordinates, tracking and sampling a reference voltage vector track model in a reference voltage period, calculating a switch state vector, following the same signal distribution principle, repeating reference voltage vector track sampling in the next n-1 reference voltage periods for realizing capacitor voltage balance control, and circularly distributing modulation signals.
Specifically, the method comprises the following steps: in a sinusoidal reference voltage period, the tracking sampling of the reference voltage vector track is completed, and the space vector modulation is realized, following the same signal distribution principle.
Repeating sampling the reference voltage signal and completing space vector modulation in the next sinusoidal reference voltage period, but changing the distribution of the modulation signal and distributing the last time to SM1Is assigned to SM2Last time to SM2Is assigned to SM3Sequentially adjusted, last assigned to SM(n-1)Is assigned to SMnLast time to SMnIs assigned to SM1。
In the next sinusoidal reference period, the previous work is repeated, and the modulation signal is redistributed until n sinusoidal reference voltage periods complete one cycle.
The method comprises the following steps:
the method comprises the following steps: sampling the reference voltage vector track model to obtain a reference voltage vector Vr。
Step two: according to a reference voltage vector Vr(αr',βr') the position of the triangle of the sector in which it is located determines the equivalent base vector of the synthetic reference vector:
(1) if αr'≥0,βr' > 0 or more, reference voltage vector VrIn sector I, in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V1And V2；
(2) If αr'<0,βr'>0,αr'+βr' > 0 or more, reference voltage vector VrIn sector II, in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V2And V3；
(3) If αr'≤0,βr'≥0,αr'+βr'<0, reference voltage vector VrIn sector III, in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V3And V4；
(4) If αr'<0,βr' < 0, reference voltage vector VrIn sector IV, in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V4And V5；
(5) If αr'≥0,βr'<0,αr'+βr'<0, reference voltage vector VrLocated in a V-th sector in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V5And V6；
(6) If αr'>0,βr'≤0,αr'+βr' > 0 or more, reference voltage vector VrIn the VI-th sector, in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V6And V1。
Step three: according to the volt-second balance principle, calculating the action time of three vertex vectors of a triangle corresponding to a sector by a reference vector:
(1) in sector I, according to V0t0+V1t1+V2t2＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V1And V2Respectively has an action time of t0＝(1-αr'-βr')TS，t1＝αr'TS，t2＝βr'TS；TSRepresenting the sampling period.
(2) In sector II, according to V0t0+V2t2+V3t3＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V2And V3Respectively has an action time of t0＝(1-βr')TS，t2＝(αr'+βr')TS，t3＝-αr'TS；
(3) In sector III, according to V0t0+V3t3+V4t4＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V3And V4The action time of (A) is respectively as follows: t is t0＝(1+αr')TS，t3＝βr'TS，t4＝-(αr'+βr')TS；
(4) In sector IV, according to V0t0+V4t4+V5t5＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V4And V5The action time of (A) is respectively as follows: t is t0＝(1+αr'+βr')TS，t4＝-αr'TS，t5＝-βr'TS；
(5) In the V-th sector, according to V0t0+V5t5+V6t6＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V5And V6The time of (a) is: t is t0＝(1+βr')TS，t5＝-(αr'+βr')TS，t6＝αr'TS；
(6) In the VI th sector, according to V0t0+V1t1+V6t6＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V1And V6The action time of (A) is respectively as follows: t is t0＝(1-αr')TS，t1＝(αr'+βr')TS，t6＝-βr'TS。
Step four: the space vector modulation of the three-phase sub-module is realized by adopting seven-segment switching:
(1) in sector I, according to K0→K2→K1→K7→K1→K2→K0The switching rule of (2) completes the equivalence of one sampling period; each switch state has action time t0/4、t2/2、t1/2、t0/2、t1/2、t2/2、t0/4；
(2) In sector II, according to K0→K2→K3→K7→K3→K2→K0The switching rule of (2) completes the equivalence of one sampling period; each switch state has action time t0/4、t2/2、t3/2、t0/2、t3/2、t2/2、t0/4；
(3) In sector III, according to K0→K4→K3→K7→K3→K4→K0The switching rule of (2) completes the equivalence of one sampling period; each switch state has action time t0/4、t4/2、t3/2、t0/2、t3/2、t4/2、t0/4；
(4) In sector IV, according to K0→K4→K5→K7→K5→K4→K0The switching rule of (2) completes the equivalence of one sampling period; each switch state has action time t0/4、t4/2、t5/2、t0/2、t5/2、t4/2、t0/4；
(5) In the V-th sector, according to K0→K6→K5→K7→K5→K6→K0The switching rule of (2) completes the equivalence of one sampling period; each switch state has action time t0/4、t6/2、t5/2、t0/2、t5/2、t6/2、t0/4；
(6) In sector VI, according to K0→K6→K1→K7→K1→K6→K0The switching rule of (2) completes the equivalence of one sampling period; each switch state has action time t0/4、t6/2、t1/2、t0/2、t1/2、t6/2、t0/4；
6 non-zero basis vectors V1、V2、V3、V4、V5、V6The corresponding switch state vectors are respectively K1(1,1,0)、K2(0,1,0)、K3(0,1,1)、K4(0,0,1)、K5(1,0,1)、K6(1,0,0)，V0The corresponding switch state vector is K0(0,0,0) and K7(1,1,1)；Kj(a, b, c) (j ═ 0, 1.., 7) where K isjAnd the names of the switch states are represented, the (a, b and c) represent three-phase output levels corresponding to the switch states, the three-phase output levels are the conduction states of the switches, the a, b and c are 0 to represent that the lower half-bridge switch tube of the phase submodule is conducted, and the a, b and c are 1 to represent that the upper half-bridge switch tube of the phase submodule is conducted. The signals of all three-phase submodules conform to the conditions that a, b and c are 0, the conduction of a lower half-bridge switching tube of the phase submodule is represented, and a, b and c are 1, the phase submodule is representedThe upper half bridge switching tube of the module is conducted. Given first is SM1The modulation signals of the three-phase sub-modules are formed, and the signals on the other (n-1) three-phase sub-modules are obtained through phase-shifting sampling calculation.
Upper bridge arm SMiAnd lower bridge arm SMiThe signals above are identical.
Step five: obtaining switch driving signals (also called modulation signals) of the rest (n-1) three-phase submodules based on phase shifting;
suppose the first sampled reference voltage vector is Vr1The switch state signal obtained by calculation according to the steps (step two, step three and step four) is used for driving the SM in the upper bridge arm and the lower bridge arm1(ii) a Reference voltage vector Vr1Phase-shifting △ theta to obtain a reference voltage vector Vr2The switch state signal obtained by calculation according to the steps (step two, step three and step four) is used for driving the SM in the upper bridge arm and the lower bridge arm2(ii) a Reference voltage vector Vr1Phase-shifting 2 x △ theta to obtain a reference voltage vector Vr3The switch state signal obtained by calculation according to the steps (step two, step three and step four) is used for driving the SM in the upper bridge arm and the lower bridge arm3(ii) a … …, respectively; reference voltage vector Vr1Phase-shifting (n-1) △ theta to obtain a reference voltage vector VrnThe switch state signal obtained by calculation according to the steps (step two, step three and step four) is used for driving the SM in the upper bridge arm and the lower bridge armn；
Step six: and in a sinusoidal reference voltage period, tracking and sampling the reference voltage vector, and repeating the steps of I, II, III, IV and V to realize space vector modulation.
Step seven: and (3) periodically transforming signal distribution based on the sinusoidal reference voltage:
when the sampling reference voltage vector track is completed for one circle (corresponding to one reference voltage period), the step six is circulated again, but the signal distribution is changed, and the reference voltage vector V is usedr1Corresponding obtained switch state signal for driving SM in upper and lower bridge arms2Reference voltage vector Vr2Corresponding obtained switch state signal for driving SM in upper and lower bridge arms3Reference voltage vector Vr3Switch obtained by correspondingThe state signal is used for driving SM in the upper bridge arm and the lower bridge arm4… …, reference voltage vector Vr(n-1)Corresponding obtained switch state signal for driving SM in upper and lower bridge armsnReference voltage vector VrnCorresponding obtained switch state signal for driving SM in upper and lower bridge arms1(ii) a The signal is cyclically distributed to achieve voltage equalization.
Step eight: repeating the seventh step in the next reference voltage period, changing the distribution of the switch state signals, and converting the reference voltage vector V into the reference voltage vectorr1Corresponding obtained switch state signal for driving SM in upper and lower bridge arms3Reference voltage vector Vr2Corresponding obtained switch state signal for driving SM in upper and lower bridge arms4Reference voltage vector Vr3Corresponding obtained switch state signal for driving SM in upper and lower bridge arms5… …, reference voltage vector Vr(n-2)Corresponding obtained switch state signal for driving SM in upper and lower bridge armsnReference voltage vector Vr(n-1)Corresponding obtained switch state signal for driving SM in upper and lower bridge arms1(ii) a Reference voltage vector VrnCorresponding obtained switch state signal for driving SM in upper and lower bridge arms2；
Step nine: according to the recursion of the seventh step and the eighth step (following the circulation rule of the seventh step and the eighth step), circulating the switch state signal corresponding to the reference voltage vector for driving the next submodule; the total cycle is completed by repeating the cycle for n reference voltage periods.
In addition, the control system corresponding to the control method (i.e., the method performs control based on the control system) is as follows:
a sub-module capacitor voltage balance control system for an MMC is characterized by comprising an MCU and a sampling module;
the MCU comprises a model analysis unit, a basic vector action time calculation unit, a phase shift and circulation control unit and a pulse generation unit; the data collected by the sampling module enters a model analysis unit in the MCU;
the model analysis unit, the basic vector action time calculation unit, the phase shift and circulation control unit and the pulse generation unit are sequentially connected;
the MMC is a three-phase modular multilevel converter, the three-phase modular multilevel converter is provided with 6 three-phase bridge arms, and each bridge arm is formed by cascading (connecting) n sub-modules (also called half-bridge sub-modules); each bridge arm is connected with an inductor L; in the 6 bridge arms, 3 upper bridge arms are respectively butted with three lower bridge arms with 3 inductors L through 3 inductors L, the 6 inductors are connected in series in pairs, and 3 series points are used as 3 output ends of the three-phase modular multilevel converter;
the phase shift and circulation control unit and the pulse generation unit generate 2 groups of pulses to respectively control an upper bridge arm and a lower bridge arm in the MMC.
The sub-modules comprise a capacitor C and 2 IGBTs S1 and S2 with freewheeling diodes;
the e pole of the IGBT S1 is connected with the c pole of the IGBT S2; the capacitor C is connected between the C pole of the IGBT S1 and the e pole of the IGBT S2 in a bridge mode;
the G poles of the IGBTs S1 and S2 are used for receiving driving pulses;
the c pole and the e pole of the IGBT S1 in the upper bridge arm half-bridge submodule are used as output connecting lines to be connected with the adjacent half-bridge submodule, the c pole and the e pole of the IGBT S2 in the lower bridge arm half-bridge submodule are used as output connecting lines to be connected with the adjacent half-bridge submodule, and the inductor L is connected in series between the upper bridge arm and the lower bridge arm and used for balancing current. The c pole of the uppermost submodule is connected to the DC bus (i.e. U)DCPositive terminal) of the lowest submodule, e pole of the lowest submodule is connected to the dc bus (i.e. U)DCThe negative terminal of).
The sampling module is used for obtaining a reference voltage vector Vr(αr',βr')，VrRepresents a reference vector, (α)r',βr') indicates vector coordinates;
the model analysis unit is used for analyzing Vr(αr',βr') processing;
the processing comprises judging a reference voltage vector V corresponding to the current sampling signalrIn which sector, and VrCorresponding to which equivalent basis vectors.
The base vector action time calculation unit is used for calculating the action time of a single base vector.
The phase-shifting and circulating control unit generates n groups of phase-shifting space vectors for controlling n three-phase sub-modules (phase difference △ theta of sampling reference voltage vectors of adjacent three-phase sub-modules), detects whether sampling of a sinusoidal reference voltage period is finished, determines whether space vector signal circulating distribution operation is needed or not, and realizes corresponding space vector signal circulating distribution operation.
The pulse generating unit is used for forming a driving pulse according to the control pulse signal so as to control each submodule.
Has the advantages that:
aiming at the problems that the capacitance voltage and/or bridge arm current must be measured by a sequencing algorithm adopted by the conventional MMC submodule capacitance-voltage balance control, the system is complex due to the fact that the number of the measured voltage is increased along with the increase of the number of the submodules, the hardware cost is greatly improved, and the calculation workload of a control system is large, the method is based on α '- β' coordinates, calculates the space vector of one three-phase submodule by using a space vector modulation algorithm, calculates the space vectors of the other three-phase submodules by using a phase shifting method, and controls the circulation of the space vectors of all the submodules to realize the MMC submodule capacitance-voltage balance control.
Compared with the existing MMC submodule capacitor voltage sharing control method, the method provided by the invention does not need to sample submodule capacitor voltage and bridge arm current, does not need voltage sequencing, has no redundant switch state vector in a non-zero space vector, is low in switching frequency, is simple to realize, can greatly reduce the calculation burden of a control system, can also obtain a good MMC submodule capacitor voltage balancing effect, is suitable for MMC with any serial unit number, and has good expansion performance.
Drawings
FIG. 1 is a three-phase MMC circuit topology and half-bridge sub-module diagram;
FIG. 2 is a three-phase sub-module space vector distribution and reference voltage vector trajectory diagram;
FIG. 3 is a schematic diagram of a switching path of the switch state of the sector I;
FIG. 4 is a diagram of a three-phase MMC circuit topology and half-bridge sub-modules with 5 half-bridge sub-modules per bridge arm;
fig. 5 shows three capacitor voltage simulation waveforms of a certain three-phase sub-module, which are obtained by taking an MMC with 5 half-bridge sub-modules included in each bridge arm as an example;
FIG. 6 is a simulated waveform of voltage across ten capacitors of a certain phase, which is obtained by taking an MMC with each bridge arm including 5 half-bridge sub-modules as an example;
fig. 7 is a simulation waveform of a line voltage obtained by taking an example of an MMC comprising 5 half-bridge sub-modules per bridge arm.
Fig. 8 is a control block diagram of the sub-module capacitor voltage equalization control system.
Detailed Description
The invention will be described in further detail below with reference to the following figures and specific examples:
fig. 1 is a diagram showing a three-phase MMC circuit topology including n half-bridge submodules per bridge arm and a half-bridge submodule. Every third half-bridge submodule SM surrounded by a dashed box in the figureiIn a α '- β' coordinate system, the three-phase submodule is modulated by adopting a space vector, the expression of a basic vector is shown as a formula (3), because the output of a half-bridge submodule is two levels, the space vector of the three-phase submodule can be calculated according to the formula (3), the distribution of the space vector is shown as a figure 2, the figure 2 is a space vector distribution and reference voltage vector locus diagram of the three-phase submodule, small black points in the diagram represent basic vectors, and the total number of 7 basic vectors V is 70、V1、V2、V3、V4、V5、V6And the three adjacent basic vectors form a sector triangle, such as the sector triangles I, II, III, IV, V and VI in the figure. 7 basis vectors correspond to 8 switch state vectors K0、K1、K2、K3、K4、K5、K6、K7。
In the α '- β' coordinate system, the reference voltage vector model of the three-phase submodule is as formula (1), the reference voltage vector trajectory is an ellipse as in fig. 2, and the magnitude of the output voltage can be adjusted by changing the modulation factor m, which is shown as the change of the major axis and the minor axis of the ellipse of the reference voltage vector trajectory.
The method comprises the following steps: sampling the reference voltage vector track model to obtain a reference voltage vector VrVector V as in FIG. 2r1、Vr2、VrnBoth represent reference voltage vectors.
Step two: according to a reference voltage vector Vr(αr',βr') the position of the triangle of the sector in which it is located determines the equivalent base vector of the synthetic reference vector:
αr'≥0,βr' > 0 or more, reference voltage vector VrIn sector I, in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V1And V2；
αr'<0,βr'>0,αr'+βr' > 0 or more, reference voltage vector VrIn sector II, in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V2And V3；
αr'≤0,βr'≥0,αr'+βr'<0, reference voltage vector VrIn sector III, in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V3And V4；
αr'<0,βr' < 0, reference voltage vector VrIn sector IV, in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V4And V5；
αr'≥0,βr'<0,αr'+βr'<0, reference voltage vector VrLocated in a V-th sector in which a reference voltage vector V is synthesizedrIs an equivalent base vector ofV0、V5And V6；
αr'>0,βr'≤0,αr'+βr' > 0 or more, reference voltage vector VrIn the VI-th sector, in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V6And V1。
Step three: according to the volt-second balance principle, calculating the action time of three vertex vectors of a triangle corresponding to a sector by a reference vector:
in sector I, according to V0t0+V1t1+V2t2＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V1And V2Respectively has an action time of t0＝(1-αr'-βr')TS，t1＝αr'TS，t2＝βr'TS；
In sector II, according to V0t0+V2t2+V3t3＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V2And V3Respectively has an action time of t0＝(1-βr')TS，t2＝(αr'+βr')TS，t3＝-αr'TS；
In sector III, according to V0t0+V3t3+V4t4＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V3And V4The action time of (A) is respectively as follows: t is t0＝(1+αr')TS，t3＝βr'TS，t4＝-(αr'+βr')TS；
In sector IV, according to V0t0+V4t4+V5t5＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V4And V5The action time of (A) is respectively as follows: t is t0＝(1+αr'+βr')TS，t4＝-αr'TS，t5＝-βr'TS；
In the V-th sector, according to V0t0+V5t5+V6t6＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V5And V6The time of (a) is: t is t0＝(1+βr')TS，t5＝-(αr'+βr')TS，t6＝αr'TS；
In the VI th sector, according to V0t0+V1t1+V6t6＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V1And V6The action time of (A) is respectively as follows: t is t0＝(1-αr')TS，t1＝(αr'+βr')TS，t6＝-βr'TS。
Step four: the space vector modulation of the three-phase sub-module is realized by adopting seven-segment switching:
in sector I, according to K0→K2→K1→K7→K1→K2→K0(the action time of each switch state is t0/4、t2/2、t1/2、t0/2、t1/2、t2/2、t0The switching rule of/4) completes the equivalence of one sampling period;
in sector II, according to K0→K2→K3→K7→K3→K2→K0(the action time of each switch state is t0/4、t2/2、t3/2、t0/2、t3/2、t2/2、t0The switching rule of/4) completes the equivalence of one sampling period;
in sector III, according to K0→K4→K3→K7→K3→K4→K0(the action time of each switch state is t0/4、t4/2、t3/2、t0/2、t3/2、t4/2、t0The switching rule of/4) completes the equivalence of one sampling period;
in sector IV, according to K0→K4→K5→K7→K5→K4→K0(the action time of each switch state is t0/4、t4/2、t5/2、t0/2、t5/2、t4/2、t0The switching rule of/4) completes the equivalence of one sampling period;
in the V-th sector, according to K0→K6→K5→K7→K5→K6→K0(the action time of each switch state is t0/4、t6/2、t5/2、t0/2、t5/2、t6/2、t0The switching rule of/4) completes the equivalence of one sampling period;
in sector VI, according to K0→K6→K1→K7→K1→K6→K0(the action time of each switch state is t0/4、t6/2、t1/2、t0/2、t1/2、t6/2、t0The switching rule of/4) completes the equivalence of one sampling period;
as shown in fig. 3, the switching state switching path diagram of the sector I is taken as an example, in the diagram, a, b, and c represent the outputs of the three-phase sub-modules, where a, b, and c are 0 to represent that the lower half-bridge switching tube of the phase half-bridge sub-module is turned on, and a, b, and c are 1 to represent that the upper half-bridge switching tube of the phase half-bridge sub-module is turned on, and as can be seen from fig. 3, the outputs of the half-bridge sub-modules are centrosymmetric in one sampling period.
Step five: as shown in FIG. 2, assume that the reference voltage vector for the first sample is Vr1The switching state signal obtained by the second, third and fourth steps is used for driving the SM in the upper bridge arm and the lower bridge arm1(ii) a Reference voltage vector Vr1Phase-shifting △ theta to obtain a reference voltage vector Vr2The switching state signal obtained by the second, third and fourth steps is used for driving the SM in the upper bridge arm and the lower bridge arm2(ii) a Reference voltage vector Vr1Phase-shifting 2 x △ theta to obtain a reference voltage vector Vr3The switching state signal obtained by the second, third and fourth steps is used for driving the SM in the upper bridge arm and the lower bridge arm3(ii) a … …, respectively; reference voltage vector Vr1Phase-shifting (n-1) △ theta to obtain a reference voltage vector VrnThe switching state signal obtained by the second, third and fourth steps is used for driving the SM in the upper bridge arm and the lower bridge armn。
Step six: and repeating the first step, the second step, the third step, the fourth step and the fifth step to finish tracking the reference vector track by one sine reference voltage period.
Step seven: repeating the sixth step when the sampling reference voltage vector track is completed for one circle, but changing the signal distribution to obtain the reference voltage vector Vr1Corresponding obtained switch state signal for driving SM in upper and lower bridge arms2Reference voltage vector Vr2Corresponding obtained switch state signal for driving SM in upper and lower bridge arms3Reference voltage vector Vr3Corresponding obtained switch state signal for driving SM in upper and lower bridge arms4… …, reference voltage vector Vr(n-1)Corresponding obtained switch state signal for driving SM in upper and lower bridge armsnReference voltage vector VrnCorresponding obtained switch state signal for driving SM in upper and lower bridge arms1。
Step eight: and repeating the seventh step in the next sinusoidal reference voltage period, and circularly shifting the phase of the reference voltage vector corresponding to the switch state signal to drive the next submodule. Thus, the cyclic distribution of the cyclic signal is completed by shifting the phase of n periods of the sinusoidal reference voltage. And then entering the next control period.
Fig. 4 is a diagram of a three-phase MMC circuit topology and half-bridge sub-modules including 5 half-bridge sub-modules per leg.
Fig. 5 is a waveform diagram illustrating simulation of three capacitor voltages on a three-phase sub-module obtained by taking an MMC with 5 half-bridge sub-modules in each bridge arm as an example, and it can be seen from the waveform diagram that the ripple range of the capacitor voltage on each three-phase sub-module is very small, and the capacitor voltages of the sub-modules can be well balanced.
Fig. 6 is a simulated waveform of voltage on ten capacitors of a certain phase, which is obtained by taking an MMC with 5 half-bridge sub-modules included in each bridge arm as an example, and it can be seen from the waveform diagram that the ripple range of the capacitor voltage on the half-bridge sub-modules of the upper and lower bridge arms of each phase is very small, and the capacitor voltage of the sub-modules can well realize the effect of equalization.
Fig. 7 is a waveform diagram of a simulated line voltage obtained by taking an MMC with 5 half-bridge sub-modules in each bridge arm as an example, and it can be seen from the waveform diagram that the waveform of the line voltage is close to a sine wave and is three-phase symmetric.
Fig. 8 is a block diagram of a control module, in which the control signals of the upper and lower bridge arms are the same, and since one half bridge requires two complementary PWM signals, the upper and lower bridge arms have 3 × 2n pulse signals. The model analysis unit in the figure is realized by software, the action time of the basic vector is also realized by software, and the phase shift, the cycle control and the pulse generation can be realized by software or FPGA.
In summary, the invention provides an MMC sub-module capacitance-voltage balance control method based on phase-shift space vector modulation (PS-SVPWM) by combining the advantages of carrier phase-shift modulation and space vector modulation, the method does not need voltage sequencing, has low switching frequency and simple realization, can greatly reduce the calculation burden of a control system, and can obtain good MMC sub-module capacitance-voltage balance effect.
Claims (3)
1. A MMC capacitor voltage balance control method based on phase-shift space vector modulation is characterized in that the MMC is a three-phase modular multilevel converter, the three-phase modular multilevel converter is provided with 6 three-phase bridge arms, and each bridge arm is formed by cascading n sub-modules; each bridge arm is connected with an inductor L; in the 6 bridge arms, 3 upper bridge arms are respectively butted with three lower bridge arms with 3 inductors L through 3 inductors L, the 6 inductors are connected in series in pairs, and 3 series points are used as 3 output ends of the three-phase modular multilevel converter;
the method is characterized in that:
the method is characterized in that the capacitance voltage balance of each submodule is realized based on phase-shift space vector modulation, and the method comprises the following steps:
calculating the space vector of the first three-phase submodule by using a two-level space vector modulation algorithm under α '- β' coordinates;
in order to realize the control of the rest n-1 three-phase submodules, the space vector modulation signal of the first three-phase submodule is subjected to phase shifting to obtain the modulation signals of the other n-1 three-phase submodules, the phase difference delta theta of the adjacent three-phase submodules,
fSis the sampling frequency, f is the sinusoidal reference voltage frequency; pulse signals are formed based on the modulation signals and distributed to each submodule so as to control the on-off of each submodule in 6 bridge arms;
in a reference voltage period, tracking and sampling a reference voltage vector track model, calculating a switch state vector and following the same signal distribution principle;
in order to realize capacitor voltage balance control, repeating reference voltage vector track sampling for the next n-1 reference voltage periods, and circularly distributing modulation signals;
the method comprises the following steps:
the method comprises the following steps: sampling the reference voltage vector track model to obtain a reference voltage vector Vr(αr',βr')，VrRepresents a reference vector, (α)r',βr') indicates vector coordinates;
step two: according to a reference voltage vector VrDetermining the equivalent basic vector of the synthesized reference vector at the position of the triangle of the located sector:
(1) if αr'≥0,βr' > 0 or more, reference voltage vector VrIn sector I, in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V1And V2；
(2) If αr'＜0,βr'＞0,αr'+βr' > 0 or more, reference voltage vector VrIn sector II, in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V2And V3；
(3) If αr'≤0,βr'≥0,αr'+βr' < 0, reference voltage vector VrIn sector III, in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V3And V4；
(4) If αr'＜0,βr' < 0, reference voltage vector VrIn sector IV, in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V4And V5；
(5) If αr'≥0,βr'＜0,αr'+βr' < 0, reference voltage vector VrLocated in a V-th sector in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V5And V6；
(6) If αr'＞0,βr'≤0,αr'+βr' > 0 or more, reference voltage vector VrIn the VI-th sector, in which a reference voltage vector V is synthesizedrHas an equivalent base vector of V0、V6And V1；
Step three: according to the volt-second balance principle, calculating the action time of three vertex vectors of a triangle corresponding to a sector by a reference vector:
(1) in sector I, according to V0t0+V1t1+V2t2＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V1And V2Respectively has an action time of t0＝(1-αr'-βr')TS，t1＝αr'TS，t2＝βr'TS；TSRepresents a sampling period;
(2) in sector II, according to V0t0+V2t2+V3t3＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V2And V3Respectively has an action time of t0＝(1-βr')TS，t2＝(αr'+βr')TS，t3＝-αr'TS；
(3) In sector III, according to V0t0+V3t3+V4t4＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V3And V4The action time of (A) is respectively as follows: t is t0＝(1+αr')TS，t3＝βr'TS，t4＝-(αr'+βr')TS；
(4) In sector IV, according to V0t0+V4t4+V5t5＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V4And V5The action time of (A) is respectively as follows: t is t0＝(1+αr'+βr')TS，t4＝-αr'TS，t5＝-βr'TS；
(5) In the V-th sector, according to V0t0+V5t5+V6t6＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V5And V6The time of (a) is: t is t0＝(1+βr')TS，t5＝-(αr'+βr')TS，t6＝αr'TS；
(6) In the VI th sector, according to V0t0+V1t1+V6t6＝VrTSCalculating a synthetic reference vector VrOf the basic vector V0、V1And V6The action time of (A) is respectively as follows: t is t0＝(1-αr')TS，t1＝(αr'+βr')TS，t6＝-βr'TS；
Step four: the space vector modulation of the three-phase sub-module is realized by adopting seven-segment switching:
(1) in sector I, according to K0→K2→K1→K7→K1→K2→K0The switching rule of (2) completes the equivalence of one sampling period; each switch state has action time t0/4、t2/2、t1/2、t0/2、t1/2、t2/2、t0/4；
(2) In sector II, according to K0→K2→K3→K7→K3→K2→K0The switching rule of (2) completes the equivalence of one sampling period; each switch state has action time t0/4、t2/2、t3/2、t0/2、t3/2、t2/2、t0/4；
(3) In sector III, according to K0→K4→K3→K7→K3→K4→K0The switching rule of (2) completes the equivalence of one sampling period; each switch state has action time t0/4、t4/2、t3/2、t0/2、t3/2、t4/2、t0/4；
(4) In sector IV, according to K0→K4→K5→K7→K5→K4→K0The switching rule of (2) completes the equivalence of one sampling period; each switch state has action time t0/4、t4/2、t5/2、t0/2、t5/2、t4/2、t0/4；
(5) In the V-th sector, according to K0→K6→K5→K7→K5→K6→K0The switching rule of (2) completes the equivalence of one sampling period; each switch state has action time t0/4、t6/2、t5/2、t0/2、t5/2、t6/2、t0/4；
(6) In sector VI, according to K0→K6→K1→K7→K1→K6→K0The switching rule of (2) completes the equivalence of one sampling period; each switch state has action time t0/4、t6/2、t1/2、t0/2、t1/2、t6/2、t0/4；
6 non-zero basis vectors V1、V2、V3、V4、V5、V6The corresponding switch state vectors are respectively K1(1,1,0)、K2(0,1,0)、K3(0,1,1)、K4(0,0,1)、K5(1,0,1)、K6(1,0,0)，V0The corresponding switch state vector is K0(0,0,0) and K7(1,1,1)；Kj(a, b, c), j ═ 0, 1.., 7, where K isjThe three-phase output level is used for representing the name of a switch state, and a, b and c represent the three-phase output level corresponding to the switch state;
step five: obtaining switch driving signals of the rest n-1 three-phase sub-modules based on phase shifting;
suppose the first sampled reference voltage vector is Vr1The switch state signal obtained by calculation according to the previous steps is used for driving SM in the upper bridge arm and the lower bridge arm1(ii) a Reference voltage vector Vr1Phase shift Delta theta to obtain a reference voltage vector Vr2The switch state signal obtained by calculation according to the previous steps is used for driving SM in the upper bridge arm and the lower bridge arm2(ii) a Reference voltage vector Vr1Phase-shifting 2 x delta theta to obtain a reference voltage vector Vr3The switch state signal obtained by calculation according to the previous steps is used for driving SM in the upper bridge arm and the lower bridge arm3(ii) a … …, respectively; reference voltage vector Vr1Phase-shifting (n-1) Δ θ to obtain a reference voltage vector VrnAccording to the above stepsThe switch state signal obtained by the step calculation is used for driving SM in the upper bridge arm and the lower bridge armn；
Step six: tracking and sampling a reference voltage vector track in a sine reference voltage period, and repeating the steps of I, II, III, IV and V to realize space vector modulation;
step seven: and (3) periodically transforming signal distribution based on the sinusoidal reference voltage:
when the sampling reference voltage vector track is completed for one circle, the next reference voltage period is circulated again in the step six, but the signal distribution is changed, and the reference voltage vector V is usedr1Corresponding obtained switch state signal for driving SM in upper and lower bridge arms2Reference voltage vector Vr2Corresponding obtained switch state signal for driving SM in upper and lower bridge arms3Reference voltage vector Vr3Corresponding obtained switch state signal for driving SM in upper and lower bridge arms4… …, reference voltage vector Vr(n-1)Corresponding obtained switch state signal for driving SM in upper and lower bridge armsnReference voltage vector VrnCorresponding obtained switch state signal for driving SM in upper and lower bridge arms1；
Step eight: repeating the seventh step in the next reference voltage period, changing the distribution of the switch state signals, and converting the reference voltage vector V into the reference voltage vectorr1Corresponding obtained switch state signal for driving SM in upper and lower bridge arms3Reference voltage vector Vr2Corresponding obtained switch state signal for driving SM in upper and lower bridge arms4Reference voltage vector Vr3Corresponding obtained switch state signal for driving SM in upper and lower bridge arms5… …, reference voltage vector Vr(n-2)Corresponding obtained switch state signal for driving SM in upper and lower bridge armsnReference voltage vector Vr(n-1)Corresponding obtained switch state signal for driving SM in upper and lower bridge arms1(ii) a Reference voltage vector VrnCorresponding obtained switch state signal for driving SM in upper and lower bridge arms2；
Step nine: according to the recursion of the seventh step and the eighth step, the switch state signal corresponding to the reference voltage vector is circularly used for driving the next submodule; the total cycle is completed by repeating the cycle for n reference voltage periods.
2. The MMC capacitor voltage balance control method based on phase-shifting space vector modulation of claim 1, wherein the reference voltage vector trajectory model in step one is characterized by the following formula;
in the formula, αr' and βr' coordinate values of a submodule reference voltage vector in α ' - β ' coordinate systems are respectively represented, and m represents a modulation coefficient;
α '- β', the expression of the base vector is:
in the above formula, α 'and β' respectively represent coordinate values corresponding to the basic vectors in the α '- β' coordinate system, and a, b and c respectively represent output levels of the submodules, which are 0 or 1.
3. The MMC capacitor-voltage balance control method based on phase-shifted space vector modulation of any one of claims 1-2, wherein each bridge arm comprises 5 sub-modules.
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