CN110911401A - Semiconductor device with a plurality of semiconductor chips - Google Patents
Semiconductor device with a plurality of semiconductor chips Download PDFInfo
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- CN110911401A CN110911401A CN201910128015.9A CN201910128015A CN110911401A CN 110911401 A CN110911401 A CN 110911401A CN 201910128015 A CN201910128015 A CN 201910128015A CN 110911401 A CN110911401 A CN 110911401A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/02—Details
- H01J37/04—Arrangements of electrodes and associated parts for generating or controlling the discharge, e.g. electron-optical arrangement, ion-optical arrangement
- H01J37/147—Arrangements for directing or deflecting the discharge along a desired path
- H01J37/1472—Deflecting along given lines
- H01J37/1474—Scanning means
- H01J37/1477—Scanning means electrostatic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
Abstract
Embodiments of the present invention relate to a semiconductor device. The semiconductor device of the embodiment includes: 1 st semiconductor layer; a2 nd semiconductor layer; a1 st multilayer wiring layer provided between the 1 st semiconductor layer and the 2 nd semiconductor layer, having a plurality of 1 st conductive layers; a2 nd multilayer wiring layer provided between the 1 st multilayer wiring layer and the 2 nd semiconductor layer, having a plurality of 2 nd conductive layers; a1 st transistor having a1 st impurity region in a1 st semiconductor layer; a2 nd transistor having a2 nd impurity region in the 2 nd semiconductor layer; a1 st hole penetrating the 1 st semiconductor layer, the 1 st multilayer wiring layer, the 2 nd multilayer wiring layer, and the 2 nd semiconductor layer; a2 nd hole penetrating the 1 st semiconductor layer, the 1 st multilayer wiring layer, the 2 nd multilayer wiring layer, and the 2 nd semiconductor layer; a1 st electrode provided in the 1 st multilayer wiring layer; and a2 nd electrode provided in the 1 st multilayer wiring layer and facing the 1 st electrode with the 1 st hole interposed therebetween.
Description
The application claims priority based on Japanese patent application 2018-173109 (application date: 2018, 9 and 14). This application incorporates by reference the content of the application in its entirety.
Technical Field
The present invention relates to a semiconductor device.
Background
In a multi-beam electron beam writing apparatus, a plurality of electron beams are simultaneously irradiated to a sample. In order to individually control irradiation and non-irradiation to a sample of a plurality of electron beams, a Blanking Aperture Array (BAA) is used. In the semiconductor layer of the BAA, a through hole for passing a plurality of electron harnesses is provided. Each through hole has 1 pair of electrodes, and each electron beam is independently deflected by an electric field generated between the electrodes.
For example, if the number of electron beams is increased, the arrangement pitch of the through holes needs to be shortened. However, if the arrangement pitch of the through holes is shortened, the deflection accuracy of the electron beam is lowered due to the influence of the electric field generated by the electrodes of the adjacent through holes.
Disclosure of Invention
The invention provides a semiconductor device which improves the deflection precision of an electron beam.
A semiconductor device according to an aspect of the present invention includes: 1 st semiconductor layer; a2 nd semiconductor layer; a1 st multilayer wiring layer provided between the 1 st semiconductor layer and the 2 nd semiconductor layer, and having a plurality of 1 st conductive layers stacked in a1 st direction from the 1 st semiconductor layer toward the 2 nd semiconductor layer; a2 nd multilayer wiring layer provided between the 1 st multilayer wiring layer and the 2 nd semiconductor layer, and having a plurality of 2 nd conductive layers stacked in the 1 st direction; a1 st transistor having a1 st impurity region in the 1 st semiconductor layer; a2 nd transistor having a2 nd impurity region in the 2 nd semiconductor layer; a1 st hole penetrating the 1 st semiconductor layer, the 1 st multilayer wiring layer, the 2 nd multilayer wiring layer, and the 2 nd semiconductor layer; a2 nd via penetrating the 1 st semiconductor layer, the 1 st multilayer wiring layer, the 2 nd multilayer wiring layer, and the 2 nd semiconductor layer; a1 st electrode provided in the 1 st multilayer wiring layer; and a2 nd electrode provided in the 1 st multilayer wiring layer and facing the 1 st electrode with the 1 st hole interposed therebetween.
According to the above configuration, a semiconductor device in which deflection accuracy of an electron beam is improved is provided.
Drawings
Fig. 1 is a schematic view of a semiconductor device according to embodiment 1.
Fig. 2 is an enlarged schematic cross-sectional view of a part of the semiconductor device according to embodiment 1.
Fig. 3 is a schematic sectional view of the semiconductor device according to embodiment 1 during its manufacture.
Fig. 4 is a schematic sectional view of the semiconductor device according to embodiment 1 during its manufacture.
Fig. 5 is a schematic sectional view of the semiconductor device according to embodiment 1 during its manufacture.
Fig. 6 is a schematic sectional view of the semiconductor device according to embodiment 1 during its manufacture.
Fig. 7 is a schematic sectional view of the semiconductor device according to embodiment 1 during its manufacture.
Fig. 8 is a schematic sectional view of the semiconductor device according to embodiment 1 during its manufacture.
Fig. 9 is an explanatory diagram of an operation of the semiconductor device according to embodiment 1.
Fig. 10 is an enlarged schematic cross-sectional view of a part of the semiconductor device according to embodiment 2.
Description of the reference symbols
10 the 1 st semiconductor layer
12 st source-drain region (1 st impurity region)
20 nd 2 nd semiconductor layer
22 nd 2 nd source-drain region (2 nd impurity region)
30 st 1 multilayer wiring layer
31 the 1 st conductive layer
32 st 1 gate electrode
40 2 nd multilayer wiring layer
41 nd 2 nd conductive layer
42 nd 2 nd gate electrode
100 BAA (semiconductor device)
101a 1 st through hole (1 st hole)
200 BAA (semiconductor device)
E1 No. 1 electrode
E2 No. 2 electrode
E3 No. 3 electrode
E4 No. 4 electrode
E5 th electrode 5
E6 th electrode 6
E7 No. 7 electrode
E8 th electrode 8
TR1 transistor 1
Detailed Description
In this specification, the same or similar components are given the same reference numerals, and overlapping description may be omitted.
In the present specification, in order to indicate the positional relationship of parts and the like, the upper side of the drawings may be referred to as "upper" and the lower side of the drawings may be referred to as "lower". In the present specification, the concept of "up" and "down" is not necessarily a term indicating a relationship with the orientation of gravity.
(embodiment 1)
The semiconductor device of embodiment 1 includes: 1 st semiconductor layer; a2 nd semiconductor layer; a1 st multilayer wiring layer provided between the 1 st semiconductor layer and the 2 nd semiconductor layer, and having a plurality of 1 st conductive layers stacked in a1 st direction from the 1 st semiconductor layer toward the 2 nd semiconductor layer; a2 nd multilayer wiring layer provided between the 1 st multilayer wiring layer and the 2 nd semiconductor layer, and having a plurality of 2 nd conductive layers stacked in the 1 st direction; a1 st transistor having a1 st impurity region in the 1 st semiconductor layer; a2 nd transistor having a2 nd impurity region in the 2 nd semiconductor layer; a1 st hole penetrating the 1 st semiconductor layer, the 1 st multilayer wiring layer, the 2 nd multilayer wiring layer, and the 2 nd semiconductor layer; a2 nd via penetrating the 1 st semiconductor layer, the 1 st multilayer wiring layer, the 2 nd multilayer wiring layer, and the 2 nd semiconductor layer; a1 st electrode provided in the 1 st multilayer wiring layer; and a2 nd electrode provided in the 1 st multilayer wiring layer and facing the 1 st electrode with the 1 st hole interposed therebetween.
Fig. 1 is a schematic view of a semiconductor device according to embodiment 1. Fig. 1(a) is a plan view and fig. 1(b) is a sectional view. FIG. 1(b) is a cross-sectional view AA' of FIG. 1 (a).
The semiconductor device according to embodiment 1 is, for example, a BAA100 used in a multibeam electron beam writing apparatus. The multi-beam electron beam writing apparatus uses a plurality of electron beams to write a pattern on a sample.
The BAA100 has a function of individually deflecting each of the plurality of electron beams. For example, by combining the BAA100 with holes for shielding electron beams, irradiation and non-irradiation of the sample with each electron beam can be controlled independently.
As shown in fig. 1, the BAA100 has a plurality of through holes 101 in the central portion. The electron beams pass through the through holes 101, respectively. Fig. 1(a) illustrates a case where a total of 121 through-holes 101 of 11 horizontal and 11 vertical rows are arranged in an array. However, the number and arrangement shape of the through holes 101 are not limited to the above-described embodiments.
The diameter of the through-hole 101 is, for example, 3 μm to 20 μm. The pitch of the through holes 101 is, for example, 20 μm to 40 μm.
An electrode pad 102 is provided on the upper surface of the BAA 100. The electrode pad 102 is provided for applying a voltage to the BAA100 from the outside. The electrode pad 102 is electrically connected to, for example, a control circuit of the BAA100 and an electrode for deflection control, which are not shown.
Fig. 2 is an enlarged schematic cross-sectional view of a part of the semiconductor device according to embodiment 1. Fig. 2 includes a cross section of 2 through holes 101.
The BAA100 includes a1 st semiconductor layer 10, a2 nd semiconductor layer 20, a1 st multilayer wiring layer 30, a2 nd multilayer wiring layer 40, a1 st transistor TR1, and a2 nd transistor TR 2. The BAA100 includes a1 st electrode E1, a2 nd electrode E2, a 3 rd electrode E3, a 4 th electrode E4, a 5 th electrode E5, a 6 th electrode E6, a 7 th electrode E7, and an 8 th electrode E8. The BAA100 has a1 st through hole 101a (1 st hole) and a2 nd through hole 101b (2 nd hole).
The 1 st semiconductor layer 10 has a1 st substrate region 11 of p-type, n+Type 1 st source-drain region 12 (1 st impurity region), p+Type 1 st contact area 13. The 2 nd semiconductor layer 20 has a p-type 2 nd substrate region 21, n+Type 2 nd source-drain region 22 (2 nd impurity region), p+Type 2 nd contact area 23.
The 1 st multilayer wiring layer 30 has a1 st conductive layer 31, a1 st gate electrode 32, a1 st contact plug 33, a1 st connection pad 34, and a1 st interlayer insulating layer 35. The 2 nd multilayer wiring layer 40 has a2 nd conductive layer 41, a2 nd gate electrode 42, a2 nd contact plug 43, a2 nd connection pad 44, and a2 nd interlayer insulating layer 45.
The 1 st semiconductor layer 10 is, for example, single crystal silicon. The 1 st substrate region 11 of p-type is silicon containing p-type impurities. n is+The 1 st source-drain region 12 of type is silicon containing n-type impurities. p is a radical of+The type 1 st contact region 13 is silicon containing p-type impurities.
The potential of the 1 st semiconductor layer 10 is, for example, a ground potential. The potential of the p-type 1 st substrate region 11 is, for example, a ground potential.
The 2 nd semiconductor layer 20 is, for example, single crystal silicon. The 2 nd substrate region 21 of p-type is silicon containing p-type impurities. n is+The 2 nd source-drain region 22 of type is silicon containing n-type impurities. p is a radical of+The type 2 nd contact region 23 is silicon containing p-type impurities.
The potential of the 2 nd semiconductor layer 20 is, for example, a ground potential. The potential of the p-type 2 nd substrate region 21 is, for example, a ground potential.
The 1 st multilayer wiring layer 30 is disposed between the 1 st semiconductor layer 10 and the 2 nd semiconductor layer 20. The 1 st multilayer wiring layer 30 has a plurality of 1 st conductive layers 31. The 1 st conductive layer 31 is laminated in the 1 st direction from the 1 st semiconductor layer 10 toward the 2 nd semiconductor layer 20. The 1 st direction is a direction perpendicular to the surface of the 1 st semiconductor layer. The number of layers of the 1 st conductive layer 31 is, for example, 3 to 20.
A1 st interlayer insulating layer 35 is provided between the 1 st conductive layers 31. The 1 st interlayer insulating layer 35 is, for example, silicon oxide.
A part of the 1 st conductive layer 31 functions as a wiring. The 1 st conductive layer 31 is, for example, metal.
The 1 st contact plug 33 is provided between the 1 st semiconductor layer 10 and the 1 st conductive layer 31, between the 1 st conductive layer 31 and the 1 st conductive layer 31, and between the 1 st conductive layer 31 and the 1 st connection pad 34. The 1 st contact plug 33 has a function of electrically connecting between the 1 st semiconductor layer 10 and the 1 st conductive layer 31, between the 1 st conductive layer 31 and the 1 st conductive layer 31, and between the 1 st conductive layer 31 and the 1 st connection pad 34. The 1 st contact plug 33 is, for example, metal.
The 1 st connection pad 34 is in contact with the 2 nd connection pad 44. The 1 st connection pad 34 is electrically connected to the 2 nd connection pad 44. The 1 st connection pad 34 is, for example, metal.
The 1 st gate electrode 32 is a conductor. The 1 st gate electrode 32 is, for example, polysilicon containing conductive impurities.
The 2 nd multilayer wiring layer 40 is disposed between the 1 st multilayer wiring layer 30 and the 2 nd semiconductor layer 20. The 2 nd multilayer wiring layer 40 has a plurality of 2 nd conductive layers 41. The 2 nd conductive layer 41 is laminated in the 1 st direction from the 1 st semiconductor layer 10 toward the 2 nd semiconductor layer 20. The number of layers of the 2 nd conductive layer 41 is, for example, 5 to 20.
A2 nd interlayer insulating layer 45 is provided between the 2 nd conductive layers 41. The 2 nd interlayer insulating layer 45 is, for example, silicon oxide.
A part of the 2 nd conductive layer 41 functions as a wiring. The 2 nd conductive layer 41 is, for example, metal.
The 2 nd contact plug 43 is provided between the 2 nd semiconductor layer 20 and the 2 nd conductive layer 41, between the 2 nd conductive layer 41 and the 2 nd conductive layer 41, and between the 2 nd conductive layer 41 and the 2 nd connection pad 44. The 2 nd contact plug 43 has a function of electrically connecting between the 2 nd semiconductor layer 20 and the 2 nd conductive layer 41, between the 2 nd conductive layer 41 and the 2 nd conductive layer 41, and between the 2 nd conductive layer 41 and the 2 nd connection pad 44. The 2 nd contact plug 43 is, for example, metal.
The 2 nd connection pad 44 is in contact with the 1 st connection pad 34. The 2 nd connection pad 44 is electrically connected to the 1 st connection pad 34. The 2 nd connection pad 44 is, for example, metal.
By electrically connecting the 2 nd connection pad 44 and the 1 st connection pad 34, the 1 st conductive layer 31 and the 2 nd conductive layer 41 are electrically connected.
The 2 nd gate electrode 42 is a conductor. The 2 nd gate electrode 42 is, for example, polysilicon containing conductive impurities.
The 1 st through hole 101a penetrates the 1 st semiconductor layer 10, the 1 st multilayer wiring layer 30, the 2 nd multilayer wiring layer 40, and the 2 nd semiconductor layer 20.
The 2 nd through hole 101b penetrates the 1 st semiconductor layer 10, the 1 st multilayer wiring layer 30, the 2 nd multilayer wiring layer 40, and the 2 nd semiconductor layer 20.
The 1 st electrode E1, the 2 nd electrode E2, the 5 th electrode E5, and the 6 th electrode E6 are disposed in the 1 st multilayer wiring layer 30. The 1 st electrode E1, the 2 nd electrode E2, the 5 th electrode E5, and the 6 th electrode E6 have a stacked structure including a plurality of 1 st conductive layers 31. The 1 st electrode E1, the 2 nd electrode E2, the 5 th electrode E5, and the 6 th electrode E6 are formed of a plurality of 1 st conductive layers 31 connected by a1 st contact plug 33.
The 1 st electrode E1 and the 2 nd electrode E2 face each other with the 1 st through hole 101a interposed therebetween. The 1 st electrode E1 and the 2 nd electrode E2 are exposed on the side surface of the 1 st through hole 101a, for example.
The 1 st electrode E1 is electrically connected to the 1 st semiconductor layer 10. The 1 st electrode E1 is electrically connected to p+Type 1 st contact area 13. The potential of the 1 st electrode E1 is the ground potential.
The 2 nd electrode E2 is electrically connected to n+Type 1 source-drain region 12. The potential of the 2 nd electrode E2 changes. The potential of the 2 nd electrode E2 changes between, for example, the ground potential and a predetermined positive potential.
The 5 th electrode E5 and the 6 th electrode E6 face each other with the 2 nd through hole 101b interposed therebetween. The 5 th electrode E5 and the 6 th electrode E6 are exposed on the side surface of the 2 nd through hole 101b, for example.
The 5 th electrode E5 is electrically connected to the 1 st semiconductor layer 10. The 5 th electrode E5 is electrically connected to p+Type 1 st contact area 13. The potential of the 5 th electrode E5 is the ground potential.
The 6 th electrode E6 is electrically connected to n+And type 2 source-drain region 22. The potential of the 6 th electrode E6 changes. The potential of the 6 th electrode E6 changes between, for example, the ground potential and a predetermined positive potential.
The 3 rd electrode E3, the 4 th electrode E4, the 7 th electrode E7, and the 8 th electrode E8 are disposed in the 2 nd multilayer wiring layer 40. The 3 rd, 4 th, 7 th, and 8 th electrodes E3, E4, E7, and E8 have a stacked structure including a plurality of 2 nd conductive layers 41. The 3 rd electrode E3, the 4 th electrode E4, the 7 th electrode E7, and the 8 th electrode E8 are formed of a plurality of 2 nd conductive layers 41 connected by a2 nd contact plug 43.
The 3 rd electrode E3 and the 4 th electrode E4 face each other with the 1 st through hole 101a interposed therebetween. The 3 rd electrode E3 and the 4 th electrode E4 are exposed on the side surface of the 1 st through hole 101a, for example.
The 3 rd electrode E3 is electrically connected to the 2 nd semiconductor layer 20. The 3 rd electrode E3 is electrically connected to p+On the 2 nd contact area 23 of the pattern. The potential of the 3 rd electrode E3 is the ground potential.
The 4 th electrode E4 is electrically connected to n+Type 1 source-drain region 12. The 4 th electrode E4 is electrically connected to the 2 nd electrode E2. The potential of the 4 th electrode E4 changes. The potential of the 4 th electrode E4 changes between, for example, the ground potential and a predetermined positive potential.
The 7 th electrode E7 and the 8 th electrode E8 face each other with the 2 nd through hole 101b interposed therebetween. The 7 th electrode E7 and the 8 th electrode E8 are exposed on the side surface of the 2 nd through hole 101b, for example.
The 7 th electrode E7 is electrically connected to the 2 nd semiconductor layer 20. The 7 th electrode E7 is electrically connected to p+On the 2 nd contact area 23 of the pattern. The potential of the 7 th electrode E7 is the ground potential.
The 8 th electrode E8 is connected to n+And type 2 source-drain region 22. The 8 th electrode E8 is electrically connected to the 4 th electrode E4. The potential of the 8 th electrode E8 changes. The potential of the 8 th electrode E8 changes between, for example, the ground potential and a predetermined positive potential.
The 1 st transistor TR1 has a1 st gate electrode 32 and 1 pair n+Type 1 st source-drain region 12. A1 st gate insulating film, not shown, is provided between the 1 st gate electrode 32 and the 1 st semiconductor layer 10. The 1 st transistor TR1 is an n-channel transistor in which electrons are carriers.
The 1 st transistor TR1 has a function of controlling, for example, potentials applied to the 2 nd electrode E2 and the 4 th electrode E4. In addition, the 1 st semiconductor layer 10 and the 1 st multilayer wiring layer 30 include many transistors for controlling the BAA100 in addition to the 1 st transistor TR 1. For example, a p-channel transistor is included in addition to an n-channel transistor. The 1 st transistor TR1 may be a p-channel transistor.
The 2 nd transistor TR2 has a2 nd gate electrode 42 and 1 pair n+Type 2 source-drain region 22. A2 nd gate insulating film, not shown, is provided between the 2 nd gate electrode 42 and the 2 nd semiconductor layer 20. The 2 nd transistor TR2 is an n-channel transistor in which electrons are carriers.
The 2 nd transistor TR2 has a function of controlling potentials applied to the 6 th electrode E6 and the 8 th electrode E8, for example. In addition, the 2 nd semiconductor layer 20 and the 2 nd multilayer wiring layer 40 include many transistors for controlling the BAA100 in addition to the 2 nd transistor TR 2. For example, a p-channel transistor is included in addition to an n-channel transistor. The 2 nd transistor TR2 may be a p-channel transistor.
Next, an example of a method for manufacturing a semiconductor device according to embodiment 1 will be described. Fig. 3, 4, 5, 6, 7, and 8 are schematic cross-sectional views of the semiconductor device according to embodiment 1 during its manufacture.
First, a plurality of 1 st semiconductor chips SC1 are formed on a1 st wafer (fig. 3). The 1 st semiconductor chip SC1 has a1 st semiconductor layer 10 and a1 st multilayer wiring layer 30.
Next, a plurality of 2 nd semiconductor chips SC2 are formed on the 2 nd wafer (fig. 4). The 2 nd semiconductor chip SC2 has the 2 nd semiconductor layer 20 and the 2 nd multilayer wiring layer 40.
Next, the 1 st wafer and the 2 nd wafer are bonded by a known wafer bonding process so that the 1 st multilayer wiring layer 30 is in contact with the 2 nd multilayer wiring layer 40. Next, the 2 nd semiconductor layer 20 is thinned by grinding (fig. 5).
Next, a hole 101x is formed in the 2 nd semiconductor layer 20 and the 2 nd multilayer wiring layer 40 by photolithography and reactive ion etching (fig. 6).
Next, the support substrate 52 is attached to the 2 nd semiconductor layer 20 using the adhesive layer 50. The support substrate 52 is, for example, quartz glass. Next, the 1 st semiconductor layer 10 is thinned by grinding.
Next, the 1 st through hole 101a and the 2 nd through hole 101b are formed by photolithography and reactive ion etching so that the hole 101x reaches the 1 st semiconductor layer 10 and the 1 st multilayer wiring layer 30 (fig. 7).
Next, the 1 st interlayer insulating layer 35 and the 2 nd interlayer insulating layer 45 are etched so that the 1 st conductive layer 31 and the 2 nd conductive layer 41 are exposed on the side surfaces of the 1 st through hole 101a and the 2 nd through hole 101b (fig. 8). The etching is performed, for example, by wet etching.
Subsequently, the support substrate 52 is peeled off. Next, the bonded 1 st and 2 nd wafers are singulated by dicing, and BAA100 in which the 1 st and 2 nd semiconductor chips SC1 and SC2 are bonded is manufactured.
The operation and effect of the semiconductor device according to embodiment 1 will be described below.
Fig. 9 is an explanatory diagram of an operation of the semiconductor device according to embodiment 1. Fig. 9 is an explanatory diagram of deflection control of the electron beam of the BAA 100.
The electron beam EB1 passing through the 1 st through hole 101a is focused. The 1 st electrode E1 and the 3 rd electrode E3 are electrically connected to the 1 st semiconductor layer 10 and the 2 nd semiconductor layer 20 at the ground potential. Therefore, the 1 st electrode E1 and the 3 rd electrode E3 are at ground potential.
The 2 nd electrode E2 opposed to the 1 st electrode E1 and the 4 th electrode E4 opposed to the 3 rd electrode E3 are electrically connected. The 2 nd electrode E2 and the 4 th electrode E4 are set to predetermined positive potentials by control of the 1 st transistor TR1, for example.
In this case, an electric field in a direction indicated by a white arrow is generated in the 1 st through hole 101 a. The electron beam EB1 is deflected by the electric field generated in the 1 st through hole 101 a.
Next, attention is focused on the electron beam EB2 passing through the 2 nd through hole 101 b. The 5 th electrode E5 and the 7 th electrode E7 are electrically connected to the 1 st semiconductor layer 10 and the 2 nd semiconductor layer 20 at the ground potential. Therefore, the 5 th electrode E5 and the 7 th electrode E7 are at ground potential.
The 6 th electrode E6 opposed to the 5 th electrode E5 and the 8 th electrode E8 opposed to the 7 th electrode E7 are electrically connected. The 6 th electrode E6 and the 8 th electrode E8 are grounded by control of the 2 nd transistor TR2, for example.
In this case, no electric field is generated in the 2 nd through hole 101 b. Thus, electron beam EB2 travels straight without deflection.
In general, if the arrangement pitch of the through holes is shortened, the deflection accuracy of the electron beam is lowered due to the influence of the electric field generated by the electrodes of the adjacent through holes. Therefore, it is desirable to reduce the influence of the electric field generated by the electrodes of the adjacent through holes.
In the BAA100 of embodiment 1, the 1 st electrode E1, the 2 nd electrode E2, the 3 rd electrode E3, the 4 th electrode E4, the 5 th electrode E5, the 6 th electrode E6, the 7 th electrode E7, and the 8 th electrode E8 are sandwiched between the 1 st semiconductor layer 10 and the 2 nd semiconductor layer 20 whose potentials are fixed. Therefore, for example, an electric field generated by the electrode of the 1 st through hole 101a is shielded by the 1 st semiconductor layer 10 and the 2 nd semiconductor layer 20. Therefore, the electric field generated by the electrode of the 1 st through-hole 101a has less influence on the electric field of the 2 nd through-hole 101b adjacent to the 1 st through-hole 101 a. Thereby, the deflection accuracy of the electron beam of the BAA100 is improved.
The 1 st conductive layer 31 and the 2 nd conductive layer 41 existing between the 1 st through hole 101a and the 2 nd through hole 101b also produce an electric field shielding effect. Thus, the deflection accuracy of the electron beam of the BAA100 is improved.
In the BAA100 of embodiment 1, the potential of the electrode can be fixed to the ground potential by the semiconductor layer directly below the electrode. Further, the potential of the electrode can be fixed to the ground potential by both the 1 st semiconductor layer 10 and the 2 nd semiconductor layer 20 above and below the electrode. Therefore, the ground potential of the electrodes is stabilized, and the deflection accuracy of the electron beam of the BAA100 is improved.
If the arrangement pitch of the through holes is shortened, the area of the semiconductor layer that can be used to form the transistor is also reduced. Therefore, for example, in order to secure an area of the semiconductor layer necessary for forming the transistor, reduction in the arrangement pitch of the through holes may be restricted.
In the BAA100 of embodiment 1, a transistor is formed using the 2 nd semiconductor layer 20 in addition to the 1 st semiconductor layer 10. For example, the area of the semiconductor layer that can be used to form a transistor is 2 times larger than BAA having a semiconductor layer only on one side of the electrode. This facilitates reduction in the arrangement pitch of the through holes.
The 1 st electrode E1 and the 2 nd electrode E2 are preferably exposed on the side surface of the 1 st through hole 101 a. The 3 rd electrode E3 and the 4 th electrode E4 are preferably exposed on the side surface of the 1 st through hole 101 a. The 5 th electrode E5 and the 6 th electrode E6 are preferably exposed on the side surface of the 2 nd through hole 101 b. The 7 th electrode E7 and the 8 th electrode E8 are preferably exposed on the side surface of the 2 nd through hole 101 b.
The area of the insulating layer is reduced on the side surface of the 1 st through-hole 101a and the side surface of the 2 nd through-hole 101b, and charging on the side surface of the 1 st through-hole 101a and the side surface of the 2 nd through-hole 101b is suppressed. Thus, the deflection accuracy of the electron beam of the BAA100 is improved
As described above, according to the semiconductor device of embodiment 1, the electrode is sandwiched by the upper and lower 2 semiconductor layers, and thus the electric field shielding effect is improved. Thus, the deflection accuracy of the electron beam is improved. Further, a transistor can be formed in the upper and lower 2 semiconductor layers, and the arrangement pitch of the through holes can be easily reduced.
(embodiment 2)
The semiconductor device according to embodiment 2 is different from embodiment 1 in that the 1 st electrode and the 3 rd electrode are not electrically connected. Hereinafter, description of the overlapping contents with embodiment 1 will be omitted.
The semiconductor device according to embodiment 2 is a BAA200 used in a multibeam electron beam writing apparatus, similar to the semiconductor device according to embodiment 1.
Fig. 10 is an enlarged schematic cross-sectional view of a part of the semiconductor device according to embodiment 2. Fig. 10 includes a cross section of 2 through holes 101.
The BAA200 includes a1 st semiconductor layer 10, a2 nd semiconductor layer 20, a1 st multilayer wiring layer 30, a2 nd multilayer wiring layer 40, a1 st transistor TR1, and a2 nd transistor TR 2. The BAA100 includes a1 st electrode E1, a2 nd electrode E2, a 3 rd electrode E3, a 4 th electrode E4, a 5 th electrode E5, a 6 th electrode E6, a 7 th electrode E7, and an 8 th electrode E8. The BAA100 has a1 st through hole 101a (1 st hole) and a2 nd through hole 101b (2 nd hole).
The 1 st semiconductor layer 10 has a1 st substrate region 11 of p-type, n+Type 1 st source-drain region 12 (1 st impurity region), p+Type 1 st connectionThe contact region 13. The 2 nd semiconductor layer 20 has a p-type 2 nd substrate region 21, n+Type 2 nd source-drain region 22 (2 nd impurity region), p+Type 2 nd contact area 23.
The 1 st multilayer wiring layer 30 has a1 st conductive layer 31, a1 st gate electrode 32, a1 st contact plug 33, and a1 st interlayer insulating layer 35. The 2 nd multilayer wiring layer 40 has a2 nd conductive layer 41, a2 nd gate electrode 42, a2 nd contact plug 43, and a2 nd interlayer insulating layer 45.
In the BAA200, the 1 st conductive layer 31 and the 2 nd conductive layer 41 are not electrically connected.
The 2 nd electrode E2 and the 4 th electrode E4 are not electrically connected. The 2 nd electrode E2 is electrically connected to n+Type 1 source-drain region 12. The 4 th electrode E4 is electrically connected to n+And type 2 source-drain region 22. The potential of the 2 nd electrode E2 and the potential of the 4 th electrode E4 are independently controlled.
The 6 th electrode E6 and the 8 th electrode E8 are not electrically connected. The 6 th electrode E6 is electrically connected to n+Type 1 source-drain region 12. The 8 th electrode E8 is electrically connected to n+And type 2 source-drain region 22. The potential of the 6 th electrode E6 and the potential of the 8 th electrode E8 are independently controlled.
As described above, according to the semiconductor device of embodiment 2, as in embodiment 1, the electrodes are sandwiched by the upper and lower 2 semiconductor layers, whereby the electric field shielding effect is improved.
In embodiments 1 and 2, the case where the 1 st semiconductor layer 10 and the 2 nd semiconductor layer 20 are single crystal silicon has been described as an example, but the 1 st semiconductor layer 10 and the 2 nd semiconductor layer 20 may be another semiconductor material such as single crystal silicon carbide.
In embodiments 1 and 2, the case where the BAA of the present invention is used in a multibeam electron beam writing apparatus has been described as an example, but the BAA of the present invention may be used in another multibeam electron beam exposure apparatus such as a multibeam electron beam inspection apparatus.
Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments may be implemented in other various forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. For example, the components of one embodiment may be replaced or changed with the components of another embodiment. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.
The above embodiments can be summarized as the following embodiments.
Technical solution 1
A semiconductor device, wherein,
the disclosed device is provided with:
1 st semiconductor layer;
a2 nd semiconductor layer;
a1 st multilayer wiring layer provided between the 1 st semiconductor layer and the 2 nd semiconductor layer, and having a plurality of 1 st conductive layers stacked in a1 st direction from the 1 st semiconductor layer toward the 2 nd semiconductor layer;
a2 nd multilayer wiring layer provided between the 1 st multilayer wiring layer and the 2 nd semiconductor layer, and having a plurality of 2 nd conductive layers stacked in the 1 st direction;
a1 st transistor having a1 st impurity region in the 1 st semiconductor layer;
a2 nd transistor having a2 nd impurity region in the 2 nd semiconductor layer;
a1 st hole penetrating the 1 st semiconductor layer, the 1 st multilayer wiring layer, the 2 nd multilayer wiring layer, and the 2 nd semiconductor layer;
a2 nd via penetrating the 1 st semiconductor layer, the 1 st multilayer wiring layer, the 2 nd multilayer wiring layer, and the 2 nd semiconductor layer;
a1 st electrode provided in the 1 st multilayer wiring layer; and
and a2 nd electrode provided in the 1 st multilayer wiring layer and facing the 1 st electrode with the 1 st hole interposed therebetween.
The semiconductor device according to claim 1, wherein,
the 1 st electrode has a laminated structure including the 1 st conductive layer;
the 2 nd electrode has a laminated structure including the 1 st conductive layer.
The semiconductor device according to claim 1 or 2, wherein,
the 1 st electrode is electrically connected to the 1 st semiconductor layer.
Technical solution 4
The semiconductor device according to any one of claims 1 to 3, wherein,
the 2 nd electrode is electrically connected to the 1 st impurity region.
Technical solution 5
The semiconductor device according to any one of claims 1 to 4, wherein,
further provided with:
a 3 rd electrode provided in the 2 nd multilayer wiring layer and electrically connected to the 1 st electrode; and
and a 4 th electrode provided in the 2 nd multilayer wiring layer, electrically connected to the 2 nd electrode, and facing the 3 rd electrode with the 1 st hole interposed therebetween.
Technical scheme 6
The semiconductor device according to claim 5, wherein,
the 3 rd electrode has a laminated structure including the 2 nd conductive layer;
the 4 th electrode has a laminated structure including the 2 nd conductive layer.
Technical scheme 7
The semiconductor device according to claim 5 or 6, wherein,
the 3 rd electrode is electrically connected to the 2 nd semiconductor layer.
Technical solution 8
The semiconductor device according to any one of claims 5 to 7, wherein,
further provided with:
a 5 th electrode provided in the 1 st multilayer wiring layer;
a 6 th electrode provided in the 1 st multilayer wiring layer and facing the 5 th electrode with the 2 nd via interposed therebetween;
a 7 th electrode provided in the 2 nd multilayer wiring layer and electrically connected to the 5 th electrode; and
and an 8 th electrode provided in the 2 nd multilayer wiring layer, electrically connected to the 6 th electrode, and facing the 7 th electrode with the 2 nd via interposed therebetween.
Technical solution 9
The semiconductor device according to claim 8, wherein,
the 5 th electrode is electrically connected to the 1 st semiconductor layer.
Technical means 10
The semiconductor device according to claim 8 or 9, wherein,
the 8 th electrode is electrically connected to the 2 nd impurity region.
Technical means 11
The semiconductor device according to any one of claims 1 to 10, wherein,
the 1 st electrode and the 2 nd electrode are exposed on a side surface of the 1 st hole.
Technical means 12
The semiconductor device according to any one of claims 1 to 11, wherein,
the potentials of the 1 st semiconductor layer and the 2 nd semiconductor layer are ground potential.
Claims (12)
1. A semiconductor device, wherein,
the disclosed device is provided with:
1 st semiconductor layer;
a2 nd semiconductor layer;
a1 st multilayer wiring layer provided between the 1 st semiconductor layer and the 2 nd semiconductor layer, and having a plurality of 1 st conductive layers stacked in a1 st direction from the 1 st semiconductor layer toward the 2 nd semiconductor layer;
a2 nd multilayer wiring layer provided between the 1 st multilayer wiring layer and the 2 nd semiconductor layer, and having a plurality of 2 nd conductive layers stacked in the 1 st direction;
a1 st transistor having a1 st impurity region in the 1 st semiconductor layer;
a2 nd transistor having a2 nd impurity region in the 2 nd semiconductor layer;
a1 st hole penetrating the 1 st semiconductor layer, the 1 st multilayer wiring layer, the 2 nd multilayer wiring layer, and the 2 nd semiconductor layer;
a2 nd via penetrating the 1 st semiconductor layer, the 1 st multilayer wiring layer, the 2 nd multilayer wiring layer, and the 2 nd semiconductor layer;
a1 st electrode provided in the 1 st multilayer wiring layer; and
and a2 nd electrode provided in the 1 st multilayer wiring layer and facing the 1 st electrode with the 1 st hole interposed therebetween.
2. The semiconductor device according to claim 1,
the 1 st electrode has a laminated structure including the 1 st conductive layer;
the 2 nd electrode has a laminated structure including the 1 st conductive layer.
3. The semiconductor device according to claim 1 or 2,
the 1 st electrode is electrically connected to the 1 st semiconductor layer.
4. The semiconductor device according to any one of claims 1 to 3,
the 2 nd electrode is electrically connected to the 1 st impurity region.
5. The semiconductor device according to any one of claims 1 to 4,
further provided with:
a 3 rd electrode provided in the 2 nd multilayer wiring layer and electrically connected to the 1 st electrode; and
and a 4 th electrode provided in the 2 nd multilayer wiring layer, electrically connected to the 2 nd electrode, and facing the 3 rd electrode with the 1 st hole interposed therebetween.
6. The semiconductor device according to claim 5,
the 3 rd electrode has a laminated structure including the 2 nd conductive layer;
the 4 th electrode has a laminated structure including the 2 nd conductive layer.
7. The semiconductor device according to claim 5 or 6,
the 3 rd electrode is electrically connected to the 2 nd semiconductor layer.
8. The semiconductor device according to any one of claims 5 to 7,
further provided with:
a 5 th electrode provided in the 1 st multilayer wiring layer;
a 6 th electrode provided in the 1 st multilayer wiring layer and facing the 5 th electrode with the 2 nd via interposed therebetween;
a 7 th electrode provided in the 2 nd multilayer wiring layer and electrically connected to the 5 th electrode; and
and an 8 th electrode provided in the 2 nd multilayer wiring layer, electrically connected to the 6 th electrode, and facing the 7 th electrode with the 2 nd via interposed therebetween.
9. The semiconductor device according to claim 8,
the 5 th electrode is electrically connected to the 1 st semiconductor layer.
10. The semiconductor device according to claim 8 or 9,
the 8 th electrode is electrically connected to the 2 nd impurity region.
11. The semiconductor device according to any one of claims 1 to 10,
the 1 st electrode and the 2 nd electrode are exposed at a side surface of the 1 st hole.
12. The semiconductor device according to any one of claims 1 to 11,
the potentials of the 1 st semiconductor layer and the 2 nd semiconductor layer are ground potential.
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| JP6965222B2 (en) | 2021-11-10 |
| JP2020047667A (en) | 2020-03-26 |
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