CN110910853B

CN110910853B - Shifting register, driving method thereof and grid driving circuit

Info

Publication number: CN110910853B
Application number: CN201911319523.1A
Authority: CN
Inventors: 余豪; 袁东旭; 赵剑; 毛大龙; 陈鹏; 刘子正; 马勇
Original assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Priority date: 2019-12-19
Filing date: 2019-12-19
Publication date: 2021-10-29
Anticipated expiration: 2039-12-19
Also published as: CN110910853A

Abstract

The shift register comprises an input sub-circuit, a discharge sub-circuit, an output sub-circuit, a pull-up sub-circuit, a pull-down sub-circuit and a reset sub-circuit, wherein the input sub-circuit provides signals of a signal input end to a first pull-up node and a second pull-up node under the control of the signal input end, the discharge sub-circuit discharges the second pull-up node under the control of the second pull-up node, and the output sub-circuit provides signals of a clock signal input end and the second pull-up node to a signal output end under the control of the first pull-up node and a reference node; the pull-down sub-circuit provides a signal of a second power supply end to the first pull-up node, the second pull-up node, the reference node and the signal output end under the control of the pull-down node. The compensation of the grid voltage of the thin film transistor in the liquid crystal display is realized, and the stability of the shift register and the display quality of the display panel are improved.

Description

Shifting register, driving method thereof and grid driving circuit

Technical Field

The present invention relates to, but not limited to, the field of display technologies, and in particular, to a shift register unit, a driving method thereof, and a gate driving circuit.

Background

With the rapid development of flat panel display technology, the demand for the picture quality of a Thin film transistor liquid crystal display (TFT-LCD) panel is increasing. The Gate Driver On Array (GOA) technology integrates a Gate Driver Circuit (IC) of a display device On an Array substrate, and the GOA technology can reduce the usage amount of the IC, thereby reducing the production cost and power consumption of the product, and can also realize a narrow frame of the display device.

The general grid driving circuit is composed of a plurality of cascaded shift register units, each shift register unit outputs scanning signals to grid lines on an array substrate, in the working process of the traditional shift register unit, most of the time of outputting the scanning signals is negative pressure, a thin film transistor in a liquid crystal display is under negative bias for a long time, the threshold voltage of the thin film transistor can drift along with the change of time, when the drift range of the threshold voltage is too large, abnormal display is easy to cause, and particularly, the threshold voltage drift phenomenon is easy to occur in the structure of an oxide thin film transistor developed at present.

Disclosure of Invention

The application provides a shift register, a driving method thereof and a grid driving circuit, which can improve the display quality of a display panel.

An embodiment of the present application provides a shift register, including: an input sub-circuit, a discharge sub-circuit, an output sub-circuit, a pull-up sub-circuit, a pull-down sub-circuit, and a reset sub-circuit, wherein: the input sub-circuit is respectively connected with the signal input end, the first pull-up node and the second pull-up node and is used for providing signals of the signal input end for the first pull-up node and the second pull-up node under the control of the signal input end; the discharging sub-circuit is respectively connected with the second pull-up node and the reference node and is used for discharging the second pull-up node under the control of the second pull-up node; the output sub-circuit is respectively connected with the clock signal input end, the first pull-up node, the second pull-up node, the reference node and the signal output end and is used for providing signals of the clock signal input end and the second pull-up node for the signal output end under the control of the first pull-up node and the reference node; the pull-up sub-circuit is respectively connected with the first power supply end and the pull-down node and is used for providing a signal of the first power supply end to the pull-down node under the control of the first power supply end; the pull-down sub-circuit is respectively connected with the first pull-up node, the second pull-up node, the pull-down node, the reference node, the second power supply end and the signal output end, and is used for providing a signal of the second power supply end for the pull-down node under the control of the first pull-up node and providing a signal of the second power supply end for the first pull-up node, the second pull-up node, the reference node and the signal output end under the control of the pull-down node; the reset sub-circuit is respectively connected with the reset signal input end, the second power end, the first pull-up node and the reference node, and is used for providing signals of the second power end for the first pull-up node and the reference node under the control of the reset signal input end.

Optionally, the input sub-circuit comprises: a first transistor and a second transistor, wherein: a control electrode and a first electrode of the first transistor are connected with the signal input end, and a second electrode of the first transistor is connected with the first pull-up node; and the control electrode and the first electrode of the second transistor are connected with the signal input end, and the second electrode of the second transistor is connected with the second pull-up node.

Optionally, the discharge sub-circuit comprises: a third transistor, wherein: a control electrode and a first electrode of the third transistor are coupled to the second pull-up node, and a second electrode of the third transistor is coupled to the reference node.

Optionally, the output sub-circuit comprises: a fourth transistor, a fifth transistor, a first capacitor, and a second capacitor, wherein: a control electrode of the fourth transistor is connected with the first pull-up node, a first electrode of the fourth transistor is connected with the clock signal input end, and a second electrode of the fourth transistor is connected with the reference node; a control electrode of the fifth transistor is connected with the reference node, a first electrode of the fifth transistor is connected with the second pull-up node, and a second electrode of the fifth transistor is connected with the signal output end; one end of the first capacitor is connected with the first pull-up node, and the other end of the first capacitor is connected with the reference node; one end of the second capacitor is connected with the second pull-up node, and the other end of the second capacitor is connected with the reference node.

Optionally, the pull-up sub-circuit comprises: a sixth transistor and a seventh transistor, wherein: a control electrode and a first electrode of the sixth transistor are connected with the first power supply end, and a second electrode of the sixth transistor is connected with a fifth node; a control electrode of the seventh transistor is connected to the fifth node, a first electrode of the seventh transistor is connected to the first power terminal, and a second electrode of the seventh transistor is connected to the pull-down node.

Optionally, the pull-down sub-circuit comprises: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor, wherein: a control electrode of the eighth transistor is connected to the first pull-up node, a first electrode of the eighth transistor is connected to a fifth node, and a second electrode of the eighth transistor is connected to the second power supply terminal; a control electrode of the ninth transistor is connected with the first pull-up node, a first electrode of the ninth transistor is connected with the pull-down node, and a second electrode of the ninth transistor is connected with the second power supply terminal; a control electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the second power source terminal; a control electrode of the eleventh transistor is connected with the pull-down node, a first electrode of the eleventh transistor is connected with the signal output end, and a second electrode of the eleventh transistor is connected with the second power supply end; a control electrode of the twelfth transistor is connected with the pull-down node, a first electrode of the twelfth transistor is connected with the second pull-up node, and a second electrode of the twelfth transistor is connected with the second power supply end; a control electrode of the thirteenth transistor is connected to the pull-down node, a first electrode of the thirteenth transistor is connected to the reference node, and a second electrode of the thirteenth transistor is connected to the second power source terminal.

Optionally, the reset sub-circuit comprises: a fourteenth transistor and a fifteenth transistor, wherein: a control electrode of the fourteenth transistor is connected to the reset signal input terminal, a first electrode of the fourteenth transistor is connected to the first pull-up node, and a second electrode of the fourteenth transistor is connected to the second power source terminal; a control electrode of the fifteenth transistor is connected to the reset signal input terminal, a first electrode of the fifteenth transistor is connected to the reference node, and a second electrode of the fifteenth transistor is connected to the second power source terminal.

Optionally, the input sub-circuit comprises: a first transistor and a second transistor, the discharge sub-circuit including: a third transistor, the output sub-circuit comprising: a fourth transistor, a fifth transistor, a first capacitor, and a second capacitor, the pull-up sub-circuit comprising: a sixth transistor and a seventh transistor, the pull-down sub-circuit comprising: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor, the reset sub-circuit including: a fourteenth transistor and a fifteenth transistor, wherein: a control electrode and a first electrode of the first transistor are connected with the signal input end, and a second electrode of the first transistor is connected with the first pull-up node; a control electrode and a first electrode of the second transistor are connected with the signal input end, and a second electrode of the second transistor is connected with the second pull-up node; a control electrode and a first electrode of the third transistor are connected with the second pull-up node, and a second electrode of the third transistor is connected with the reference node; a control electrode of the fourth transistor is connected with the first pull-up node, a first electrode of the fourth transistor is connected with the clock signal input end, and a second electrode of the fourth transistor is connected with the reference node; a control electrode of the fifth transistor is connected with the reference node, a first electrode of the fifth transistor is connected with the second pull-up node, and a second electrode of the fifth transistor is connected with the signal output end; one end of the first capacitor is connected with the first pull-up node, and the other end of the first capacitor is connected with the reference node; one end of the second capacitor is connected with the second pull-up node, and the other end of the second capacitor is connected with the reference node; a control electrode and a first electrode of the sixth transistor are connected with the first power supply end, and a second electrode of the sixth transistor is connected with a fifth node; a control electrode of the seventh transistor is connected to the fifth node, a first electrode of the seventh transistor is connected to the first power supply terminal, and a second electrode of the seventh transistor is connected to the pull-down node; a control electrode of the eighth transistor is connected to the first pull-up node, a first electrode of the eighth transistor is connected to a fifth node, and a second electrode of the eighth transistor is connected to the second power supply terminal; a control electrode of the ninth transistor is connected with the first pull-up node, a first electrode of the ninth transistor is connected with the pull-down node, and a second electrode of the ninth transistor is connected with the second power supply terminal; a control electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the second power source terminal; a control electrode of the eleventh transistor is connected with the pull-down node, a first electrode of the eleventh transistor is connected with the signal output end, and a second electrode of the eleventh transistor is connected with the second power supply end; a control electrode of the twelfth transistor is connected with the pull-down node, a first electrode of the twelfth transistor is connected with the second pull-up node, and a second electrode of the twelfth transistor is connected with the second power supply end; a control electrode of the thirteenth transistor is connected with the pull-down node, a first electrode of the thirteenth transistor is connected with the reference node, and a second electrode of the thirteenth transistor is connected with the second power supply terminal; a control electrode of the fourteenth transistor is connected to the reset signal input terminal, a first electrode of the fourteenth transistor is connected to the first pull-up node, and a second electrode of the fourteenth transistor is connected to the second power source terminal; a control electrode of the fifteenth transistor is connected to the reset signal input terminal, a first electrode of the fifteenth transistor is connected to the reference node, and a second electrode of the fifteenth transistor is connected to the second power source terminal.

An embodiment of the present application further provides a gate driving circuit, including: a plurality of cascaded shift registers as described in any of the preceding, wherein: the signal input end of the first-stage shift register is connected with the first initial signal input end, the signal input end of the second-stage shift register is connected with the second initial signal input end, the signal input end of the (N +3) th-stage shift register is connected with the signal output end of the (N +1) th-stage shift register, the signal output end of the (N +2) th-stage shift register is connected with the reset signal input end of the (N +1) th-stage shift register, and N is an integer greater than or equal to 0; the first power supply end of each stage of shift register is connected with a first external power line; a second power supply end of each stage of shift register is connected with an external second power line; the clock signal input end of the (3N +1) th-stage shift register is connected with an external first clock signal line, the clock signal input end of the (3N +2) th-stage shift register is connected with an external second clock signal line, and the clock signal input end of the (3N +3) th-stage shift register is connected with an external third clock signal line.

An embodiment of the present application further provides a driving method of a shift register, which is applied to the shift register described in any of the foregoing paragraphs, where the method includes: the input sub-circuit provides signals of the signal input end to the first pull-up node and the second pull-up node under the control of the signal input end; the pull-down sub-circuit provides a signal of a second power supply end to the pull-down node under the control of the first pull-up node; the electronic discharge circuit discharges the second pull-up node under the control of the second pull-up node; the output sub-circuit provides signals of a clock signal input end and a second pull-up node to a signal output end under the control of the first pull-up node and the reference node; the reset sub-circuit provides signals of a second power supply end to the first pull-up node and the reference node under the control of a reset signal input end; the pull-up sub-circuit provides a signal of the first power supply end to the pull-down node under the control of the first power supply end; the pull-down sub-circuit provides a signal of a second power supply end to the first pull-up node, the second pull-up node, the reference node and the signal output end under the control of the pull-down node.

Compared with the prior art, the shift register, the driving method thereof and the gate driving circuit provide signals of the signal input end to the first pull-up node and the second pull-up node through the input sub-circuit, the discharge sub-circuit discharges the second pull-up node under the control of the second pull-up node, and the output sub-circuit provides signals of the clock signal input end and the second pull-up node to the signal output end under the control of the first pull-up node and the reference node, so that the compensation of the gate voltage of the thin film transistor in the liquid crystal display is realized, and the stability of the shift register and the display quality of the display panel are improved.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the present application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.

Drawings

The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure;

fig. 2 is an equivalent circuit diagram of an input sub-circuit according to an embodiment of the present disclosure;

fig. 3 is an equivalent circuit diagram of a discharge sub-circuit according to an embodiment of the present disclosure;

fig. 4 is an equivalent circuit diagram of an output sub-circuit according to an embodiment of the present disclosure;

fig. 5 is an equivalent circuit diagram of a pull-up sub-circuit according to an embodiment of the present disclosure;

fig. 6 is an equivalent circuit diagram of a pull-down sub-circuit according to an embodiment of the present disclosure;

fig. 7 is an equivalent circuit diagram of a reset sub-circuit according to an embodiment of the present disclosure;

fig. 8 is an equivalent circuit diagram of a shift register according to an embodiment of the present application;

fig. 9 is a timing diagram illustrating an operation of a shift register according to an embodiment of the present disclosure;

fig. 10 is a flowchart of a driving method of a shift register according to an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.

Description of reference numerals:

INPUT-signal INPUT; OUTPUT-signal OUTPUT terminal;

CLK-clock signal input; RESET-RESET signal input;

VDD — the first power supply terminal; VSS — a second power supply terminal;

PU — first pull-up node; PO-second pull-up node;

PD — pull down node; POC-reference node;

PD _ CN — fifth node; C1-C2-capacitance;

M1-M15-transistor.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

Unless otherwise defined, technical or scientific terms used in the disclosure of the embodiments of the present application should have the ordinary meaning as understood by those having ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar terms in the embodiments of the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that a particular element or item appears in front of the word or is detected by mistake, and that the word or item appears after the word or item and its equivalents, but does not exclude other elements or misdetections.

It will be appreciated by those skilled in the art that the transistors employed in all embodiments of the present application may be thin film transistors or field effect transistors or other devices having the same characteristics. Preferably, the thin film transistor used in the embodiment of the present application may be an oxide semiconductor transistor. Since the source and drain of the transistor used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present application, in order to distinguish two electrodes of a transistor except for a gate, one of the electrodes is referred to as a first electrode, the other electrode is referred to as a second electrode, the first electrode may be a source or a drain, and the second electrode may be a drain or a source.

Fig. 1 is a schematic structural diagram of a shift register provided in an embodiment of the present application, and as shown in fig. 1, the shift register provided in the embodiment of the present application includes: the circuit comprises an input sub-circuit, a discharge sub-circuit, an output sub-circuit, a pull-up sub-circuit, a pull-down sub-circuit and a reset sub-circuit.

Specifically, the INPUT sub-circuit is respectively connected to the signal INPUT terminal INPUT, the first pull-up node PU and the second pull-up node PO, and is configured to provide the signal of the signal INPUT terminal INPUT to the first pull-up node PU and the second pull-up node PO under the control of the signal INPUT terminal INPUT; the discharging sub-circuit is respectively connected with the second pull-up node PO and the reference node POC and is used for discharging the second pull-up node PO under the control of the second pull-up node PO; the OUTPUT sub-circuit is respectively connected with the clock signal input end CLK, the first pull-up node PU, the second pull-up node PO, the reference node POC and the signal OUTPUT end OUTPUT, and is used for providing signals of the clock signal input end CLK and the second pull-up node PO for the signal OUTPUT end OUTPUT under the control of the first pull-up node PU and the reference node POC; the pull-up sub-circuit is respectively connected with the first power supply end VDD and the pull-down node PD and is used for providing a signal of the first power supply end VDD to the pull-down node PD under the control of the first power supply end VDD; the pull-down sub-circuit is respectively connected with the first pull-up node PU, the second pull-up node PO, the pull-down node PD, the reference node POC, the second power supply end VSS and the signal OUTPUT end OUTPUT, and is used for providing signals of the second power supply end VSS for the first pull-up node PU, the second pull-up node PO, the reference node POC and the signal OUTPUT end OUTPUT under the control of the first pull-up node PU and the pull-down node PD; the RESET sub-circuit is connected to the RESET signal input terminal RESET, the second power source terminal VSS, the first pull-up node PU and the reference node POC, respectively, for providing signals of the second power source terminal VSS to the first pull-up node PU and the reference node POC under the control of the RESET signal input terminal RESET.

The shift register provides signals of a signal INPUT end INPUT to a first pull-up node PU and a second pull-up node PO through an INPUT sub-circuit, a discharge sub-circuit discharges the second pull-up node PO under the control of the second pull-up node PO, an OUTPUT sub-circuit provides signals of a clock signal INPUT end CLK and the second pull-up node PO to a signal OUTPUT end OUTPUT under the control of the first pull-up node PU and a reference node POC, compensation of grid voltage of a thin film transistor in a liquid crystal display is achieved, and stability of the shift register and display quality of a display panel are improved.

Optionally, fig. 2 is an equivalent circuit diagram of an input sub-circuit provided in the embodiment of the present application, and as shown in fig. 2, the input sub-circuit provided in the embodiment of the present application includes: a first transistor M1 and a second transistor M2.

Specifically, a control electrode and a first electrode of the first transistor M1 are connected to the signal INPUT terminal INPUT, and a second electrode of the first transistor M1 is connected to the first pull-up node PU; a control electrode and a first electrode of the second transistor M2 are connected to the signal INPUT terminal INPUT, and a second electrode of the second transistor M2 is connected to the second pull-up node PO.

An exemplary structure of the input sub-circuit is specifically shown in fig. 2. Those skilled in the art will readily appreciate that the implementation of the input sub-circuits is not so limited, so long as their respective functions are achieved.

Optionally, fig. 3 is an equivalent circuit diagram of the discharge sub-circuit provided in the embodiment of the present application, and as shown in fig. 3, the discharge sub-circuit provided in the embodiment of the present application includes: and a third transistor M3.

Specifically, the control electrode and the first electrode of the third transistor M3 are connected to the second pull-up node PO, and the second electrode of the third transistor M3 is connected to the reference node POC.

An exemplary structure of the discharge sub-circuit is specifically shown in fig. 3. It is easily understood by those skilled in the art that the implementation of the discharge sub-circuit is not limited thereto as long as its respective functions can be realized.

Optionally, fig. 4 is an equivalent circuit diagram of an output sub-circuit provided in the embodiment of the present application, and as shown in fig. 4, the output sub-circuit provided in the embodiment of the present application includes: a fourth transistor M4, a fifth transistor M5, a first capacitor C1 and a second capacitor C2.

Specifically, the control electrode of the fourth transistor M4 is connected to the first pull-up node PU, the first electrode of the fourth transistor M4 is connected to the clock signal input terminal CLK, and the second electrode of the fourth transistor M4 is connected to the reference node POC; a control electrode of the fifth transistor M5 is connected to the reference node POC, a first electrode of the fifth transistor M5 is connected to the second pull-up node PO, and a second electrode of the fifth transistor M5 is connected to the signal OUTPUT terminal OUTPUT; one end of the first capacitor C1 is connected to the first pull-up node PU, and the other end of the first capacitor C1 is connected to the reference node POC; one terminal of the second capacitor C2 is connected to the second pull-up node PO, and the other terminal of the second capacitor C2 is connected to the reference node POC.

One exemplary structure of the output sub-circuit is specifically shown in fig. 4. Those skilled in the art will readily appreciate that the implementation of the output sub-circuits is not limited thereto as long as their respective functions can be implemented.

Optionally, fig. 5 is an equivalent circuit diagram of a pull-up sub-circuit provided in the embodiment of the present application, and as shown in fig. 5, the pull-up sub-circuit provided in the embodiment of the present application includes: a sixth transistor M6 and a seventh transistor M7.

Specifically, the control electrode and the first electrode of the sixth transistor M6 are connected to the first power terminal VDD, and the second electrode of the sixth transistor M6 is connected to the fifth node PD _ CN; a control electrode of the seventh transistor M7 is connected to the fifth node PD _ CN, a first electrode of the seventh transistor M7 is connected to the first power source terminal VDD, and a second electrode of the seventh transistor M7 is connected to the pull-down node PD.

One exemplary structure of the pull-up sub-circuit is specifically shown in fig. 5. It is easily understood by those skilled in the art that the implementation of the pull-up sub-circuit is not limited thereto as long as its respective functions can be realized.

Optionally, fig. 6 is an equivalent circuit diagram of the pull-down sub-circuit provided in the embodiment of the present application, and as shown in fig. 6, the pull-down sub-circuit provided in the embodiment of the present application includes: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13.

Specifically, a control electrode of the eighth transistor M8 is connected to the first pull-up node PU, a first electrode of the eighth transistor M8 is connected to the fifth node PD _ CN, and a second electrode of the eighth transistor M8 is connected to the second power source terminal VSS; a control electrode of the ninth transistor M9 is connected to the first pull-up node PU, a first electrode of the ninth transistor M9 is connected to the pull-down node PD, and a second electrode of the ninth transistor M9 is connected to the second power source terminal VSS; a control electrode of the tenth transistor M10 is connected to the pull-down node PD, a first electrode of the tenth transistor M10 is connected to the first pull-up node PU, and a second electrode of the tenth transistor M10 is connected to the second power source terminal VSS; a control electrode of the eleventh transistor M11 is connected to the pull-down node PD, a first electrode of the eleventh transistor M11 is connected to the signal OUTPUT terminal OUTPUT, and a second electrode of the eleventh transistor M11 is connected to the second power source terminal VSS; a control electrode of the twelfth transistor M12 is connected to the pull-down node PD, a first electrode of the twelfth transistor M12 is connected to the second pull-up node PO, and a second electrode of the twelfth transistor M12 is connected to the second power source terminal VSS; a control electrode of the thirteenth transistor M13 is connected to the pull-down node PD, a first electrode of the thirteenth transistor M13 is connected to the reference node POC, and a second electrode of the thirteenth transistor M13 is connected to the second power source terminal VSS.

One exemplary structure of the pull-down sub-circuit is specifically shown in fig. 6. Those skilled in the art will readily appreciate that the implementation of the pull-down sub-circuits is not so limited, so long as their respective functions are achieved.

Optionally, fig. 7 is an equivalent circuit diagram of a reset sub-circuit provided in the embodiment of the present application, and as shown in fig. 7, the reset sub-circuit provided in the embodiment of the present application includes: a fourteenth transistor M14 and a fifteenth transistor M15.

Specifically, a control electrode of the fourteenth transistor M14 is connected to the RESET signal input terminal RESET, a first electrode of the fourteenth transistor M14 is connected to the first pull-up node PU, and a second electrode of the fourteenth transistor M14 is connected to the second power supply terminal VSS; a control electrode of the fifteenth transistor M15 is connected to the RESET signal input terminal RESET, a first electrode of the fifteenth transistor M15 is connected to the reference node POC, and a second electrode of the fifteenth transistor M15 is connected to the second power source terminal VSS.

One exemplary structure of the reset sub-circuit is specifically shown in fig. 7. Those skilled in the art will readily appreciate that the implementation of the reset sub-circuit is not so limited as long as its respective function is achieved.

Fig. 8 is an equivalent circuit diagram of a shift register according to an embodiment of the present application, and as shown in fig. 8, an input sub-circuit in the shift register according to the embodiment of the present application includes: a first transistor M1 and a second transistor M2, the discharge sub-circuit comprising: the third transistor M3, the output sub-circuit, includes: a fourth transistor M4, a fifth transistor M5, a first capacitor C1 and a second capacitor C2, the pull-up sub-circuit comprising: a sixth transistor M6 and a seventh transistor M7, the pull-down sub-circuit comprising: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13, and the reset sub-circuit includes: a fourteenth transistor M14 and a fifteenth transistor M15.

Specifically, a control electrode and a first electrode of the first transistor M1 are connected to the signal INPUT terminal INPUT, and a second electrode of the first transistor M1 is connected to the first pull-up node PU; a control electrode and a first electrode of the second transistor M2 are connected to the signal INPUT terminal INPUT, and a second electrode of the second transistor M2 is connected to the second pull-up node PO; a control electrode and a first electrode of the third transistor M3 are connected to the second pull-up node PO, and a second electrode of the third transistor M3 is connected to the reference node POC; a control electrode of the fourth transistor M4 is connected to the first pull-up node PU, a first electrode of the fourth transistor M4 is connected to the clock signal input terminal CLK, and a second electrode of the fourth transistor M4 is connected to the reference node POC; a control electrode of the fifth transistor M5 is connected to the reference node POC, a first electrode of the fifth transistor M5 is connected to the second pull-up node PO, and a second electrode of the fifth transistor M5 is connected to the signal OUTPUT terminal OUTPUT; one end of the first capacitor C1 is connected to the first pull-up node PU, and the other end of the first capacitor C1 is connected to the reference node POC; one end of the second capacitor C2 is connected to the second pull-up node PO, and the other end of the second capacitor C2 is connected to the reference node POC; a control electrode and a first electrode of the sixth transistor M6 are connected to the first power terminal VDD, and a second electrode of the sixth transistor M6 is connected to the fifth node PD _ CN; a control electrode of the seventh transistor M7 is connected to the fifth node PD _ CN, a first electrode of the seventh transistor M7 is connected to the first power source terminal VDD, and a second electrode of the seventh transistor M7 is connected to the pull-down node PD; a control electrode of the eighth transistor M8 is connected to the first pull-up node PU, a first electrode of the eighth transistor M8 is connected to the fifth node PD _ CN, and a second electrode of the eighth transistor M8 is connected to the second power source terminal VSS; a control electrode of the ninth transistor M9 is connected to the first pull-up node PU, a first electrode of the ninth transistor M9 is connected to the pull-down node PD, and a second electrode of the ninth transistor M9 is connected to the second power source terminal VSS; a control electrode of the tenth transistor M10 is connected to the pull-down node PD, a first electrode of the tenth transistor M10 is connected to the first pull-up node PU, and a second electrode of the tenth transistor M10 is connected to the second power source terminal VSS; a control electrode of the eleventh transistor M11 is connected to the pull-down node PD, a first electrode of the eleventh transistor M11 is connected to the signal OUTPUT terminal OUTPUT, and a second electrode of the eleventh transistor M11 is connected to the second power source terminal VSS; a control electrode of the twelfth transistor M12 is connected to the pull-down node PD, a first electrode of the twelfth transistor M12 is connected to the second pull-up node PO, and a second electrode of the twelfth transistor M12 is connected to the second power source terminal VSS; a control electrode of the thirteenth transistor M13 is connected to the pull-down node PD, a first electrode of the thirteenth transistor M13 is connected to the reference node POC, and a second electrode of the thirteenth transistor M13 is connected to the second power source terminal VSS; a control electrode of the fourteenth transistor M14 is connected to the RESET signal input terminal RESET, a first electrode of the fourteenth transistor M14 is connected to the first pull-up node PU, and a second electrode of the fourteenth transistor M14 is connected to the second power source terminal VSS; a control electrode of the fifteenth transistor M15 is connected to the RESET signal input terminal RESET, a first electrode of the fifteenth transistor M15 is connected to the reference node POC, and a second electrode of the fifteenth transistor M15 is connected to the second power source terminal VSS.

Exemplary structures of the input sub-circuit, the discharge sub-circuit, the output sub-circuit, the pull-up sub-circuit, the pull-down sub-circuit, and the reset sub-circuit are specifically shown in fig. 8. Those skilled in the art will readily appreciate that the implementation of each of the above sub-circuits is not limited thereto as long as their respective functions can be achieved.

In the embodiment, the transistors M1 to M15 may be both N-type thin film transistors or P-type thin film transistors, so that the process flow can be unified, which is helpful for improving the yield of the product. For transistors with different doping types, only the effective level of the related signal needs to be adjusted. For example, when all the switching elements are N-type thin film transistors, the active level thereof is a high level, and when all the switching elements are P-type thin film transistors, the active level thereof is a low level. In addition, in consideration of the fact that the low-temperature polysilicon thin film transistor has a small leakage current, all transistors are preferably low-temperature polysilicon thin film transistors in the embodiments of the present application, and the thin film transistor may specifically be a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure, as long as the switching function can be achieved.

The first capacitor C1 and the second capacitor C2 may be liquid crystal capacitors formed by the pixel electrode and the common electrode, or may be equivalent capacitors formed by the liquid crystal capacitors formed by the pixel electrode and the common electrode and the storage capacitor, but the present invention is not limited thereto.

Taking the transistors M1 to M15 in the shift register provided in the embodiment of the present application as an example, the operation process of a shift register unit in a frame period is specifically described with reference to the shift register unit shown in fig. 8 and the signal waveform diagram shown in fig. 9. As shown in fig. 8, the shift register according to the embodiment of the present application includes 15 transistor units (M1 to M15), 2 capacitor units (C1, C2), 3 INPUT terminals (INPUT, RESET, CLK), 1 OUTPUT terminal (OUTPUT), and 2 power source terminals (VDD and VSS), wherein the first power source terminal VDD continuously provides a high-level signal, and the second VSS continuously provides a low-level signal. The working process comprises the following steps:

in the first stage S1, i.e., the INPUT stage, the INPUT signal at the signal INPUT terminal INPUT is at a high level, the first transistor M1 and the second transistor M2 are turned on, the potentials of the first pull-up node PU and the second pull-up node PO are pulled high, at this time, the fourth transistor M4, the eighth transistor M8, the ninth transistor M9, the sixth transistor M6, the seventh transistor M7, and the third transistor M3 are turned on, the first capacitor C1 and the second capacitor C2 start to be charged, the potential of the pull-down node PD is pulled down to a low level of the second power terminal VSS by the ninth transistor M9, the potential of the pull-down node PD is not pulled up by the sixth transistor M6 and the seventh transistor M7 because the ninth transistor M9 and the eighth transistor M8 are turned on, and the potential of the pull-down node PD is pulled down to a low level by the fourth transistor M4 because the INPUT signal at the clock signal INPUT terminal CLK is at a low level.

A second stage S2, namely a discharging stage, in which the INPUT signal at the signal INPUT terminal INPUT is at a low level, the first transistor M1 and the second transistor M2 are turned off, the INPUT signal at the clock signal INPUT terminal CLK is at a low level, the potential of the first pull-up node PU is kept at a high level, the potential of the pull-down node PD is kept at a low level, the potential of the reference node POC is kept at a low level, the second pull-up node PO is discharged through the third transistor M3, when the voltage of the second pull-up node PO drops to the threshold voltage Vth of the third transistor M3, the third transistor M3 is turned off, and at this time, the voltage value stored in the second capacitor C2 is the threshold voltage Vth of the third transistor M3, namely, the voltage value of the second pull-up node PO;

in the third phase, i.e. the output phase, the input signal at the clock signal input terminal CLK is at a high level, and since the fourth transistor M4 is still in a conducting state, the potential of the reference node POC is pulled up to the high level Vgh at the clock signal input terminal CLK by the fourth transistor M4. Due to the bootstrap action of the first capacitor C1 and the second capacitor C2, the potentials of the first pull-up node PU and the second pull-up node PO are further pulled up along with the pulling up of the potential of the reference node POC, at this time, the potential value of the second pull-up node PO is pulled up to Vgh + Vth, the fifth transistor M5 is turned on, and the signal Output terminal Output outputs the potential value Vgh + Vth of the second pull-up node PO, i.e., the gate driving signal.

A fourth stage S4, i.e., a Reset stage, in which an input signal at the Reset signal input terminal Reset is at a high level, the fourteenth transistor M14 and the fifteenth transistor M15 are turned on, the fourteenth transistor M14 pulls down the potential of the first pull-up node PU to a low level of the second power source terminal VSS, the fifteenth transistor M15 pulls down the potential of the reference node POC to a low level of the second power source terminal VSS, the eighth transistor M8 and the ninth transistor M9 are turned off, the sixth transistor M6 and the seventh transistor M7 pull up the potential of the pull-down node PD, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12 and the thirteenth transistor M13 are turned on, the potential of the first pull-up node PU is further pulled down by the tenth transistor M10, the potential of the signal OUTPUT terminal OUTPUT is pulled down by the eleventh transistor M11, the potential of the second pull-up node PO is pulled down by the twelfth transistor M12, and the potential of the reference node POC is further pulled down by the thirteenth transistor M13.

In this embodiment, after the first stage S1, the INPUT signal at the signal INPUT terminal INPUT is continuously at a low level; after the third stage S3, the OUTPUT signal of the signal OUTPUT terminal OUTPUT continues to be at the low level; after the fourth stage S4, the input signal of the RESET signal input terminal RESET continues to be at a low level; in all stages, the input signal of the first power terminal VDD continues to be at a high level; the input signal of the second power source terminal VSS continues to be at a low level.

Based on the working time sequence, the shift register unit completes the shift register function, realizes the compensation of the grid voltage of the thin film transistor in the liquid crystal display, and improves the stability of the shift register and the display quality of the display panel.

Based on the same inventive concept, some embodiments of the present invention further provide a driving method of a shift register, which is applied to the shift register provided in the foregoing embodiments, and the shift register includes: fig. 10 is a flowchart of a driving method of a shift register according to an embodiment of the present disclosure, and as shown in fig. 10, the method specifically includes the following steps:

step 100, the input sub-circuit provides signals of the signal input end to the first pull-up node and the second pull-up node under the control of the signal input end; the pull-down sub-circuit provides a signal of the second power supply terminal to the pull-down node under the control of the first pull-up node.

Specifically, the input signal at the signal input terminal is a pulse signal, and in this step, the input signal at the signal input terminal is at a high level, and the input sub-circuit pulls up the potentials of the first pull-up node and the second pull-up node. The input signal of the second power supply end is low level, and the pull-down sub-circuit pulls down the pull-down node to the low level of the second power supply end.

Step 200, the discharging sub-circuit discharges the second pull-up node under the control of the second pull-up node.

Specifically, in this step, the input signal at the signal input terminal is at a low level, and the discharge sub-circuit pulls down the potential of the second pull-up node to the level of the threshold voltage of the thin film transistor.

Step 300, the output sub-circuit provides the clock signal input end and the signal of the second pull-up node to the signal output end under the control of the first pull-up node and the reference node.

Specifically, in this step, the input signal of the clock signal input terminal is at a high level, and the output signal of the signal output terminal is the sum of the potentials of the clock signal input terminal and the second pull-up node.

In step 400, the reset sub-circuit provides a signal of the second power supply terminal to the first pull-up node and the reference node under the control of the reset signal input terminal.

Specifically, the input signal of the reset signal input terminal is a pulse signal, in this step, the input signal of the reset signal input terminal is a high level, and the reset sub-circuit pulls down the levels of the first pull-up node and the reference node to a low level signal of the second power supply terminal, so as to avoid noise.

In step 500, the pull-up sub-circuit provides a signal of the first power source terminal to the pull-down node under the control of the first power source terminal.

Specifically, in this step, the input signal of the first power source terminal is at a high level, and the pull-up sub-circuit pulls up the potential of the pull-down node under the control of the first power source terminal.

Step 600, the pull-down sub-circuit provides a signal of a second power end to the first pull-up node, the second pull-up node, the reference node and the signal output end under the control of the pull-down node.

Specifically, the pull-down sub-circuit pulls down the levels of the first pull-up node, the second pull-up node, the reference node and the signal output terminal to a low level signal of the second power supply terminal to avoid noise.

According to the technical scheme provided by the invention, the input sub-circuit provides signals of the signal input end to the first pull-up node and the second pull-up node, the discharge sub-circuit discharges the second pull-up node under the control of the second pull-up node, and the output sub-circuit provides signals of the clock signal input end and the second pull-up node to the signal output end under the control of the first pull-up node and the reference node, so that the compensation of the grid voltage of the thin film transistor in the liquid crystal display is realized, and the stability of the shift register and the display quality of the display panel are improved.

Based on the same inventive concept, an embodiment of the present application further provides a gate driving circuit, and fig. 11 is a schematic structural diagram of the gate driving circuit provided in the embodiment of the present application, as shown in fig. 11, the gate driving circuit includes: a plurality of cascaded shift registers, comprising: the shift register comprises a first-stage shift register GOA (1), a second-stage shift register GOA (2), a third-stage shift register GOA (3), a fourth-stage shift register GOA (4) and the like.

Specifically, a signal input end of the first-stage shift register is connected with a first initial signal input end, a signal input end of the second-stage shift register is connected with a second initial signal input end, a signal input end of the (N +3) th-stage shift register is connected with a signal output end of the (N +1) th-stage shift register, a signal output end of the (N +2) th-stage shift register is connected with a reset signal input end of the (N +1) th-stage shift register, and N is an integer greater than or equal to 0.

The first power supply end of each stage of shift register is connected with a first external power line; the second power supply terminal of each stage of the shift register is connected to a second power supply line outside.

The clock signal input end of the (3N +1) th-stage shift register is connected with an external first clock signal line, the clock signal input end of the (3N +2) th-stage shift register is connected with an external second clock signal line, and the clock signal input end of the (3N +3) th-stage shift register is connected with an external third clock signal line.

For example, the signal input terminal of the first stage shift register is connected to the first initial signal input terminal STV1, the clock signal input terminal of the first stage shift register is connected to the first clock signal line CLK, and the reset signal input terminal of the first stage shift register is connected to the signal output terminal GATE2 of the second stage shift register; the signal input end of the second-stage shift register is connected with a second initial signal input end STV2, the clock signal input end of the second-stage shift register is connected with a second clock signal line CLKb, and the reset signal input end of the second-stage shift register is connected with the signal output end GATE3 of the third-stage shift register; the signal input end of the third stage shift register is connected with the signal output end GATE1 of the first stage shift register, the clock signal input end of the third stage shift register is connected with the third clock signal line CLKC, the reset signal input end of the third stage shift register is connected with the signal output end GATE4 of the fourth stage shift register, and so on.

The shift register is provided in the first embodiment, and the implementation principle and the implementation effect are similar, which are not described herein again.

The following points need to be explained:

the drawings of the embodiments of the present application relate only to the structures related to the embodiments of the present application, and other structures may refer to general designs.

Without conflict, features of embodiments of the present invention, that is, embodiments, may be combined with each other to arrive at new embodiments.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A shift register, comprising: an input sub-circuit, a discharge sub-circuit, an output sub-circuit, a pull-up sub-circuit, a pull-down sub-circuit, and a reset sub-circuit, wherein:

the input sub-circuit is respectively connected with the signal input end, the first pull-up node and the second pull-up node and is used for providing signals of the signal input end for the first pull-up node and the second pull-up node under the control of the signal input end;

the discharging sub-circuit is respectively connected with the second pull-up node and the reference node and is used for discharging the second pull-up node under the control of the second pull-up node;

the output sub-circuit is respectively connected with the clock signal input end, the first pull-up node, the second pull-up node, the reference node and the signal output end, and is used for providing a signal of the clock signal input end for the reference node under the control of the first pull-up node and providing a signal of the second pull-up node for the signal output end under the control of the reference node;

the pull-up sub-circuit is respectively connected with the first power supply end and the pull-down node and is used for providing a signal of the first power supply end to the pull-down node under the control of the first power supply end;

the pull-down sub-circuit is respectively connected with the first pull-up node, the second pull-up node, the pull-down node, the reference node, the second power supply end and the signal output end, and is used for providing a signal of the second power supply end for the pull-down node under the control of the first pull-up node and providing a signal of the second power supply end for the first pull-up node, the second pull-up node, the reference node and the signal output end under the control of the pull-down node;

the reset sub-circuit is respectively connected with the reset signal input end, the second power end, the first pull-up node and the reference node, and is used for providing signals of the second power end for the first pull-up node and the reference node under the control of the reset signal input end.

2. The shift register of claim 1, wherein the input sub-circuit comprises: a first transistor and a second transistor, wherein:

a control electrode and a first electrode of the first transistor are connected with the signal input end, and a second electrode of the first transistor is connected with the first pull-up node;

and the control electrode and the first electrode of the second transistor are connected with the signal input end, and the second electrode of the second transistor is connected with the second pull-up node.

3. The shift register according to claim 1, wherein the discharge circuit comprises: a third transistor, wherein:

a control electrode and a first electrode of the third transistor are coupled to the second pull-up node, and a second electrode of the third transistor is coupled to the reference node.

4. The shift register of claim 1, wherein the output sub-circuit comprises: a fourth transistor, a fifth transistor, a first capacitor, and a second capacitor, wherein:

a control electrode of the fourth transistor is connected with the first pull-up node, a first electrode of the fourth transistor is connected with the clock signal input end, and a second electrode of the fourth transistor is connected with the reference node;

a control electrode of the fifth transistor is connected with the reference node, a first electrode of the fifth transistor is connected with the second pull-up node, and a second electrode of the fifth transistor is connected with the signal output end;

one end of the first capacitor is connected with the first pull-up node, and the other end of the first capacitor is connected with the reference node;

one end of the second capacitor is connected with the second pull-up node, and the other end of the second capacitor is connected with the reference node.

5. The shift register of claim 1, wherein the pull-up subcircuit comprises: a sixth transistor and a seventh transistor, wherein:

a control electrode and a first electrode of the sixth transistor are connected with the first power supply end, a second electrode of the sixth transistor is connected with a fifth node, and the fifth node is connected with the pull-down sub-circuit;

a control electrode of the seventh transistor is connected to the fifth node, a first electrode of the seventh transistor is connected to the first power terminal, and a second electrode of the seventh transistor is connected to the pull-down node.

6. The shift register of claim 1, wherein the pull-down subcircuit comprises: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor, wherein:

a control electrode of the eighth transistor is connected with the first pull-up node, a first electrode of the eighth transistor is connected with a fifth node, a second electrode of the eighth transistor is connected with the second power supply terminal, and the fifth node is connected with the pull-up sub-circuit;

a control electrode of the ninth transistor is connected with the first pull-up node, a first electrode of the ninth transistor is connected with the pull-down node, and a second electrode of the ninth transistor is connected with the second power supply terminal;

a control electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the second power source terminal;

a control electrode of the eleventh transistor is connected with the pull-down node, a first electrode of the eleventh transistor is connected with the signal output end, and a second electrode of the eleventh transistor is connected with the second power supply end;

a control electrode of the twelfth transistor is connected with the pull-down node, a first electrode of the twelfth transistor is connected with the second pull-up node, and a second electrode of the twelfth transistor is connected with the second power supply end;

a control electrode of the thirteenth transistor is connected to the pull-down node, a first electrode of the thirteenth transistor is connected to the reference node, and a second electrode of the thirteenth transistor is connected to the second power source terminal.

7. The shift register of claim 1, wherein the reset subcircuit comprises: a fourteenth transistor and a fifteenth transistor, wherein:

a control electrode of the fourteenth transistor is connected to the reset signal input terminal, a first electrode of the fourteenth transistor is connected to the first pull-up node, and a second electrode of the fourteenth transistor is connected to the second power source terminal;

a control electrode of the fifteenth transistor is connected to the reset signal input terminal, a first electrode of the fifteenth transistor is connected to the reference node, and a second electrode of the fifteenth transistor is connected to the second power source terminal.

8. The shift register of claim 1, wherein the input sub-circuit comprises: a first transistor and a second transistor, the discharge sub-circuit including: a third transistor, the output sub-circuit comprising: a fourth transistor, a fifth transistor, a first capacitor, and a second capacitor, the pull-up sub-circuit comprising: a sixth transistor and a seventh transistor, the pull-down sub-circuit comprising: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor, the reset sub-circuit including: a fourteenth transistor and a fifteenth transistor, wherein:

a control electrode and a first electrode of the second transistor are connected with the signal input end, and a second electrode of the second transistor is connected with the second pull-up node;

a control electrode and a first electrode of the third transistor are connected with the second pull-up node, and a second electrode of the third transistor is connected with the reference node;

one end of the second capacitor is connected with the second pull-up node, and the other end of the second capacitor is connected with the reference node;

a control electrode and a first electrode of the sixth transistor are connected with the first power supply end, and a second electrode of the sixth transistor is connected with a fifth node;

a control electrode of the seventh transistor is connected to the fifth node, a first electrode of the seventh transistor is connected to the first power supply terminal, and a second electrode of the seventh transistor is connected to the pull-down node;

a control electrode of the eighth transistor is connected to the first pull-up node, a first electrode of the eighth transistor is connected to a fifth node, and a second electrode of the eighth transistor is connected to the second power supply terminal;

a control electrode of the thirteenth transistor is connected with the pull-down node, a first electrode of the thirteenth transistor is connected with the reference node, and a second electrode of the thirteenth transistor is connected with the second power supply terminal;

9. A gate drive circuit, comprising: a plurality of cascaded shift registers according to any of claims 1-8, wherein:

the signal input end of the first-stage shift register is connected with the first initial signal input end, the signal input end of the second-stage shift register is connected with the second initial signal input end, the signal input end of the (N +3) th-stage shift register is connected with the signal output end of the (N +1) th-stage shift register, the signal output end of the (N +2) th-stage shift register is connected with the reset signal input end of the (N +1) th-stage shift register, and N is an integer greater than or equal to 0;

the first power supply end of each stage of shift register is connected with a first external power line; a second power supply end of each stage of shift register is connected with an external second power line;

10. A method for driving a shift register, which is applied to the shift register according to any one of claims 1 to 8, the method comprising:

the input sub-circuit provides signals of the signal input end to the first pull-up node and the second pull-up node under the control of the signal input end; the pull-down sub-circuit provides a signal of a second power supply end to the pull-down node under the control of the first pull-up node;

the electronic discharge circuit discharges the second pull-up node under the control of the second pull-up node;

the output sub-circuit provides a signal of a clock signal input end to a reference node under the control of a first pull-up node, and provides a signal of a second pull-up node to a signal output end under the control of the reference node;

the reset sub-circuit provides signals of a second power supply end to the first pull-up node and the reference node under the control of a reset signal input end;

the pull-up sub-circuit provides a signal of the first power supply end to the pull-down node under the control of the first power supply end;

the pull-down sub-circuit provides a signal of a second power supply end to the first pull-up node, the second pull-up node, the reference node and the signal output end under the control of the pull-down node.