CN110896064A - Semi-etched lead frame structure and manufacturing method thereof - Google Patents

Semi-etched lead frame structure and manufacturing method thereof Download PDF

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Publication number
CN110896064A
CN110896064A CN201911122929.0A CN201911122929A CN110896064A CN 110896064 A CN110896064 A CN 110896064A CN 201911122929 A CN201911122929 A CN 201911122929A CN 110896064 A CN110896064 A CN 110896064A
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CN
China
Prior art keywords
layer
pattern layer
lead frame
corrosion
etched
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Pending
Application number
CN201911122929.0A
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Chinese (zh)
Inventor
张凯
任鹏飞
陆晓燕
任姣
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Priority to CN201911122929.0A priority Critical patent/CN110896064A/en
Publication of CN110896064A publication Critical patent/CN110896064A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49534Multi-layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention relates to a half-etching lead frame structure and a manufacturing method thereof, wherein the lead frame structure comprises a first pattern layer (1), a second pattern layer (2) is arranged on the first pattern layer (1), a first corrosion-resistant layer (4) is arranged between the first pattern layer (1) and the second pattern layer (2), the peripheries of the first pattern layer (1), the second pattern layer (2) and the first corrosion-resistant layer (4) are encapsulated with an insulating material (3), a second corrosion-resistant layer (6) is arranged on part of the surface of the second pattern layer (2), and the area, which is not provided with the second corrosion-resistant layer (6), of the surface of the second pattern layer (2) is etched to the first corrosion-resistant layer (4) so as to form a half-etching groove (5). The invention solves the problem of uniformity which is difficult to solve by the traditional process, can meet more requirements of customers on half etching depth, and has the advantages of simple process, short production period, low control cost and greatly improved competitive advantage of products in the market.

Description

Semi-etched lead frame structure and manufacturing method thereof
Technical Field
The invention relates to a semi-etched lead frame structure and a manufacturing method thereof, belonging to the technical field of semiconductor packaging.
Background
With the continuous development of modern science, semiconductor packaging technology is more and more widely applied to various fields. The great application of the high-voltage power supply to the automobile electronics makes the requirement on the reliability of the high-voltage power supply high. In order to obtain better welding performance, at present, a half-etched area (as shown in fig. 1 and fig. 2) is formed on a plurality of lead frames aiming at a back pin, and an anti-oxidation coating can be electroplated on the surface of the half-etched area, so that after cutting, the exposed position of the side surface can cover the coating, and the side surface is not oxidized due to the protection of the coating during welding, so that the side surface can be well soaked in tin paste, and the welding is firmer.
In the existing half-etching process, the bottom of the half-etched region is not in a full flat state but is similar to a U shape (as shown in fig. 3), and a customer needs the U-shaped bottom flat region to be long enough due to the requirement of packaging performance, which is very strict in process requirement and difficult to meet the requirement. Moreover, the current etching process is affected by conditions, and once the depth required by a customer is deeper, a great extreme difference is caused, the requirements of the customer are difficult to meet, and the risk that a product is etched through exists. Limitations such as the above process conditions result in limitations in current half-etch products.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a half-etched lead frame structure and a manufacturing method thereof, aiming at the above prior art, the obtained half-etched depth has better uniformity, and can meet more different depth requirements.
The technical scheme adopted by the invention for solving the problems is as follows: a half-etching lead frame structure comprises a first graph layer, wherein a second graph layer is arranged on the first graph layer, a first corrosion resistant layer is arranged between the first graph layer and the second graph layer, the peripheries of the first graph layer, the second graph layer and the first corrosion resistant layer are encapsulated with insulating materials, a part of the surface of the second graph layer is provided with a second corrosion resistant layer, and the area, without the second corrosion resistant layer, of the surface of the second graph layer is etched to the first corrosion resistant layer to form a half-etching groove.
Preferably, all exposed metal layer surfaces of the lead frame structure are provided with surface metal plating layers.
A method of manufacturing a half-etched lead frame structure, the method comprising the steps of:
step one, taking a metal substrate;
step two, electroplating a first pattern layer on the front surface of the metal substrate;
step three, performing insulating material pre-encapsulation on the front surface of the metal substrate to encapsulate the first graphic layer;
step four, carrying out surface grinding on the encapsulated metal substrate to expose the first pattern layer;
step five, electroplating a first corrosion-resistant layer and a second pattern layer on the first pattern layer in sequence;
sixthly, performing insulating material pre-encapsulation again to encapsulate the first anti-corrosion layer and the second pattern layer;
step seven, grinding again to expose the second pattern layer;
step eight, etching off part of the metal substrate on the back surface, and exposing the first pattern layer from the back surface;
step nine, electroplating a second resist layer to protect the area which does not need to be half-etched;
step ten, directly etching to etch the semi-etched groove;
and step eleven, electroplating a metal oxidation resistant layer on all exposed metal surfaces.
Preferably, the pre-encapsulation in the third step and the sixth step adopts transfer injection molding, hot-press injection molding, film pressing or gluing.
Preferably, the pre-encapsulation insulating material in the third step and the sixth step adopts plastic package material, ABF film or insulating glue.
Preferably, the first resist in step five is nickel or tin.
Preferably, the second resist layer in the ninth step is made of nickel or tin.
Preferably, the metal antioxidation layer in the eleventh step adopts nickel gold, nickel palladium gold or tin.
Preferably, the step two to the step four are repeated for a plurality of times to produce the multilayer pattern.
Compared with the prior art, the invention has the advantages that:
the semi-etching lead frame structure and the manufacturing method thereof solve the problem of uniformity which is difficult to solve by the traditional process, can meet more semi-etching depth requirements of customers, and have the advantages of simple process, short production period, low control cost and great improvement on the competitive advantage of products in the market.
Drawings
Fig. 1 and 2 are schematic structural views of a conventional half-etching frame.
Fig. 3 is a cross-sectional view of a conventional half-etched region.
FIG. 4 is a schematic structural diagram of a half-etched lead frame structure according to the present invention.
Fig. 5-15 are process flow diagrams of a method for manufacturing a half-etched lead frame structure according to the present invention.
Wherein:
first graphic layer 1
Second graphics layer 2
Insulating material 3
First resist layer 4
Half-etched groove 5
Second resist layer 6
A metal oxidation resistant layer 7.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
As shown in fig. 4, a half-etched lead frame structure in the present embodiment includes a first pattern layer 1, a second pattern layer 2 is disposed on the first pattern layer 1, a first resist layer 4 is disposed between the first pattern layer 1 and the second pattern layer 2, an insulating material 3 is encapsulated around the first pattern layer 1, the second pattern layer 2 and the first resist layer 4, a portion of a surface of the second pattern layer 2 is disposed with a second resist layer 6, and a portion of a surface of the second pattern layer 2, where the second resist layer 6 is not disposed, is etched into the first resist layer 4 to form a half-etched groove 5;
and all exposed metal layer surfaces of the lead frame structure are provided with metal oxidation resistant layers 7.
The manufacturing method comprises the following steps:
step one, referring to fig. 5, a metal substrate is taken;
step two, referring to fig. 6, electroplating a first graphic layer on the front surface of the metal substrate;
step three, referring to fig. 7, pre-encapsulating the insulating material on the front surface of the metal substrate to encapsulate the first graphic layer;
the pre-encapsulation mode adopts a transfer injection molding, hot-press injection molding, film pressing or gluing mode; the pre-encapsulated insulating material is made of insulating materials such as plastic encapsulating material, ABF film, insulating glue and the like;
step four, referring to fig. 8, the surface of the encapsulated metal substrate is ground to expose the first pattern layer;
step five, referring to fig. 9, electroplating a first resist layer and a second pattern layer on the first pattern layer in sequence;
the first resist layer employs nickel, tin, or the like;
sixthly, referring to fig. 10, pre-encapsulating the insulating material again to encapsulate the first resist layer and the second pattern layer;
the pre-encapsulation mode adopts a transfer injection molding, hot-press injection molding, film pressing or gluing mode; the pre-encapsulated insulating material is made of insulating materials such as plastic encapsulating material, ABF film, insulating glue and the like;
step seven, referring to fig. 11, grinding again to expose the second pattern layer;
step eight, referring to fig. 12, etching off a part of the metal substrate on the back surface to expose the first pattern layer from the back surface;
step nine, referring to fig. 13, electroplating a second resist layer to protect the area not requiring half etching, and leaving part of the second pattern layer exposed;
the second resist layer employs nickel, tin, or the like;
step ten, referring to fig. 14, directly etching the surface of the second pattern layer to the first resist layer, and etching the half-etched groove;
step eleven, referring to fig. 15, electroplating a metal oxidation resistant layer on all exposed metal surfaces;
the metal oxidation resistant layer adopts nickel gold, nickel palladium gold, tin and the like.
And a multilayer pattern can be manufactured by repeating the second step to the fourth step.
In addition to the above embodiments, the present invention also includes other embodiments, and any technical solutions formed by equivalent transformation or equivalent replacement should fall within the scope of the claims of the present invention.

Claims (9)

1. A half-etched lead frame structure, characterized in that: the pattern structure comprises a first pattern layer (1), wherein a second pattern layer (2) is arranged on the first pattern layer (1), a first corrosion-resistant layer (4) is arranged between the first pattern layer (1) and the second pattern layer (2), insulating materials (3) are encapsulated at the peripheries of the first pattern layer (1), the second pattern layer (2) and the first corrosion-resistant layer (4), a second corrosion-resistant layer (6) is arranged on part of the surface of the second pattern layer (2), and the area, which is not provided with the second corrosion-resistant layer (6), of the surface of the second pattern layer (2) is etched to the first corrosion-resistant layer (4) so as to form a half-etched groove (5).
2. The half-etched lead frame structure according to claim 1, wherein: and all exposed metal layer surfaces of the lead frame structure are provided with surface metal coatings (7).
3. A method of fabricating a half-etched lead frame structure, said method comprising the steps of:
step one, taking a metal substrate;
step two, electroplating a first pattern layer on the front surface of the metal substrate;
step three, performing insulating material pre-encapsulation on the front surface of the metal substrate to encapsulate the first graphic layer;
step four, carrying out surface grinding on the encapsulated metal substrate to expose the first pattern layer;
step five, electroplating a first corrosion-resistant layer and a second pattern layer on the first pattern layer in sequence;
sixthly, performing insulating material pre-encapsulation again to encapsulate the first anti-corrosion layer and the second pattern layer;
step seven, grinding again to expose the second pattern layer;
step eight, etching off part of the metal substrate on the back surface, and exposing the first pattern layer from the back surface;
step nine, electroplating a second resist layer to protect the area which does not need to be half-etched;
step ten, directly etching to etch the semi-etched groove;
and step eleven, electroplating a metal oxidation resistant layer on all exposed metal surfaces.
4. The method of claim 3, wherein the step of forming the lead frame further comprises: and the pre-encapsulation mode in the third step and the sixth step adopts a transfer injection molding, hot-press injection molding, film pressing or gluing mode.
5. The method of claim 3, wherein the step of forming the lead frame further comprises: and step three and step six, the pre-packaging insulating material adopts plastic packaging material, ABF film or insulating glue.
6. The method of claim 3, wherein the step of forming the lead frame further comprises: the first resist layer in the fifth step adopts nickel or tin.
7. The method of claim 3, wherein the step of forming the lead frame further comprises: the second resist layer in the ninth step uses nickel or tin.
8. The method of claim 3, wherein the step of forming the lead frame further comprises: and step eleven, adopting nickel gold, nickel palladium gold or tin as the metal oxidation resistant layer.
9. The method of claim 3, wherein the step of forming the lead frame further comprises: and repeating the steps two to four times to manufacture a multilayer pattern.
CN201911122929.0A 2019-11-16 2019-11-16 Semi-etched lead frame structure and manufacturing method thereof Pending CN110896064A (en)

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Application Number Priority Date Filing Date Title
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Publication Number Publication Date
CN110896064A true CN110896064A (en) 2020-03-20

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Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5481798A (en) * 1994-01-19 1996-01-09 Sony Corporation Etching method for forming a lead frame
KR19980045141A (en) * 1996-12-09 1998-09-15 김광호 Multi-layer wiring process of semiconductor device
US6077727A (en) * 1996-01-31 2000-06-20 Sony Corporation Method for manufacturing lead frame
CN102265394A (en) * 2008-12-24 2011-11-30 Lg伊诺特有限公司 Structure for multi-row leadframe and semiconductor package thereof and manufacture method thereof
CN102376672A (en) * 2011-11-30 2012-03-14 江苏长电科技股份有限公司 Foundation island-free ball grid array packaging structure and manufacturing method thereof
CN103400773A (en) * 2013-08-06 2013-11-20 江苏长电科技股份有限公司 Packaging-prior-to-etching passive device type three-dimensional system-level metal circuit board structure and process method thereof
CN104168726A (en) * 2013-05-17 2014-11-26 深南电路有限公司 Coreless substrate processing method
CN106876360A (en) * 2017-03-06 2017-06-20 江阴芯智联电子科技有限公司 The pre-packaged wettable lead frame structure in many sides and its manufacture method
CN108493118A (en) * 2018-05-11 2018-09-04 江苏长电科技股份有限公司 Lead frame process method with side tin-climbing pin
CN209133501U (en) * 2018-12-21 2019-07-19 江阴芯智联电子科技有限公司 Subtractive process pre-packaged lead frame structure
CN210837734U (en) * 2019-11-16 2020-06-23 江苏长电科技股份有限公司 Semi-etched lead frame structure

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5481798A (en) * 1994-01-19 1996-01-09 Sony Corporation Etching method for forming a lead frame
US6077727A (en) * 1996-01-31 2000-06-20 Sony Corporation Method for manufacturing lead frame
KR19980045141A (en) * 1996-12-09 1998-09-15 김광호 Multi-layer wiring process of semiconductor device
CN102265394A (en) * 2008-12-24 2011-11-30 Lg伊诺特有限公司 Structure for multi-row leadframe and semiconductor package thereof and manufacture method thereof
CN102376672A (en) * 2011-11-30 2012-03-14 江苏长电科技股份有限公司 Foundation island-free ball grid array packaging structure and manufacturing method thereof
CN104168726A (en) * 2013-05-17 2014-11-26 深南电路有限公司 Coreless substrate processing method
CN103400773A (en) * 2013-08-06 2013-11-20 江苏长电科技股份有限公司 Packaging-prior-to-etching passive device type three-dimensional system-level metal circuit board structure and process method thereof
CN106876360A (en) * 2017-03-06 2017-06-20 江阴芯智联电子科技有限公司 The pre-packaged wettable lead frame structure in many sides and its manufacture method
CN108493118A (en) * 2018-05-11 2018-09-04 江苏长电科技股份有限公司 Lead frame process method with side tin-climbing pin
CN209133501U (en) * 2018-12-21 2019-07-19 江阴芯智联电子科技有限公司 Subtractive process pre-packaged lead frame structure
CN210837734U (en) * 2019-11-16 2020-06-23 江苏长电科技股份有限公司 Semi-etched lead frame structure

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