CN110890331A - 半导体装置封装及其制造方法 - Google Patents

半导体装置封装及其制造方法 Download PDF

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Publication number
CN110890331A
CN110890331A CN201910837821.3A CN201910837821A CN110890331A CN 110890331 A CN110890331 A CN 110890331A CN 201910837821 A CN201910837821 A CN 201910837821A CN 110890331 A CN110890331 A CN 110890331A
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layer
semiconductor device
package body
antenna
circuit layer
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CN201910837821.3A
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Inventor
谢盛祺
王陈肇
李德章
陈建桦
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication of CN110890331A publication Critical patent/CN110890331A/zh
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Abstract

一种半导体装置封装包含玻璃载体、封装主体、第一电路层和第一天线层。所述玻璃载体具有第一表面和与所述第一表面相对的第二表面。所述封装主体安置于所述玻璃载体的所述第一表面上。所述封装主体具有穿透所述封装主体的互连结构。所述第一电路层安置于所述封装主体上。所述第一电路层具有电连接到所述封装主体的所述互连结构的再分布层RDL。所述第一天线层安置于所述玻璃载体的所述第二表面上。

Description

半导体装置封装及其制造方法
技术领域
本公开涉及一种半导体装置封装及其制造方法，且更具体地说，涉及一种包含天线的半导体装置封装及其制造方法。
背景技术
例如手机等无线通信装置通常包含用于发射和接收射频(RF)信号的天线。类似地，无线通信装置包含各自安置在电路板的不同部分上的天线及通信模块。根据类似的方法，单独地制造天线及通信模块，并在将天线及通信模块放置在电路板上之后将其电连接到一起。因此，所述两组件可能带来单独的制造成本。此外，可能难以减少无线通信装置的大小以达成合适紧凑型产品设计。为减小成本和封装大小，提供封装中天线(Antenna-in-Package，AiP)方法。一般来说，在AiP系统中普遍使用有机衬底。然而，归因于有机衬底的工艺限制，难以达成细间距(小于15/15μm)，且有机衬底的厚度是相对厚的，这将阻碍AiP系统的小型化。
发明内容
根据本公开的一些实施例，一种半导体装置封装包含玻璃载体、封装主体、第一电路层和第一天线层。玻璃载体具有第一表面和与所述第一表面相对的第二表面。封装主体安置于玻璃载体的第一表面上。封装主体具有穿透封装主体的互连结构。第一电路层安置于封装主体上。第一电路层具有电连接到封装主体的互连结构的再分布层(RDL)。第一天线层安置于玻璃载体的第二表面上。
根据本公开的一些实施例，一种半导体装置封装包含玻璃载体、第一电路层、第一封装主体和第一天线层。玻璃载体具有第一表面和与所述第一表面相对的第二表面。第一电路层安置于玻璃载体的第一表面上。第一电路层具有再分布层(RDL)。第一封装主体安置于第一电路层上。第一封装主体具有穿透第一封装主体的互连结构且电连接到所述RDL。第一天线层安置于玻璃载体的第二表面上。
根据本公开的一些实施例，一种制造半导体装置封装的方法包含：(a)提供具有第一表面和与第一表面相对的第二表面的玻璃载体；(b)在玻璃载体的第一表面上形成具有再分布层(RDL)的电路层；(c)在所述电路层上安置电子组件且将其电连接到电路层的RDL；以及(d)在电路层上形成第一封装主体并覆盖电子组件，所述第一封装主体具有穿透第一封装主体的互连结构且连接到电路层的RDL；以及(e)在玻璃载体的第二表面上形成第一天线层。
附图说明
图1A示出根据本公开的一些实施例的半导体装置封装的横截面图。
图1B示出根据本公开的一些实施例的天线的示意图。
图1C示出根据本公开的一些实施例的天线的示意图。
图1D示出根据本公开的一些实施例的天线阵列的示意图。
图1E示出根据本公开的一些实施例的通信系统的示意图。
图1F示出根据本公开的一些实施例的天线阵列的示意图。
图2示出根据本公开的一些实施例的半导体装置封装的横截面图。
图3A、图3B、图3C、图3D、图3E、图3F、图3G、图3H和图3I示出根据本公开的一些实施例的半导体制造方法。
图4示出根据本公开的一些实施例的半导体装置封装的横截面图。
图5示出根据本公开的一些实施例的半导体装置封装的横截面图。
图6A示出根据本公开的一些实施例的半导体装置封装的横截面图。
图6B示出根据本公开的一些实施例如图6A所示由点线环绕的结构的放大视图。
图6C示出根据本公开的一些实施例如图6A所示的半导体装置封装的联接结构。
图6D展示根据本公开的一些实施例的不同半导体装置封装的频率响应。
图7A示出根据本公开的一些实施例的半导体装置封装的横截面图。
图7B示出根据本公开的一些实施例如图7A所示的半导体装置封装的互连层的俯视图。
图7C示出根据本公开的一些实施例如图7A所示的天线的放大视图。
图7D示出根据本公开的一些实施例如图7A所示的天线的透视图。
图8示出根据本公开的一些实施例的半导体装置封装的横截面图。
图9示出根据本公开的一些实施例的半导体装置封装的横截面图。
图10示出根据本公开的一些实施例的半导体装置封装的横截面图。
图11示出根据本公开的一些实施例的半导体装置封装的横截面图。
图12A、图12B、图12C、图12D和图12E示出根据本公开的一些实施例的半导体制造方法。
图13A、图13B、图13C、图13D和图13E示出根据本公开的一些实施例的半导体制造方法。
图14A、图14B、图14C和图14D示出根据本公开的一些实施例的半导体制造方法。
图15A、图15B、图15C、图15D、图15E和图15F示出根据本公开的一些实施例的半导体制造方法。
贯穿图式和详细描述使用共同参考标号来指示相同或类似组件。根据以下结合附图作出的详细描述将容易理解本公开。
具体实施方式
随着技术进步，归因于电子组件的尺寸缩小，各种电子组件可集成到封装中。举例来说，在聚集在2.4GHz附近的频带内使用或操作的天线具有是在聚集在28GHz附近的频带内使用或操作的另一天线的尺寸的12.5倍的尺寸。举例来说，在聚集在2.4GHz附近的频带内使用或操作的天线具有是在聚集在60GHz附近的频带内使用或操作的另一天线的尺寸的25倍的尺寸。
包含天线或天线结构的半导体装置封装还可被称作封装中天线(AiP)或封装上天线(AoP)。举例来说，如图1A所示，其示出鉴于本公开的一些实施例的半导体装置封装1的横截面图，半导体装置封装1是AiP/AoP的实例。半导体装置封装1包含载体10、电子组件11和天线12(或包含天线12的天线阵列)。
电子组件11可包含例如(但不限于)射频(RF)集成电路(IC)。当在聚集在约5GHz以下的频带内操作半导体装置封装1时，电子组件11和天线12之间的距离不会影响半导体装置封装1的性能。然而，发射路径中的损耗(或路径损耗)可能随着半导体装置封装1的工作频率(或操作频率)升高而变得严重。举例来说，相对高频带(例如，其中发射毫米波的毫米带(具有30吉兆赫(GHz)和300GHz之间的频谱))中的路径损耗是相对低频带(例如，聚集在2.4GHz附近的频率)中的损耗的10倍。相应地，天线12和电子组件11应安置成尽可能接近以缓解损耗。
图1B示出根据本公开的一些实施例的天线12的示意图。箭头中的每一个表示信号发射方向。天线12还可被称作全向天线。天线12能够在水平面中在任何方向上同等地发射和接收无线电信号。由点线环绕的区域表示信号覆盖度。天线12可具有约1dB到2dB的增益。
图1C是示出根据本公开的其它实施例的天线12的实例的示意图。天线12还可被称作定向天线。天线12可包含毫米波天线。由点线环绕的区域表示信号覆盖度。天线12可具有约7dB到8dB的增益。天线12可具有是前述全向天线的增益的近似4倍的增益。
图1D是示出根据本公开的一些实施例包含天线12的天线阵列的实例的示意图。天线阵列s可包含毫米波天线。天线阵列可包含全向天线。天线阵列可包含定向天线。天线阵列可包含全向天线和定向天线。由点线环绕的区域表示信号覆盖度。天线阵列可具有约13dB到14dB的增益。天线阵列可具有是前述全向天线的增益的近似16倍的增益。
图1E是示出通信系统的实例的示意图。通信系统包含天线阵列，目标A、目标B和目标C。通信系统可包含波束成形系统。
在图1E中示出的天线阵列可包含毫米波天线。在图1E中示出的天线阵列可包含天线相位阵列。在图1E中示出的天线阵列可包含全向天线。在图1E中示出的天线阵列可包含定向天线。在图1E中示出的天线阵列可包含全向天线和定向天线。在图1E中示出的天线阵列可包含用于波束成形的切换波束天线。
图1F是示出天线阵列的实例的示意图。天线阵列可包含相位阵列。信号借助于天线阵列和虚线框中的电路被发射或接收。虚线框中的电路可包含例如(但不限于)相移电路。
图2示出根据本公开的一些实施例的半导体装置封装2。半导体装置封装2包含半导体装置118A和118B、保护层108和124、电介质层110和126、钝化层102、天线单元104、SMT装置132、导电元件106、112、114、120和128，以及连接元件130。
图3A、图3B、图3C、图3D、图3E、图3F、图3G、图3H和图3I展示根据本公开的一些实施例制造半导体装置封装的操作。
参看图3A，钝化层102形成于支撑载体100上方。天线元件104形成于钝化层102上方。
参看图3B，导电元件106形成于天线元件104上方。
参看图3C，保护层108形成于图3B中展示的结构上方以环绕天线元件104和导电元件106。保护层108由模制化合物材料制成或包含模制化合物材料。模制化合物材料可包含具有分散在其中的填料的环氧基树脂。填料可包含绝缘纤维、绝缘粒子、其它合适的要素或其组合。举例来说，填料包含氧化硅、氮化硅、碳化硅、含碳聚合材料、其它合适的材料或其组合，或由它们制成。在一些实施例中，保护层108使用转移模制工艺、压缩工艺、浸没工艺、另一可适用的工艺或其组合形成。
在一些实施例中，使用平坦化工艺使保护层108变薄直至导电元件106暴露。平坦化工艺可包含碾磨工艺、化学机械抛光(CMP)工艺、蚀刻工艺、另一可适用的工艺或其组合。在一些其它实施例中，不执行平坦化工艺。举例来说，使用转移模制工艺形成保护层108。通过使用转移模制工艺，在保护层108的形成期间，导电特征106的顶部表面不会被保护层108覆盖。因此，可以不必执行平坦化工艺来暴露导电元件106。
参看图3D，电介质层110沉积在保护层108和导电元件106上方。然后，包含导电元件112a、112b和112c的导电元件形成于电介质层110上方。不透明的保护层108可导致未对准问题。举例来说，导电元件112a、112b和112c以及天线元件104可能未对准。
参看图3E，导电元件114形成于导电元件112上方，且半导体裸片118A和118B放置在导电元件112a、112b和/或112c以及电介质层110上方。粘合剂膜116用于将半导体裸片118A和118B附连在导电元件112a、112b和/或112c上。
参看图3F，保护层124形成于图3E中展示的结构上方。保护层124环绕导电元件114以及半导体裸片118A和118B。在一些实施例中，保护层124由模制化合物材料制成或包含模制化合物材料。模制化合物材料可包含具有分散在其中的填料的环氧基树脂。在一些实施例中，保护层124使用转移模制工艺、压缩工艺、浸没工艺、另一可适用的工艺或其组合形成。保护层124包含具有大于3的介电常数(Dk)的材料。保护层124包含具有大于0.01的损耗角正切或耗散因子(Df)的材料。损耗角正切或Df可随着工作频率增长得相对高而变糟。
在一些实施例中，使用平坦化工艺使保护层124变薄直至半导体裸片118A和118B的导电特征114和导电元件120暴露。平坦化工艺可包含碾磨工艺、CMP工艺、蚀刻工艺、另一可适用的工艺或其组合。在一些其它实施例中，不执行平坦化工艺。举例来说，使用转移模制工艺形成保护层124，其中半导体裸片118A和118B的导电元件114和导电元件120的顶部表面不被保护层124覆盖。
在不同阶段中形成保护层108和保护层124可花费相对长的时间，这可能不利地影响半导体装置封装的良品率。
相比于其它元件/组件(例如半导体裸片118A和118B、天线元件104、导电元件106、112、114等)具有相对大体积的保护层108和保护层124可能导致翘曲问题。
参看图3G，互连结构形成于图3F中展示的结构上方。互连结构包含多个电介质层126和多个导电元件128。
参看图3H，连接元件130形成于一些导电元件128上方。在一些实施例中，导电元件130包含焊料凸块。焊料凸块由锡和其它金属材料制成。在一些实施例中，导电元件130可包含例如铜柱等金属柱。然后，根据一些实施例，表面安装装置132放置在一些导电元件128上，如图3H所示。表面安装装置132可包含无源装置，例如电容器、电阻器和/或电感器。
参看图3I，图3H中展示的结构倒置且安置于带框134或载体134上。然后移除支撑载体100。在一些实施例中，执行切片操作以获得多个半导体封装。
然后，根据一些实施例，移除带框134或载体134，如图2所示，其中展示半导体装置封装中的一个。
图4示出根据本公开的一些实施例的半导体装置封装4的横截面图。半导体装置封装4包含载体40、电子组件41、封装主体42、电路层43、保护层44和电接触件45。
在一些实施例中，载体40可以是或包含玻璃衬底。载体40可包含导电衬垫、迹线和互连(例如，通孔)。在一些实施例中，载体40可包含透明材料。在一些实施例中，载体40可包含不透明材料。载体40包含具有小于近似3.5的Dk的材料。载体40包含具有小于近似3的Dk的材料。载体40包含具有小于近似0.005的损耗角正切或耗散因子(Df)的材料。载体40包含具有小于近似0.003的Df的材料。载体40具有表面401和与表面401相对的表面402。与有机衬底相比，更容易控制玻璃载体的厚度，这可促进半导体装置封装4的小型化。在一些实施例中，载体40的厚度为约400μm。
导电层40p安置于载体40的表面402上。在一些实施例中，导电层40p限定图案化天线，例如定向天线、全向天线、天线阵列。举例来说，导电层40p限定片状天线。导电层40p是例如金属或金属合金等导电材料，或包含例如金属或金属合金等导电材料。导电材料的实例包含金(Au)、银(Ag)、铜(Cu)、铂(Pt)、钯(Pd)、其它金属或合金，或其两个或两个以上的组合。
电子组件41安置于载体40的表面401上。电子组件41可以是有源电子组件，例如集成电路(IC)芯片或裸片。电子组件41具有通过粘合元件41h结合或附接到载体的表面401的背侧表面。粘合元件41h包含凝胶、裸片附接膜(DAF)等。
一或多个互连结构42p(例如，导电柱或导电元件)安置于载体40的表面401上。互连结构42p是或包含例如金属或金属合金等导电材料。导电材料的实例包含Au、Ag、Cu、Pt、Pd或其合金。
封装主体42安置于载体40的表面401上。封装主体42覆盖电子组件41且暴露电子组件41的有源表面。举例来说，封装主体的表面421与电子组件41的有源表面大体上共面。封装主体42覆盖互连结构42p的一部分且暴露互连结构42p的另一部分(例如，顶部部分)以用于电连接。在一些实施例中，封装主体42包含包含填料的环氧树脂、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚化合物或材料、包含分散在其中的硅酮的材料，或其组合。
电路层43安置于封装主体42的表面421上。电路层43包含一或多个互连层(例如，再分布层，RDL)43r和一或多个电介质层43d。互连层43r的一部分由电介质层43d覆盖或囊封，而互连层43r的另一部分从电介质层43d暴露以提供电连接。互连层43r的暴露部分电连接到互连结构42p和电子组件41的有源表面。
在一些实施例中，电介质层43d可包含预浸复合纤维(例如，预浸体)、硼磷硅玻璃(BPSG)、氧化硅、氮化硅、氮氧化硅、未掺杂的硅玻璃(USG)、其中两者或两者以上的任何组合，等等。预浸体的实例可包含(但不限于)通过堆叠或层压若干预浸材料/片材而形成的多层结构。在一些实施例中，取决于设计规范可存在任何数目的互连层43r。在一些实施例中，互连层43r由Au、Ag、Cu、Pt、Pd或其合金形成或包含Au、Ag、Cu、Pt、Pd或其合金。
保护层44安置于电路层43上以覆盖从电介质层43d暴露的互连层43r的一部分，且暴露从电介质层43d暴露的互连层43r的另一部分以用于电连接。在一些实施例中，保护层44可为或包含焊料掩模或其它合适的材料。
电接触件45安置于从保护层44暴露的互连层43r上。在一些实施例中，电接触件45可包含焊料或其它合适的材料。
图5示出根据本公开的一些实施例的半导体装置封装5的横截面图。半导体装置封装5类似于图4中的半导体装置封装4，且下文描述其间的差异。
封装主体42具有或限定腔42c以暴露载体40的表面401。导电元件52具有安置于腔42c的侧壁上的第一部分52a，和安置于从封装主体42暴露的载体40的表面401上的第二部分52b。电子组件41安置于腔42c内以及导电元件52的部分52b上。电子组件41与导电元件52的部分52a隔开。举例来说，导电元件52的部分52a和电子组件41之间存在间隙。在一些实施例中，电介质层43d安置于导电元件52的部分52a和电子组件41之间的间隙内。在一些实施例中，导电元件52可充当电磁干扰(EMI)屏蔽件以保护电子组件41使其免受EMI影响。导电元件52由Au、Ag、Cu、Pt、Pd或其合金形成或包含Au、Ag、Cu、Pt、Pd或其合金。
图6A示出根据本公开的一些实施例的半导体装置封装6的横截面图。半导体装置封装6类似于图4中的半导体装置封装4，且下文描述其间的差异。
电路层43安置于载体40的表面401上。在一些实施例中，直接安置于载体40的表面401上的电路层43的互连层43r的一部分可限定天线。电子组件41安置于电路层43上且电连接到从电介质层43d暴露的互连层43r。互连结构42p安置于电路层43上，且电连接到从电介质层43d暴露的互连层43r。
封装主体42安置于电路层43上。封装主体42具有或限定腔42c以容纳电子组件41。在一些实施例中，电子组件41与腔42c的侧壁隔开。举例来说，腔42c的侧壁和电子组件41之间存在间隙。在一些实施例中，电介质层43d安置于腔42c的侧壁和电子组件41之间的间隙内。封装主体42覆盖互连结构42p的一部分且暴露互连结构42p的另一部分以用于电连接。导电层42cp安置于封装主体42上。导电层42cp的一部分电连接到互连结构42p的暴露部分。
图6B是如图6A所示的由点线环绕的结构的放大视图。使天线元件(例如，导电层40p)与互连层43r(其可包含对应天线场型)间隔或分隔的载体40可促进信号耦合。举例来说，在载体40使天线元件(例如，导电层40p)与互连层43r(其可包含对应天线场型)间隔或分隔近似200μm到近似400μm的范围内的距离D61的一个条件中，半导体装置封装6的工作频率可由近似3GHz到近似6GHz范围内的带宽扩展。半导体装置封装6的工作频率的带宽的增益或增加可通过改变载体40的材料(例如，利用相对低Dk材料)或改变联接距离来实现。
图6C示出如图6A所示的半导体装置封装6的联接结构。所述联接结构包含三层天线或辐射器60。联接结构可包含更多或更层的天线。联接结构可帮助扩展半导体装置封装6的工作频率的带宽。
图6D展示根据本公开的一些实施例的不同半导体装置封装的频率响应。
参看图6D，曲线G2b表示如图6A所示的半导体装置封装6的频率响应。曲线G2b'表示类似于如图6A所示的半导体装置封装6的另一半导体装置封装(未图示)的频率响应，只是消除了导电层40p和载体40。具有联接设计的半导体装置封装6具有相对广/宽的工作频率带宽。
图7A示出根据本公开的一些实施例的半导体装置封装7的横截面图。半导体装置封装7类似于图4中的半导体装置封装4，且下文描述其间的差异。
半导体装置封装7包含安置于载体40的表面401上且邻近于载体40的横向表面403的天线73。在一些实施例中，天线73是或包含偶极天线。在一些实施例中，偶极天线可包含二维(2D)偶极天线或三维(3D)偶极天线。在一些实施例中，天线73电连接到互连层43r。
图7B示出如图7A中所示的半导体装置封装7的电路层43的互连层43r的俯视图。参看图7B，互连层43r可包含由天线73(例如，偶极天线阵列)环绕的片状天线。
图7C示出根据本公开的一些实施例如图7A所示的天线73的放大视图。参看图7C，天线73可包含2D偶极天线。天线73可包含图案化导电迹线。
图7D示出根据本公开的其它实施例如图7A中所示的天线73的透视图。参看图7D，天线73可包含3D偶极天线。天线73可包含弯曲导电件或板。天线73可包含“L”形或“类似于L”形的导电件或板。
图8示出根据本公开的一些实施例的半导体装置封装8的横截面图。半导体装置封装8类似于图6A中的半导体装置封装6，且下文描述其间的差异。
半导体装置封装8包含安置于载体40的表面402上且邻近于电路层40的横向表面403的天线83。在一些实施例中，天线83通过导电元件40v电连接到互连层43r。在一些实施例中，天线83电连接到导电层40p。在一些实施例中，天线83是或包含偶极天线。在一些实施例中，偶极天线可包含2D偶极天线或3D偶极天线。在一些实施例中，天线83具有与如图7A、7B、7C和7D中所展示的天线73相同或类似的结构。
图9示出根据本公开的一些实施例的半导体装置封装9的横截面图。半导体装置封装9类似于图6A中的半导体装置封装6，且下文描述其间的差异。
半导体装置封装9进一步包含导电元件91a和91b。导电元件91a安置于电路层43上且邻近于电子组件41。导电元件91a的一部分由封装主体42囊封，而导电元件91a的另一部分从封装主体42暴露。在一些实施例中，导电元件91a环绕电子组件41。导电元件91b安置于封装主体42上且电连接到导电元件91a。导电元件91a和91b可限定EMI屏蔽件以保护电子组件41使其免受EMI影响。
图10示出根据本公开的一些实施例的半导体装置封装10的横截面图。半导体装置封装10类似于图6A中的半导体装置封装6，且下文描述其间的差异。
参看图10，省略封装主体42。保护层44安置于电路层43上。保护层44覆盖从电介质层43d暴露的互连层43r的一部分，且暴露从电介质层43d暴露的互连层43r的另一部分。底部填充物41u安置于电子组件41的有源表面和保护层44之间。在一些实施例中，底部填充物41u可包含具有相比于封装主体42的尺寸相对小的尺寸的填料。在一些实施例中，底部填充物41u可不具有填料。在其它实施例中，底部填充物41u可省略。电接触件45安置于电路层43的互连层43r的暴露部分上。
图11示出根据本公开的一些实施例的半导体装置封装110的横截面图。半导体装置封装110类似于图10中的半导体装置封装10，只是半导体装置封装110进一步包含安置于电路层43和载体40之间的封装主体42。一或多个互连结构42p穿透封装主体42以电连接到电路层43的互连层43r。
图12A、图12B、图12C、图12D和图12E示出根据本公开的一些实施例的半导体制造方法。在一些实施例中，图12A、图12B、图12C、图12D和图12E中的方法可用于制造图5中的半导体装置封装5。
参看图12A，提供载体40。封装主体42形成于载体40上。封装主体42包含模制化合物材料。模制化合物材料可包含具有分散在其中的填料的环氧基树脂。封装主体由例如转移模制技术、压缩技术、浸没技术、激光钻孔技术、光刻技术、另一可适用的技术或其组合形成。一或多个开口42h和腔42c形成为穿透封装主体42以暴露载体40。图案化导电层42p'随开口42h和腔42c一起形成。
参看图12B，互连结构42p如图12A所示通过例如(但不限于)电镀技术而形成于图案化导电层42p'上。互连结构42p可包含导电元件52a和52b。电子组件41通过粘合元件41h附接到导电元件52b。
参看图12C，可包含电介质层43d和互连层43r的电路层43(例如，RDL结构)形成于封装主体42上。互连层43r电连接到互连结构42p和电子组件41的导电端。电介质层43d通过例如(但不限于)光刻技术形成。互连层43r通过例如(但不限于)电镀技术形成。
参看图12D，更多RDL结构可形成于如图12C所示的RDL结构上。在一些实施例中，取决于不同设计规范，存在任何数目的RDL结构。
参看图12E，通过例如(但不限于)研磨技术从下侧或底侧移除如图12D所示的载体40的一部分。导电层40p(例如，图案化天线)形成于薄化或经研磨载体40上。在一些实施例中，载体40可包含玻璃，这可促进导电层40p和互连层43r之间的对准。在一些实施例中，载体40可包含玻璃，这可缓解在各种制造阶段可能发生的翘曲问题。
在一些实施例中，保护层44和电接触件45形成于从电介质层43d暴露的互连层43r上以形成如图5所示的半导体装置封装5。
图13A、图13B、图13C、图13D和图13E示出根据本公开的一些实施例的半导体制造方法。在一些实施例中，图13A、图13B、图13C、图13D和图13E中的方法可用于制造图9中的半导体装置封装9。
参看图13A，提供载体40。可包含电介质层43d和互连层43r的电路层43(例如，RDL结构)形成于载体40上。电介质层43d通过例如(但不限于)光刻技术形成。互连层43r通过例如(但不限于)电镀技术形成。
参看图13B，互连结构42p和导电元件91a形成于电路层43上以电连接到从电介质层43d暴露的互连层43r。在一些实施例中，互连结构42p和导电元件91a通过例如(但不限于)电镀技术形成。
参看图13C，电子组件41附接或结合到从电介质层43d暴露的互连层43r。封装主体42形成为囊封互连结构42p、导电元件91a和电子组件41。封装主体42可包含模制化合物材料。
参看图13D，移除封装主体42的部分以暴露互连结构42p和导电元件91a。图案化导电层42cp(包含导电元件91b)形成于封装主体42上。导电层42cp电连接到互连结构42p，且导电元件91b电连接到导电元件91a。
参看图13E，通过例如(但不限于)研磨技术从下侧或底侧移除如图13D所示的载体40的一部分。导电层40p(例如，图案化天线)形成于薄化或经研磨载体40上。在一些实施例中，载体40可包含玻璃，这可促进导电层40p和互连层43r之间的对准。在一些实施例中，载体40可包含玻璃，这可缓解在各种制造阶段可能发生的翘曲问题。
在一些实施例中，在封装主体42上形成保护层44和电接触件45以形成如图9中所示的半导体装置封装9。
图14A、图14B、图14C和图14D示出根据本公开的一些实施例的半导体制造方法。在一些实施例中，图14A、图14B、图14C和图14D中的方法可用于制造图10中的半导体装置封装10。
参看图14A，提供载体40。可包含电介质层43d和互连层43r的电路层43(例如，RDL结构)形成于载体40上。电介质层43d通过例如(但不限于)光刻技术形成。互连层43r通过例如(但不限于)电镀技术形成。保护层44形成于电路层43上以暴露互连层43r的一部分。
参看图14B，电接触件45形成于保护层44上且电连接到从保护层44暴露的互连层43r。
参看图14C，电子组件41附接或结合到从保护层44暴露的互连层43r。底部填充物41u形成于电子组件41和电路层43之间。
参看图14D，如图14C所示的结构结合到载体30(例如带框)或安置到其上。如图14D所示，电子组件41的至少一部分、底部填充物41u和电接触件45在载体30内或被载体30覆盖。导电层40p(例如，天线场型)形成于载体40的背对电路层43的表面上。
在一些实施例中，移除载体30以形成如图11中所示的半导体装置封装10。
图15A、图15B、图15C、图15D、图15E和图15F示出根据本公开的一些实施例的半导体制造方法。
参看图15A，提供载体40。导电元件40v形成于载体40中。在一些实施例中，导电元件40v在载体40内延伸而不穿透载体40。
参看图15B，可包含电介质层43d和互连层43r的电路层43(例如，RDL结构)形成于载体40上。互连层43r电连接到导电元件40v。电介质层43d通过例如(但不限于)光刻技术形成。互连层43r通过例如(但不限于)电镀技术形成。
参看图15C，保护层44形成于电路层43上以暴露互连层43r的一部分。通过例如(但不限于)研磨技术从下侧或底侧移除如图15B所示的载体40的一部分。移除如图15B所示的载体40的一部分以暴露导电元件40v。导电层40p(例如，图案化天线)形成于薄化或经研磨载体40上。在一些实施例中，载体40可包含玻璃，这可促进导电层40p和互连层43r之间的对准。在一些实施例中，载体40可包含玻璃，这可缓解在各种制造阶段可能发生的翘曲问题。
参看图15D，封装主体62形成于载体40上以囊封或覆盖导电层40p。封装主体42可包含模制化合物材料。
参看图15E，在封装主体62的背对载体40的表面上形成导电层62p。在一些实施例中，导电层62p可限定例如片状天线等天线。在一些实施例中，导电层62p可联接到导电层40p以用于其间的信号发射。
参看图15F，电接触件45形成于保护层44上且电连接到互连层43r。电子组件41附接或结合到互连层43r。底部填充物41u接着形成于电子组件41和电路层43之间以形成半导体装置封装。
如本文中所使用，术语“大体上”、“实质”、“近似”和“约”用于指示和解释小的变化。举例来说，当结合数值使用时，术语可指小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或者小于或等于±0.05％。作为另一实例，膜或层的厚度“大体上均匀”可指膜或层的平均厚度的小于或等于±10％的标准偏差，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或者小于或等于±0.05％。术语“大体上共面”可以指沿同一平面定位的在数微米内的两个表面，例如，沿同一平面定位的在40μm内、30μm内、20μm内、10μm内或1μm内。如果两个表面或组件之间的角为例如90°±10°，例如，±5°、±4°、±3°、±2°、±1°、±0.5°、±0.1°或±0.05°，那么两个表面或组件可被认为“大体上垂直”。当结合事件或情况使用时，术语“大体上”、“实质”、“近似”和“约”可指其中事件或情况精确出现的例子，以及其中事件或情况非常近似出现的例子。
如本文所用，除非上下文另外明确规定，否则单数术语“一(a/an)”和“所述”可包含复数指示物。在一些实施例的描述中，提供于另一组件“上”或“上方”的组件可涵盖前一组件直接在后一组件上(例如，与后一组件物理接触)的情况，以及一或多个中间组件位于前一组件和后一组件之间的情况。
如本文所使用，术语“导电(conductive)”、“导电(electrically conductive)”和“电导率”指代运送电流的能力。导电材料通常指对电流流动呈现极少或零对抗的那些材料。电导率的一个量度是西门子(Siemens)/米(S/m)。通常，导电材料是电导率大于近似104S/m(例如至少105S/m或至少106S/m)的一种材料。材料的电导率有时可随温度变化。除非另外规定，否则在室温下测量材料的电导率。
另外，有时在本文中按范围格式呈现量、比率和其它数值。应理解，此类范围格式是出于便利和简洁目的而使用，且应灵活地理解，不仅包含明确地指定为范围极限的数值，而且包含涵盖于所述范围内的所有个别数值或子范围，如同明确地指定每一数值和子范围一般。
尽管已参考本公开的特定实施例描述并说明本公开，但这些描述和说明并不限制本公开。所属领域的技术人员可清楚地理解，可进行各种改变，且可在实施例内替代等效元件而不脱离如由所附权利要求书限定的本公开的真实精神和范围。图示可能未必按比例绘制。归因于制造过程中的变量等等，本公开中的艺术再现与实际设备之间可能存在区别。可存在未特定说明的本公开的其它实施例。应将说明书和图式视为说明性的，而非限制性的。可作出修改，以使特定情况、材料、物质组成、方法或过程适应于本公开的目标、精神以及范围。所有此些修改都打算属于在此所附权利要求书的范围内。虽然已参考按特定次序执行的特定操作描述本文中所公开的方法，但应理解，可在不脱离本公开的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序和分组并不限制本公开。
附图翻译
图1E
Target A|目标A
Target B 目标B
Target C 目标C
Antenna array 天线阵列
图6D
Coupling Design 联接设计
-Single patch design 单个贴片设计
Gain 增益
HFSSDesign1 HFSS设计1
Freq 频率

Claims (20)

1.一种半导体装置封装，其包括：
玻璃载体，其具有第一表面和与所述第一表面相对的第二表面；
封装主体，其安置于所述玻璃载体的所述第一表面上，所述封装主体具有穿透所述封装主体的互连结构；
第一电路层，其安置于所述封装主体上，所述第一电路层具有电连接到所述封装主体的所述互连结构的再分布层(RDL)；以及
第一天线层，其安置于所述玻璃载体的所述第二表面上。
2.根据权利要求1所述的半导体装置封装，其进一步包括安置于所述玻璃载体的所述第一表面上的电子组件，其中所述电子组件具有面向所述第一电路层并且电连接到所述第一电路层的所述RDL的有源表面。
3.根据权利要求2所述的半导体装置封装，其中所述电子组件被所述封装主体囊封。
4.根据权利要求2所述的半导体装置封装，其中所述封装主体具有穿透所述封装主体以暴露所述玻璃衬底的所述第一表面的一部分的腔，且所述电子组件安置于所述腔内。
5.根据权利要求4所述的半导体装置封装，其进一步包括所述腔内的导电层，其中所述导电层具有安置于所述腔的侧壁上的第一部分，和安置于所述玻璃衬底的所述第一表面的从所述封装主体暴露的所述部分上的第二部分。
6.根据权利要求5所述的半导体装置封装，其中所述电子组件安置于所述导电层的所述第二部分上并且与所述导电层的所述第一部分间隔开。
7.根据权利要求1所述的半导体装置封装，其中所述第一电路层的所述RDL和所述封装主体的所述互连结构限定偶极天线。
8.根据权利要求1所述的半导体装置封装，其进一步包括：
第二电路层，其安置于所述封装主体和所述玻璃载体之间，其中所述第二电路层具有电连接到所述封装主体的所述互连结构的RDL；以及
电子组件，其安置于所述第二电路层上。
9.根据权利要求8所述的半导体装置封装，其进一步包括穿透所述玻璃载体并且将所述第二电路层的所述RDL电连接到所述第一天线层的穿通孔。
10.根据权利要求8所述的半导体装置封装，其中所述封装主体具有容纳所述电子组件的腔。
11.根据权利要求10所述的半导体装置封装，其进一步包括具有第一部分和第二部分的屏蔽件，其中所述屏蔽件的所述第一部分安置于所述第二电路层上并且环绕所述电子组件，且所述屏蔽件的所述第二部分安置于所述电子组件上方并且电连接到所述屏蔽件的所述第一部分。
12.一种半导体装置封装，其包括：
玻璃载体，其具有第一表面和与所述第一表面相对的第二表面；
第一电路层，其安置于所述玻璃载体的所述第一表面上，所述第一电路层具有再分布层RDL；
第一封装主体，其安置于所述第一电路层上，所述第一封装主体具有穿透所述第一封装主体并且电连接到所述RDL的互连结构；以及
第一天线层，其安置于所述玻璃载体的所述第二表面上。
13.根据权利要求12所述的半导体装置封装，其进一步包括安置于所述第一电路层上的电子组件，其中所述电子组件具有朝向所述第一电路层且电连接到所述第一电路层的有源表面。
14.根据权利要求13所述的半导体装置封装，其中所述电子组件由所述第一封装主体囊封。
15.根据权利要求12所述的半导体装置封装，其进一步包括安置于所述玻璃载体的所述第二表面上的第二封装主体。
16.根据权利要求15所述的半导体装置封装，其进一步包括安置于所述第二封装主体的背对所述玻璃载体的表面上的第二天线层。
17.一种制造半导体装置封装的方法，所述方法包括：
(a)提供具有第一表面和与所述第一表面相对的第二表面的玻璃载体；
(b)在所述玻璃载体的所述第一表面上形成具有再分布层RDL的电路层；
(c)将电子组件安置在所述电路层上且电连接到所述电路层的所述RDL；以及
(d)在所述电路层上形成第一封装主体且覆盖所述电子组件，所述第一封装主体具有穿透所述第一封装主体且连接到所述电路层的所述RDL的互连结构；以及
(e)在所述玻璃载体的所述第二表面上形成第一天线层。
18.根据权利要求17所述的方法，其中操作(d)进一步包括：
将一或多个导电柱安置于所述电路层上并且电连接到所述电路层的所述RDL；
在所述电路层上形成所述第一封装主体以囊封所述导电柱；以及
移除所述第一封装主体的一部分以暴露所述导电柱。
19.根据权利要求17所述的方法，其进一步包括在所述玻璃载体的所述第二表面上形成第二封装主体以覆盖所述第一天线层。
20.根据权利要求19所述的方法，其进一步包括在所述第二封装主体的背对所述玻璃载体的表面上形成第二天线层。
CN201910837821.3A 2018-09-07 2019-09-05 半导体装置封装及其制造方法 Pending CN110890331A (zh)

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US11776820B2 (en) * 2020-09-30 2023-10-03 Huawei Technologies Co., Ltd. Vertical interconnection structure and manufacturing method thereof, packaged chip, and chip packaging method
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