CN110888765B - Device and method for counting 0 and 1 flip bit numbers - Google Patents
Device and method for counting 0 and 1 flip bit numbers Download PDFInfo
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- CN110888765B CN110888765B CN201911100401.3A CN201911100401A CN110888765B CN 110888765 B CN110888765 B CN 110888765B CN 201911100401 A CN201911100401 A CN 201911100401A CN 110888765 B CN110888765 B CN 110888765B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2289—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by configuration test
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a device and a method for counting 0 and 1 turnover bit numbers, wherein the device comprises a configuration module, a command FIFO, a response FIFO, a data flow control module, an adder, a master interface 1 and a master interface 2, wherein the data flow control module comprises a command processing module and a data processing module, the configuration module is connected with a control bus and is used for receiving configuration information and starting signals written by an external CPU through the control bus, the command FIFO is connected between the configuration module and the command processing module and is used for receiving and storing the configuration information written by the configuration module and writing the configuration information into the command processing module. The invention adopts two master interfaces to fetch numbers simultaneously, does not need to additionally open up space to store intermediate data, and simplifies design. Meanwhile, the device supports a plurality of commands and a large number of operations, so that the efficiency of the whole system is greatly improved, and the test time is saved.
Description
Technical Field
The invention relates to a device and a method for counting 0 and 1 flip bit numbers, belonging to the technical field of storage component testing.
Background
In performing a characteristic test on a memory device (e.g., NAND FLASH), statistics are required of the number of 0/1 flip bits before writing to the device and after reading from the device. This statistical data plays an important role in subsequent device characterization and research, and requires extensive test statistics throughout the characterization process. The traditional method adopts software to carry out statistical processing, namely the lower computer transmits all data to the upper computer, and the upper computer software carries out data comparison, so that a large amount of time is used for data transmission, the efficiency of a test system is low, and the test time is prolonged.
Disclosure of Invention
The invention aims to provide a device and a method for counting the number of 0 and 1 turnover bits, which improve the data comparison speed and save time.
In order to solve the technical problems, the invention adopts the following technical scheme: the device for counting the number of 0 and 1 flip bits comprises a configuration module, a command FIFO, a response FIFO, a data flow control module, an adder, a master interface 1 and a master interface 2, wherein the data flow control module comprises a command processing module and a data processing module, the configuration module is connected with a control bus and is used for receiving configuration information and starting signals written by an external CPU through the control bus, the command FIFO is connected between the configuration module and the command processing module and is used for receiving and storing the configuration information written by the configuration module and writing the configuration information into the command processing module, the command processing module calculates storage addresses and data lengths of original data and read data according to the configuration information, then the calculated original data address and data length signal are sent to a master interface 1, the calculated read data address and data length signal are sent to a master interface 2, the master interface 1 and the master interface 2 grasp corresponding data from a memory through a data bus according to the received data address and data length respectively, the grasped data are returned to a data processing module, the data processing module compares the data returned by the master interface 1 and the master interface 2 bit by bit, the number of bits 0 is turned over to be bits 1 and the number of bits 1 is turned over to be bits 0, an adder accumulates the number of bits 0 to be bits 1 and the number of bits 1 to be bits 0, and the accumulated result is written into a response FIFO; the configuration information includes an original data address, a read data address, and a data length.
Further, the command FIFO stores configuration information for a plurality of commands.
Further, the master interface 1 and the master interface 2 capture data in parallel.
Further, the external CPU writes configuration information into the configuration module when the start signal of the configuration module is invalid, the start signal of the configuration module is set to be valid when the full signals of the command FIFO and the response FIFO are both invalid, and after the configuration information of the command is written into the command FIFO, the start signal is set to be invalid.
Further, the data processing module outputs an effective end signal after finishing the number of the inversion bits of all the data of the command, at this time, the accumulated result of the adder is the number of the inversion bits of all the data of the command, and the adder writes the accumulated result into the response FIFO and then clears 0.
The invention also discloses a method for counting the number of the 0 and 1 turnover bits, which comprises the following steps:
s01), the external CPU writes configuration information and a starting signal of a command into a configuration module, and the configuration module writes the configuration information into a command FIFO, wherein the configuration information refers to an original data address of the command, a read data address and a data length;
s02), the command processing module in the data flow control module receives configuration information transmitted by the command FIFO to obtain information required by current operation: the method comprises the steps that an original data address, a read data address and a data length are read, and as configuration information of a command is required to be split into a plurality of addresses and the data length to be sent to a master interface, a command processing module splits the configuration information into a plurality of pieces according to a bus protocol and calculates the initial address and the data length of each piece, then the calculated original data address and data length are sent to the master interface 1, the calculated read data address and data length are sent to the master interface 2, and the data lengths sent to the two master interfaces are kept consistent;
s03), the master interface 1 receives the data address and the data length sent by the command processing module, starts data capture and returns data to the data flow control module;
s04), the master interface 2 receives the data address and the data length sent by the command processing module, starts data capture and returns data to the data flow control module;
s05), the data processing module in the data flow control module starts to compare the number of bits 0 turned over to bits and the number of bits 1 turned over to be more than 0 bit from the first address of the returned data bit by bit, and outputs the number to the adder until the comparison of all data of the current comparison command is completed, and then outputs an effective ending signal;
s06), while the step S05 is executed, the adder adds the output result of the data flow control module and the last accumulation result in real time, and outputs the current accumulation result, and when the data flow control module outputs a valid end signal, the accumulation result of the current adder is the final result;
s07), after receiving the effective ending signal, the response FIFO stores the accumulated result of the current adder;
s08), after the adder detects the effective end signal, the accumulated result is cleared to 0, and the next calculation is waited to start.
Further, the action of writing configuration information to the configuration module by the external CPU is performed in a loop until the configuration information of all commands is written to the configuration module.
Further, step S03 is performed in parallel with step S04.
Further, inquiring whether a configured starting signal is valid or not through a control bus, and if not, writing configuration information and the starting signal into a configuration module by an external CPU; the configuration module starting signal is set to be effective when full signals of the command FIFO and the response FIFO are invalid, and the starting signal is set to be invalid after configuration information compared at this time is written into the command FIFO.
Further, the external CPU checks the response FIFO state through the configuration module, and if the response FIFO state is not empty, the response FIFO state indicates that a valid result exists currently and can be read.
The invention has the beneficial effects that: the device and the method can improve the data comparison speed and the system efficiency; the device adopts two master interfaces to fetch numbers simultaneously instead of one master interface, does not need to additionally open up space to store intermediate data, and simplifies design. Meanwhile, the device supports a plurality of commands and a large number of operations, so that the efficiency of the whole system is greatly improved, and the test time is saved.
Drawings
FIG. 1 is a block diagram of an apparatus according to the present invention;
in the figure: start represents a start signal, cmd_info represents configuration information, cmd_fifo represents a command FIFO, cmpletfifo represents a response FIFO, full represents a full signal, empty represents a null signal, and end push represents an active end signal.
Detailed Description
The invention will be further described with reference to the drawings and the specific examples.
Example 1
The embodiment discloses a device for counting the number of flipped bits of data 0 and 1, as shown in fig. 1, which comprises a configuration module, a command FIFO, a response FIFO, a data flow control module, an adder, a master interface 1 and a master interface 2, wherein the data flow control module comprises a command processing module and a data processing module.
The configuration module is connected with the control bus and is used for receiving configuration information and starting signals written by an external CPU through the control bus, the command FIFO is connected between the configuration module and the command processing module and is used for receiving and storing the configuration information written by the configuration module and writing the configuration information into the command processing module, the command processing module calculates storage addresses and data lengths of original data and read-out data according to the configuration information, then the calculated original data addresses and data length signals are sent to the master interface 1, the calculated read-out data addresses and data length signals are sent to the master interface 2, the master interface 1 and the master interface 2 respectively actively capture corresponding data from a memory through the data bus according to the received data addresses and data lengths, the captured data are returned to the data processing module, the data processing module compares the data returned by the master interface 1 and the master interface 2 one by one, the number of bits 0 is counted and the number of the bits 1 is inverted to the number of the bits 1, the adder counts the number of the bits 0 is inverted to the bits 1 and the number of the bits 1 is inverted to the number of the bits 0 is counted and the number of the bits 1 is inverted to the results are accumulated and written into the FIFO; the configuration information includes an original data address, a read data address, and a data length.
In this embodiment, the command FIFO may store configuration information of a plurality of commands, support a plurality of commands, and support a large number of operations.
The master interface 1 and the master interface 2 capture data in parallel, and do not interfere with each other.
In this embodiment, after receiving the start signal, the configuration module determines whether the current command FIFO and the response FIFO are both full (full signal), and if they are not full, the start signal is valid, the configuration information is written into the command FIFO, and the start signal in the configuration module is set to be invalid. When the CPU detects that the starting signal is invalid, the last command configuration is successful, configuration information is written into the last command configuration, otherwise, the CPU waits until the current command is correctly configured.
In this embodiment, the data processing module outputs the valid end signal after completing the number of inversion bits of all data of the command, and at this time, the accumulated result of the adder is the number of inversion bits of all data of the command, and the adder writes the accumulated result into the response FIFO and then clears 0.
Example 2
The embodiment discloses a method for counting the number of bits flipped by 0 and 1, which comprises the following steps:
1. a microcontroller such as an external CPU and the like inquires whether a starting signal of the configuration module is valid or not through a control bus; if not, writing the original data address, the data length and the read data address into the configuration module, and finally writing a starting signal into the configuration module to start a comparison operation. Step 1 may be performed in a loop until all commands are written to the configuration module.
2. And if the configuration module detects that the full signals of the command FIFO and the response FIFO are invalid, the configuration module is high in effective starting signal, and the configuration information is written into the command FIFO. While the enable signal is deactivated.
3. The command processing module in the data flow control module receives the configuration information transmitted by the command FIFO to obtain the information required by the current operation: the method comprises the steps that an original data address, a data length and a read data address are needed to be split into a plurality of addresses and the data length of one command, the configuration information of the command is sent to a master interface, the command processing module splits the configuration information into a plurality of addresses and the data length of each address according to a bus protocol, then the calculated original data address and data length are sent to the master interface 1, the calculated read data address and data length are sent to the master interface 2, and the data lengths sent to the two master interfaces are kept consistent.
4. The master interface 1 receives the data address and the data length sent by the data flow control module, starts data capture and returns data to the data flow control module.
5. And meanwhile, the master interface 2 receives the data address and the data length sent by the data flow control module, starts data capture and returns data to the data flow control module. The master interface 1 and the master interface 2 are completely parallel and do not interfere with each other.
6. If the master interface 1 and the master interface 2 both have data return, the data processing module in the data flow control module simultaneously takes out one data from the master interface 1 and the master interface 2, compares the data, calculates the number of the bit 0 flipped to the bit 1 and the number of the bit 1 flipped to the bit 0, and outputs the result. And repeating the step 6 until the data processing module completes the comparison of the data with the specified length in the current configuration information. And outputting a valid end signal.
7. And 6, adding the output result of the data flow control module and the last accumulated result in real time by the adder, and outputting the current accumulated result. When the data flow control module outputs a valid end signal, the accumulated result of the current adder is the final result.
8. After receiving the effective end signal, the response FIFO stores the accumulated result of the current adder.
9. After the adder detects the end signal, the accumulated result is cleared to 0. Waiting for the next calculation to begin. The next calculation starts when the start signal is high and valid, and the comparison operation is repeated until the calculation results of all commands are completed.
10. The CPU can check the state of the response FIFO through the configuration module, and if the response FIFO is not empty, the CPU indicates that a valid result exists currently and can be read.
Compared with the traditional method for detecting the number of 0 and 1 turnover bits, the method can improve the data comparison speed and the system efficiency. The device adopts two MASTER ports to fetch numbers at the same time, but not one MASTER port, so that extra space is not required to be opened up for storing intermediate data, and the design is simplified. Meanwhile, the device supports a plurality of commands and a large number of operations, so that the efficiency of the whole system is greatly improved, and the test time is saved.
The foregoing description is only of the basic principles and preferred embodiments of the present invention, and modifications and alternatives thereto will occur to those skilled in the art to which the present invention pertains, as defined by the appended claims.
Claims (5)
1. A method for counting the number of bits flipped by 0 and 1, characterized by: the method comprises the following steps:
s01), the external CPU writes the configuration information of the command and the starting signal into the configuration module, and the action of writing the configuration information into the configuration module by the external CPU is circularly executed until the configuration information of all commands is written into the configuration module, wherein the configuration information refers to the original data address of the command, the read data address and the data length;
s02), if the configuration module detects that the full signals of the command FIFO and the response FIFO are invalid, the high-efficiency starting signal is valid, the configuration information of the command is written into the command FIFO, and meanwhile the starting signal is set to be invalid;
s03), the command processing module in the data flow control module receives the configuration information transmitted by the command FIFO to obtain the information required by the current operation: the method comprises the steps that an original data address, a read data address and a data length are read, and as configuration information of a command is required to be split into a plurality of addresses and the data length to be sent to a master interface, a command processing module splits the configuration information into a plurality of pieces according to a bus protocol and calculates the initial address and the data length of each piece, then the calculated original data address and data length are sent to the master interface 1, the calculated read data address and data length are sent to the master interface 2, and the data lengths sent to the two master interfaces are kept consistent;
s04), the master interface 1 receives the data address and the data length sent by the command processing module, starts data capture and returns data to the data flow control module;
s05), the master interface 2 receives the data address and the data length sent by the command processing module, starts data capture and returns data to the data flow control module;
s06), the data processing module in the data flow control module starts to compare and calculate the number of bits 0 turned over to bits and the number of bits 1 turned over to bits 0 bit by bit from the first address of the returned data, and outputs the number to the adder until the comparison of all the data of the current command is completed, and then outputs an effective end signal;
s07), while the step S05 is executed, the adder adds the output result of the data flow control module and the last accumulation result in real time, and outputs the current accumulation result, and when the data flow control module outputs a valid end signal, the accumulation result of the current adder is the turnover bit number of all data of the command;
s08), after receiving the effective ending signal, the response FIFO stores the accumulated result of the current adder;
s09), after the adder detects the valid end signal, the accumulated result is cleared to 0, the next calculation is waited to start, the next calculation is started when the start signal is valid, and the comparison operation is repeated until the calculation results of all commands are completed.
2. The method for counting the number of bits of 0 and 1 flip according to claim 1, wherein: step S04 is performed in parallel with step S05.
3. The method for counting the number of bits of 0 and 1 flip according to claim 1, wherein: the external CPU inquires whether the configured starting signal is valid or not through the control bus, and if not, the external CPU writes the configuration information and the starting signal into the configuration module.
4. The method for counting the number of bits of 0 and 1 flip according to claim 1, wherein: the external CPU checks the state of the response FIFO through the configuration module, and if the response FIFO is not empty, the response FIFO indicates that a valid result exists currently and can be read.
5. An apparatus for counting the number of bits flipped by 0 and 1, characterized in that: the device is used for executing the method of the statistic data 0 and 1 flip bit number in any one of claims 1-4, and comprises a configuration module, a command FIFO, a response FIFO, a data flow control module, an adder, a master interface 1 and a master interface 2, wherein the data flow control module comprises a command processing module and a data processing module, the configuration module is connected with a control bus and is used for receiving configuration information and starting signals written by an external CPU through the control bus, the command FIFO is connected between the configuration module and the command processing module and is used for receiving and storing the configuration information written by the configuration module and writing the configuration information into the command processing module, the command processing module calculates the storage address and the data length of original data and read data according to the configuration information, then the calculated original data address and data length signal are sent to a master interface 1, the calculated read data address and data length signal are sent to a master interface 2, the master interface 1 and the master interface 2 grasp corresponding data from a memory through a data bus according to the received data address and data length respectively, the grasped data are returned to a data processing module, the data processing module compares the data returned by the master interface 1 and the master interface 2 bit by bit, the number of bits 0 is turned over to be bits 1 and the number of bits 1 is turned over to be bits 0, an adder accumulates the number of bits 0 to be bits 1 and the number of bits 1 to be bits 0, and the accumulated result is written into a response FIFO; the configuration information comprises an original data address, a read data address and a data length.
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| US8639992B2 (en) * | 2011-05-16 | 2014-01-28 | GlobalFoundries, Inc. | Soft error rate detector |
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| US9419655B2 (en) * | 2014-04-04 | 2016-08-16 | Seagate Technology Llc | Error correction code (ECC) selection using probability density functions of error correction capability in storage controllers with multiple error correction codes |
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| CN109542668A (en) * | 2018-10-29 | 2019-03-29 | 百富计算机技术（深圳）有限公司 | Method of calibration, terminal device and storage medium based on NAND FLASH memory |
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